CN113922819A

CN113922819A - One-step two-bit successive approximation type analog-to-digital converter based on background calibration

Info

Publication number: CN113922819A
Application number: CN202111523333.9A
Authority: CN
Inventors: 邱政; 欧阳煜东; 孙黎棋
Original assignee: Zhejiang Lab
Current assignee: Zhejiang Lab
Priority date: 2021-12-14
Filing date: 2021-12-14
Publication date: 2022-01-11
Anticipated expiration: 2041-12-14
Also published as: CN113922819B

Abstract

The invention discloses a one-step two-bit successive approximation type analog-to-digital converter based on background calibration. Aiming at the application scenes of high speed and low power consumption, the novel successive approximation type analog-to-digital converter is innovative in that a reference level capacitor array in the structure of the novel successive approximation type analog-to-digital converter is only generated by one row of capacitor arrays, and compared with the traditional structure, the number of capacitors is reduced by half, and a one-step two-bit working mode can be realized. Based on the converter with the one-step two-bit structure, the invention provides a low-overhead redundancy correction method, and the method has strong transplanting characteristics. The invention facilitates the adoption of a double-input-end comparator to replace the traditional four-input-end comparator structure, thereby enabling the converter to have higher linearity. Aiming at the common mode voltage imbalance between the capacitor arrays in two steps, a novel common mode voltage background calibration method is provided. Aiming at the potential electric leakage problem caused by the high resistance node of the dynamic logic, the low electric leakage dynamic logic structure is provided to solve the electric leakage problem of the high-speed analog-digital converter realized by the advanced process.

Description

One-step two-bit successive approximation type analog-to-digital converter based on background calibration

Technical Field

The invention belongs to the field of integrated circuit design, and particularly relates to a one-step two-bit successive approximation type analog-to-digital converter based on background calibration.

Background

As the integrated circuit manufacturing technology is more advanced, the advantages of a successive approximation analog-to-digital converter (SAR ADC) with good process compatibility are gradually shown, which is popular with designers due to the characteristics of low power consumption and small area. In addition, the continuous reduction of transistor size and power rail voltage make it difficult to achieve high performance in conventional analog circuits such as operational amplifiers, while SAR ADCs are mainly composed of digital modules and are hardly limited by analog modules.

The conversion rate of the SAR ADC serial working mechanism is limited, and the power consumption and the area overhead of a Flash (Flash) and Pipeline (Pipeline) structure are large. Aiming at the problem that the conversion rate of a single SAR ADC is limited, high-speed structures such as a pipeline-SAR, a Flash-SAR, a time domain interleaved SAR and a one-step multi-Bit (N-Bit/Cycle) SAR emerge, and the compromise in multiple aspects of conversion rate, power consumption and area is realized.

The pure binary search algorithm has the least search times and the highest search efficiency, but lacks a fault-tolerant mechanism and is very sensitive to various non-ideal factors. By introducing the redundancy correction technology, the comparator and the margin voltage (V) of the SAR ADC can be relaxed_DAC) The established precision requirement improves the fault tolerance of the SAR ADC in the quantization process.

The traditional static digital logic has relatively large delay, and a dynamic logic technology based on Domino (Domino) logic appears for improving the overall work rate of the SAR ADC. However, in this technique, since the plurality of nodes are in a high impedance state, there is a risk of leakage.

A one-step two-Bit (2-Bit/Cycle) structure requires two types of capacitor arrays, namely: the successive approximation capacitor array (SDAC) and the reference level capacitor array (RDAC) respectively process an input signal and a reference level. But common mode level offset exists between the two capacitor arrays, so that calibration technology is needed to eliminate the common mode level offset between the two capacitor arrays.

Disclosure of Invention

The invention aims to provide a one-step two-bit successive approximation type analog-to-digital converter based on background calibration, aiming at the defects of the prior art in high-speed and low-power consumption application scenes. The invention provides a novel 2-Bit/Cycle SAR ADC structure based on a one-step two-Bit successive approximation type analog-to-digital converter (2-Bit/Cycle SAR ADC), a redundancy technology and a background calibration technology.

The purpose of the invention is realized by the following technical scheme: a one-step two-bit successive approximation type analog-to-digital converter based on background calibration comprises:

differential signal positive input endV _ipDifferential signal negative input terminalV _inReference level input terminal and its buffer circuit; the reference level comprises a common mode levelV _CMUpper reference levelV _refLower reference levelGND。

The quantization structure comprises three rows of capacitor arrays, a logic level switch array of the capacitor arrays and three two-input-end comparators.

Two rows of capacitor arrays SDAC for realizing successive approximation of differential signals are provided: row and differential signal positive input terminalV _ipThe SDAC connected is SDAC_pAnd the row of SDACs connected with the negative input end of the differential signal is SDAC_n(ii) a A bank of capacitor arrays RDAC for generating the reference levels; both SDAC and RDAC have consistent topology, capacitance weights.

The logic level switch array comprises two grid voltage bootstrap switches for signal sampling; the logic level switch array belongs to SDAC, and two rows of SDAC capacitor bottom plates are respectively connected with a positive input end and a negative input end of a differential signal through a grid voltage bootstrap switch; and the other is used for controlling the opening and closing of the top polar plates of the three rows of capacitor arrays and the common-mode level input end.

Three two-input comparators CMP, respectively₂、CMP₁、CMP₀(ii) a Wherein, CMP₂Positive input terminal and SDAC_nThe negative input end is connected with the RDAC; CMP (chemical mechanical polishing)₁Positive input terminal and SDAC_nConnected with the negative input terminal and SDAC_pConnecting; CMP (chemical mechanical polishing)₀The positive input terminal is connected with RDAC, the negative input terminal is connected with SDAC_pAre connected.

The digital logic comprises thermometer code-binary code conversion digital logic, SAR digital logic, minimum root mean square (LMS) algorithm realization digital circuit and redundancy correction circuit.

Further, the following are specific:

(1) the quantization structure comprises three rows of capacitor arrays, a logic level switch array and three comparators, wherein each capacitor array is composed of SDAC and RDAC, the topological structures and the capacitance weights of the SDAC and the RDAC are consistent, the SDAC is two rows, and the RDAC is one row. The quantization process is as follows:

(1.1) sampling stage, differential signal positive input terminalV _ipDifferential signal negative input terminalV _inWith SDAC in two rows of SDAC respectively_p、SDAC_nThe bottom plate of the capacitor is connected and the top plate of SDAC is connected to the common mode level input terminal V_CMConnecting; at the same time, the bottom plate of the RDAC capacitor is connected to the lower reference level input end GND, and the top plate is connected to V_CMAnd (4) electric potential.

(1.2) Charge redistribution stage, SDAC_p、SDAC_nThe capacitor top plate switch is turned off so that the top plate is in a high impedance state and the SDAC bottom plate is at a common mode levelV _CMAnd (4) connecting, wherein the information sampled by the SDAC bottom plate is transferred to the SDAC top plate and the SDAC_pThe potential of the top plate is2V _CM -V _ip，SDAC_nThe potential of the top plate is2V _CM -V _in(ii) a At the same time, the switch of the top plate of the RDAC capacitor is turned off, so that the top plate is in a high-impedance state, and the RDAC capacitor is in the RDACLSB+1、LSBAnd the bottom plate of the Dummy capacitor is switched to the upper reference levelV _refCausing the RDAC top plate level to rise1/4V _refAt this time, the potential of the RDAC top plate isV _CM +1/4V _ref。

(1.3) SDAC generated according to the charge redistribution in step (1.2)_p、SDAC_nRDAC top plate potential, first quantization is carried out, and three comparators CMP are carried out after quantization is finished₂、CMP₁、CMP₀Three-position thermometer code output correspondinglyT ₁、T ₂、T ₃Obtaining the highest bit by converting thermometer code-binary code into digital logicMSBAnd the second highest positionMSB-1 two-bit binary digital codeD ₁、D ₂(ii) a In the same way, inxThree comparators CMP after sub-quantization₂、CMP₁、CMP₀Three-position thermometer code output correspondinglyT _3x-2、T _3x-1、T _3xConverting to obtain the two-digit binary digital code of the highest bit and the second highest bit in the current unaffiliated digital codeD _2x-1、D _2x。

(1.4) according to step (1.3)T ₁、T ₂、T ₃Three-position thermometer code, control SDAC_p、SDAC_nAnd the logic level switching of the RDAC bottom plate is realized according to the following specific switching rule: SDAC controlled by weight of three-bit thermometer code_p、SDAC_nMiddle capacitor position (three high, middle, and low). If the thermometer code is1Then SDAC_pEnd-to-end weighted capacitor andV _refconnection, SDAC_nEnd-to-end weighted capacitor andGNDconnecting; if the thermometer code is0Then SDAC_pEnd-to-end weighted capacitor andGNDconnection, SDAC_nEnd-to-end weighted capacitor andV _refand (4) connecting.

And the RDAC drives the bottom plate of the corresponding capacitor in the charge redistribution stageGNDSwitch toV _refThe potential of the RDAC top plate before the first quantization is made to beV _CM +

V _ref(ii) a After the first quantization, the RDAC is matched with the bottom plate of the capacitorV _refSwitch toGNDThe potential of the top plate is made to be equal toV _CM +

V _ref. If there is a further quantization step, the RDAC top plate potential isV _CM +1/64V _ref、V _CM +1/256V _ref…, and so on, after the x-1 quantization, the RDAC is matched with the bottom plate of the capacitorV _refSwitch toGNDSo that the potential of the RDAC top plate before the x-th quantization isV _CM +

V _ref。

(1.5) first quantizing the generated thermometer code according to the step (1.4)T ₁、T ₂、T ₃In SDACp, SDAC_nThe RDAC top plate generates new potential and then carries out second quantization to generate thermometer codeT ₄、T ₅、T ₆。

And (1.6) repeating the steps (1.4) - (1.5) by analogy until all the digital codes are obtained by quantization.

(2) Based on the SDAC and RDAC structures in the step (1), a redundancy correction technology for a 2-Bit/Cycle SAR ADC is provided, and on the premise of N Bit precision and 1 Bit redundancy Bit, a specific implementation method of redundancy correction logic comprises the following steps:

(2.1) carrying out capacitance grouping according to a binary rule, wherein the capacitance weight distribution on the SDAC and RDAC principles is as follows:2 ^N-2 C、2 ^N ^-3 C、2 ^N-4 C、2 ^N-5 C、2 ^N-5 C、···、4C、2C、1C、1Cwherein2 ^N-5 COccur twice, i.e. with redundant bit weights of2 ^N-5 C LSB。

(2.2) according to the 2-Bit/Cycle SAR ADC, quantizing and outputting 3-Bit thermometer codes in each step to carry out capacitance splitting, and actually carrying out capacitance splitting on the SDAC and the RDACThe weight distribution is as follows;2 ^N-3 C、2 ^N-3 C、2 ^N-3 C、2 ^N-5 C、2 ^N-5 C、2 ^N-5 C、··· 、16C、16C、16C、4C、4C、4C、1C、1C、1C、1C。

(3) common mode voltage on capacitor array SDAC and RDACV _CM、V _CMSAn error value exists, and the error value is recorded aserrorThen, thenerrorCan be expressed as:

(1)

wherein the content of the first and second substances,

、

、

respectively representing SDAC_p、SDAC_nRDAC top plate residual voltage is defined as:

(2)

(3)

(4)

after the quantization step is finished, the common mode offset voltage starts to be calibrated, so that the common mode offset voltage can be calibratedV _CMSGradual approximationV _CM. In each cycleThe digital calibration circuit based on Least Mean Square (LMS) algorithm performs an iterative calculation, and the calculation result is fed back to the analog circuit for adjustmentV _CMSLevel value of (d). Common mode voltage on RDACV _CMSThe LMS iterative formula of (a) is:

(5)

(6)

wherein the content of the first and second substances,μthe convergence factor determines the accuracy and speed of convergence.E(V _CMP1 )AndE(V _CMP2 )are respectively comparators CMP₁And comparator CMP₂The expected values of the results are compared in a plurality of successive cycles.

(4) In order to inhibit the electric leakage problem of the dynamic logic, a positive feedback cross coupling structure is introduced at an output node on the basis of the traditional dynamic logic unit, so that the electric charge leakage can be effectively prevented, and the logic change of an output level is avoided.

The beneficial technical effects of the invention are as follows:

first, 4-row capacitor array (SDAC) required for conventional 2-Bit/Cycle SAR ADC_p、SDAC_n、RDAC_p、RDAC_n) In contrast, only 3 rows of capacitor arrays are required in the capacitor array required in the present invention (SDAC)_p、SDAC_nRDAC) under the same precision index, the area of the capacitor array can be effectively reduced; SDAC_p、SDAC_nThe RDAC and the RDAC have completely consistent structures, and the redundancy correction technology is conveniently realized; in addition, SDAC_p、SDAC_nThe capacitor in the RDAC is split according to the output thermometer code, the thermometer code directly controls the logic switch, and the Dynamic Element Matching (DEM) technology is conveniently realized while the delay of converting the thermometer code into the binary code in the asynchronous circuit is eliminated;

secondly, the redundancy correction technology adopted in the invention has simple principle, easy realization, universal characteristic, no need of customized design, strong portability and design time saving;

third, common mode level to RDAC by LMS algorithmV _CMSThe problem of nonlinear error caused by maladjustment between SDAC and RDAC in the one-step two-bit successive approximation type analog-to-digital converter can be effectively solved by calibration;

fourth, by adding a positive feedback cross-coupling structure to the conventional dynamic logic unit, charge leakage can be effectively prevented, and abnormal logic change of the output level of the dynamic logic circuit in the latch phase is avoided.

Drawings

FIG. 1 is a block diagram of a 2-Bit/Cycle SAR ADC module according to the present invention;

FIG. 2 is a schematic diagram of a 2-Bit/Cycle SAR ADC capacitor array structure and a logic switch connection mode in the invention;

FIG. 3 is a schematic diagram of the working timing sequence of a 2-Bit/Cycle SAR ADC in the present invention;

FIG. 4 is a schematic diagram of a first step switching method of a 2-Bit/Cycle SAR ADC according to the present invention, taking 4 bits as an example;

FIG. 5 is a schematic diagram of a second step switching method corresponding to a thermometer code 000 with 4 bits as an example for a 2-Bit/Cycle SAR ADC in the present invention;

FIG. 6 is a schematic diagram of a second step switching method corresponding to thermometer code 001 with 4 bits as an example for a 2-Bit/Cycle SAR ADC in the present invention;

FIG. 7 is a schematic diagram of a second step switching method corresponding to a thermometer code 011 by using 4 bits as an example for a 2-Bit/Cycle SAR ADC in the present invention;

FIG. 8 is a schematic diagram of a second step switching method corresponding to a thermometer code 111 of a 2-Bit/Cycle SAR ADC according to the present invention, taking 4 bits as an example;

FIG. 9 is a graph of offset voltage and ADC performance parameters as a function of calibration iterations;

FIG. 10 is a schematic diagram of dynamic SAR logic and switch control logic;

FIG. 11 is a schematic diagram of a transistor level structure of a dynamic SAR logic unit;

fig. 12 is a schematic diagram showing comparison of output waveforms of dynamic logic units before and after the anti-leakage structure is added.

Detailed Description

The innovation of the invention is that: compared with the traditional 2-Bit/Cycle SAR ADC, the reference level capacitor array in the novel SAR ADC structure is only generated by one row of capacitor arrays (RDAC), and the number of capacitors is reduced by half compared with that of the traditional structure; secondly, a double-input-end comparator is adopted to replace a traditional four-input-end comparator structure, so that the SAR ADC has higher linearity; thirdly, based on the SDAC and RDAC structures in the design, a low-overhead redundancy correction method is provided, and the method has strong transplanting characteristics; fourthly, aiming at the common mode voltage imbalance between the SDAC and the RDAC in the 2-Bit/Cycle SAR ADC, a novel common mode voltage calibration method is provided; and fifthly, aiming at the problems of high resistance nodes and potential electric leakage of the dynamic logic, a low-electric leakage dynamic logic structure is provided.

The present invention will be further described with reference to specific examples, but the embodiments of the present invention are not limited thereto, and hereinafter, unless otherwise specified, the implementation method of 2-Bit/Cycle SAR ADC with 10-Bit valid bits and 1-Bit redundancy is default.

As shown in fig. 1, the one-step two-bit successive approximation type analog-to-digital converter based on background calibration of the present invention includes the following main modules:

(1) positive and negative input ends of differential signalV _ip、V _inInput terminal of common mode levelV _CMAnd corresponding reference level input end on buffer circuitV _refAnd corresponding buffer circuit, lower reference level input terminalGND。

(2) Two kinds of grid voltage bootstrap switches are used for signal sampling.

(3) Three-row capacitor array SDAC_p、SDAC_nRDAC, and its logic level switch array. Two rows of capacitor arrays SDAC for realizing successive approximation of differential signals are provided: row and differential signal positive input terminalV _ipThe SDAC connected is SDAC_pAnd the row of SDACs connected with the negative input end of the differential signal is SDAC_n(ii) a A bank of capacitor arrays RDAC for generating the reference levels. SDAC andthe topological structure and the capacitance weight of the RDACs are consistent.

(4) Three two-input comparator CMP₂、CMP₁、CMP₀. Wherein, CMP₂Positive input terminal and SDAC_nConnected, the negative input terminal is connected with RDAC, and the output code is marked as T₁；CMP₁Positive input terminal and SDAC_nConnected with the negative input terminal and SDAC_pWhen they are connected, the output code is recorded as T₂；CMP₀The positive input terminal is connected with RDAC, the negative input terminal is connected with SDAC_pWhen they are connected, the output code is recorded as T₃。

(5) Digital logic comprising successive approximation logic, LMS calibration algorithm logic, redundancy correction logic. The successive approximation logic comprises thermometer code-binary code conversion digital logic and SAR digital logic; the LMS calibration algorithm logic implements a digital circuit for the LMS algorithm; the redundancy correction logic is a redundancy correction circuit.

As shown in FIG. 2, three rows of capacitor arrays SDAC_p、SDAC_nRDAC, and its logic level switch array, specifically are: firstly, according to the thermometer code, splitting the corresponding weight capacitor into two sub-capacitors with the same size. Second, SDAC_p、SDAC_nTop polar plate potential is referenced by common modeV _CMControlling; while SDAC_p、SDAC_nThe bottom plate potential is determined by three reference levels: upper reference levelV _refLower reference levelGNDCommon mode reference levelV _CMControl, and also the differential signal input ends (V _ipOrV _in) Are connected. RDAC top plate common mode reference levelV _CMControlled while the RDAC bottom plate potential is controlled by an upper reference levelV _refLower reference levelGNDAnd (5) controlling.

As shown in fig. 3, the ADC operation timing in the present invention specifically includes: quantization and SDAC of 11 bits (including 10-bit valid bit and 1-bit redundant bit) after multi-step operation_p、SDAC_nCommon mode level calibration between RDACs.

To illustrate SDAC_p、SDAC_nThe switching rule of the RDAC top polar plate and the RDAC bottom polar plate takes 4-bit precision as an example, and the invention quantizes a capacitance switching example of a 4-bit capacitance array, and specifically comprises the following steps:

[ sampling procedure ]

As shown in FIG. 4, during sampling, the capacitor array SDAC_pThe bottom plate is connected with an input signalV _ipCapacitor array SDAC_nThe bottom plate is connected with an input signalV _inSDAC top plate connected to common mode reference levelV _CM；RDAC_pBottom plate and lower reference levelGNDConnected, RDAC_pTop plate and common mode reference levelV _CMAre connected.

[ converting cycle step ]

Taking 4 bits as an example, the capacitor array weight arrangement will be described, specifically:

in binary arrangement, the capacitor array weights are respectively8C、4C、2C、1C、1C. Considering that each step of output in the invention is 3-bit thermometer code, the binary capacitor array is grouped two by two from high to low, namely:8Cand4C、2Cand1C、1Cthen, the high order bits in one group are divided into two, so that the capacitor array in the invention is4C、4C、4C、1C、1C、1C、1CAs shown in fig. 4.

Taking 4 bits as an example, the switching timing of the capacitor array will be described specifically as follows:

step one, charge redistribution. As shown in fig. 4, SDAC_p、SDAC_nThe capacitor top plate switch is turned off, so that the SDAC top plate is in a high-impedance state, and the SDAC bottom plate is in a common-mode reference levelV _CMAnd (4) connecting, wherein the information sampled by the SDAC bottom plate is transferred to the SDAC top plate and the SDAC_pThe potential of the top plate is2V _CM -V _ip，SDAC_nThe potential of the top plate is2V _CM -V _in. At the same time, the switch of the top plate of the RDAC capacitor is switched off, so that the top plate of the RDAC capacitor is in a high-impedance state, and the middle and lower positions of the RDAC capacitor are lowLSB+1Lowest positionLSBDummy capacitor Dummy bottom electrodeThe plate is switched toV _refCausing the RDAC top plate level to rise1/4V _refAt this time, the potential of the RDAC top plate isV _CM +1/ 4V _ref。

Step two, SDAC generated according to the charge redistribution stage of step one_p、SDAC_nAnd the RDAC top plate level, and carrying out first-step quantization. The potentials compared by the 3 comparators are as follows:2V _CM -V _inandV _CM +1/4V _ref、2V _CM -V _ipand2V _CM -V _in、V _CM + 1/4V _refand2V _CM -V _ipcan be equivalently used as input signalV _ipAre respectively connected with3/4V _ref、1/2V _ref、1/4V _refComparing to obtain a three-position thermometer codeT ₁、T ₂、T ₃The two-bit binary code can be obtained by the circuit for converting the thermometer code into the binary codeD ₁、D ₂。

Step three, according to the thermometer codeT ₁、T ₂、T ₃Switching SDAC_p、SDAC_nMost significant MSB and next most significant MSB-1 (corresponding to the embodiment)4C、 4C

、

4C) The high two-bit capacitance of (2) while switching the RDAC capacitance; the method specifically comprises the following steps:

first, as shown in FIG. 5, assume thermometer codes output by three comparatorsT ₁、T ₂、T ₃Is composed of000Corresponding binary codeD ₁、D ₂Is composed of00At this time, SDAC is controlled_pFirst group of capacitors4C、4C、4CThe bottom electrode plates are all connected withGNDConnected, SDAC_nFirst group of capacitors4C、4C、4CThe bottom electrode plates are all connected withV _refConnecting; while in RDAC1CAndV _refconnected with the other capacitorsGNDWhen connected, the RDAC generates a reference voltage ofV _CM +V _ref /16。

② As shown in FIG. 6, suppose thermometer code outputted by three comparatorsT ₁、T ₂、T ₃Is composed of001Corresponding binary codeD ₁、D ₂Is composed of01At this time, SDAC is controlled_pFirst group of capacitors4C、4C、4CThe bottom electrode plates are respectively connected withGND、GND、V _refConnected, SDAC_nFirst group of capacitors4C、4C、4CThe bottom electrode plates are respectively connected withV _ref、V _ref、GNDConnecting; while in RDAC1CAndV _refconnected with the other capacitorsGNDWhen connected, the RDAC generates a reference voltage ofV _CM +V _ref /16。

(iii) assume thermometer codes output by three comparators as shown in FIG. 7T ₁、T ₂、T ₃Is composed of011Corresponding binary codeD ₁、D ₂Is composed of10At this time, SDAC is controlled_pFirst group of capacitors4C、4C、4CThe bottom electrode plates are respectively connected withGND、V _ref、V _refConnected, SDAC_nFirst group of capacitors4C、4C、4CThe bottom electrode plates are respectively connected withV _ref、GND、GNDConnecting; while in RDAC1CAndV _refconnected with the other capacitorsGNDWhen connected, the RDAC generates a reference voltage ofV _CM +V _ref /16。

(iv) assuming thermometer codes output by three comparators as shown in FIG. 8T ₁、T ₂、T ₃Is composed of111Corresponding binary codeD ₁、D ₂Is composed of11At this time, SDAC is controlled_pFirst group of capacitors4C、4C、4CThe bottom electrode plates are all connected withV _refConnected, SDAC_nFirst group of capacitors4C、4C、4CThe bottom electrode plates are all connected withGNDConnecting; while in RDAC1CAndV _refconnected with the other capacitorsGNDWhen connected, the RDAC generates a reference voltage ofV _CM +V _ref /16。

Step four, switching the logic level of the bottom plate of the capacitor according to the step three to cause the top plate to generate a voltage change valueV _XResult in SDAC_p、SDAC_nAnd generating a new level by the RDAC top plate to carry out the second step of quantization. 3 comparators CMP₂、CMP₁、CMP₀The potentials compared respectively are:2V _CM -V _in -V _XandV _CM +1/16V _ref、2V _CM -V _ip +V _Xand2V _CM -V _in -V _X、V _CM +1/16V _refand2V _CM -V _ip +V _Xcan be equivalently used as input signalV _ipAre respectively connected with9/16V _ref +V _X、1/2V _ref +V _X、7/16V _ref +V _XComparing to obtain a three-position thermometer codeT ₄、T ₅、T ₆Thereby obtaining a two-bit binary codeD ₃、D ₄。

If the resolution (quantization digit) is improved, the analogy can be carried out according to the steps of one, two, three and four.

[ implementation of redundancy correction technique ]

By taking 10 bits as an example, the implementation of the 2-Bit/Cycle SAR ADC redundancy correction capacitor array and the algorithm is illustrated, and FIG. 2 shows a 10-Bit 2-Bit/Cycle SAR ADC and supports a capacitor array (SDAC) with 1-Bit redundancy bits_p、SDAC_nRDAC), the capacitance weights are respectively as follows:128、128、128、32、32、32、16、16、16、4、4、4、1、1、1、 1 table 1 shows the capacitance and redundancy correction range for each switching step.

Table 1: 10-bit precision redundancy 1-bit redundancy correction range

[ capacitive array common mode level calibration technique implementation ]

The implementation method of the 2-Bit/Cycle SAR ADC capacitor array common-mode level calibration technology is described by taking N =10 Bit precision and containing 1-Bit redundant Bit as an example. When the quantization process proceeds to the 6 th quantization, a comparator CMP is applied₀Quantizing the 11 th bit, and applying comparator CMP₁And CMP₂Respectively additionally compare once, the result of comparison is saved and is realized the calibration of common mode level in digital calibration circuit, and the concrete principle is:

assuming common mode voltage on capacitor arrays SDAC and RDACV _CM、V _CMSAn error value exists, and the error value is recorded aserrorThen, thenerrorCan be expressed as:

(1)

wherein the content of the first and second substances,

、

、

(2)

(3)

(4)

wherein the content of the first and second substances,V _CMSis the reset reference voltage of the actual RDAC,

ideal values of reset reference voltage and reset reference voltage for real RDACV _CMAfter each round of quantization step is finished, the common mode offset voltage starts to be calibrated, so that the common mode offset voltage is enabled to be calibratedV _CMSGradual approximationV _CM. In each quantization period, a digital calibration circuit based on Least Mean Square (LMS) algorithm performs an iterative calculation, and the calculation result is fed back to the analog circuit for adjustmentV _CMSLevel value of (d). Common mode voltage on RDACV _CMSThe LMS iterative formula of (a) is:

(5)

(6)

wherein the content of the first and second substances,μthe convergence factor determines the accuracy and speed of convergence.E(V _CMP1 )AndE(V _CMP2 )are respectively comparators CMP₁And CMP₂The expected values of the results are compared over a number of successive cycles, n representing the nth iteration.

After a number of iterations of successive cycles,V _CMSeventually, it will tend to a stable level where the offset voltage between RDAC and SDAC approaches zero, completing the calibration. FIG. 9 (a) is a variation process of the offset voltage between SDAC and RDAC in the iterative process of the calibration circuit; fig. 9 (b) shows the variation process of the ADC important index parameters signal-to-noise ratio (SNDR) and Spurious Free Dynamic Range (SFDR) in the iterative process. As the ADC continues to work, the offset voltage is continuously reduced and eventually becomes constant as the iteration data is accumulated, and the SFDR and SNDR are also increased and follow the trend of the offset voltage.

[ implementation of anti-leakage dynamic logic cell ]

The dynamic logic circuit has higher working frequency than the static logic circuit, so the dynamic logic circuit is suitable for high-speed ADC.

FIG. 10 shows a dynamic logic circuit diagram, each dynamic logic celliIt is necessary to quickly change the output logic level CMP of the comparator_PAnd CMP_NDecoded and latched to the output nodes P of the dynamic logic cells respectivelyAnd N. The logic circuit for completing decoding needs to convert P into PAnd NThe signal is latched and provided to the switch control logic module. If in one quantization period, P is caused by leakage of dynamic logic unitAnd NThe ADC will go into abnormal operation if the signal of (2) has a transition after latching.

As shown in FIG. 11, to prevent dynamic logic cells, due to M_p7Pipe, M_p8Leakage of the transistor (CMOS transistor) to cause the output node N、PTransition from a logic low level to an indeterminate state, introducing M_n4,LPipe, M_n5,LA tube (CMOS tube). Let P be asserted after comparator determinationIs high level, NAt a low level, M_n4,LThe tube is conducted so that M_n5,LThe tube is cut off. It can be seen that even M_p7The tube has leakage due to M_n4,LThe tube is conducted, and the leaked charges are not at the node NIs accumulated but passes through M_n4,LThe tube is discharged to the ground, thereby ensuring NCorrectness of logic low level. FIG. 12 is a comparison graph of time domain waveforms of the leakage-resistant dynamic logic circuit (right) and the conventional dynamic logic circuit (left) according to the present invention, and due to the leakage-resistant design, the dynamic logic circuit can well latch P in a quantization periodAnd NThe signal is not affected by the leakage.

Compared with the traditional one-step two-bit successive approximation type analog-to-digital converter which needs 4 rows of capacitor arrays, the invention only needs 3 rows of capacitor arrays, and the topological structures and the capacitor weights of the SDAC and the RDAC are completely consistent, thereby being convenient for realization, transplantation and expansion; meanwhile, the redundancy correction technology benefits from the characteristics of completely consistent structures of SDAC and RDAC, is simple to implement and has high portability. The invention adopts the principle of minimum root mean square algorithm to calibrate the common mode level offset of the top plate between the SDAC and the RDAC. Furthermore, the SAR logic is formed by adopting an anti-leakage dynamic logic unit, specifically, a cross-coupling structure is introduced at the output structure of the dynamic logic unit, the size of a transistor of the cross-coupling structure is smaller than that of other transistors, and an overlarge parasitic capacitance cannot be introduced to reduce the speed of a logic circuit.

Claims

1. The utility model provides a one-step two successive approximation type analog-to-digital converter based on backstage calibration which characterized in that includes:

differential signal positive input endV _ipDifferential signal negative input terminalV _inReference level input terminal and its buffer circuit; the reference level comprises a common-mode reference levelV _CMUpper reference levelV _refLower reference levelGND；

The quantization structure comprises three rows of capacitor arrays, a logic level switch array of the capacitor arrays and three comparators with two input ends;

two rows of capacitor arrays SDAC for realizing successive approximation of differential signals are provided: row and differential signal positive input terminalV _ipThe SDAC connected is SDAC_pOne row of the differential signal input terminals is connected with the differential signal negative input terminalThe SDAC of (A) is an SDAC_n(ii) a A bank of capacitor arrays RDAC for generating new levels; the topology and capacitance weights of both SDAC and RDAC are consistent;

three two-input comparators CMP, respectively₂、CMP₁、CMP₀(ii) a Wherein, CMP₂Positive input terminal and SDAC_nThe negative input end is connected with the RDAC; CMP (chemical mechanical polishing)₁Positive input terminal and SDAC_nConnected with the negative input terminal and SDAC_pConnecting; CMP (chemical mechanical polishing)₀The positive input terminal is connected with RDAC, the negative input terminal is connected with SDAC_pConnecting;

2. The one-step two-bit successive approximation type analog-to-digital converter based on background calibration of claim 1, wherein the logic level switch array comprises two kinds of gate voltage bootstrap switches for signal sampling; the logic level switch array belongs to SDAC, and two rows of SDAC capacitor bottom plates are respectively connected with a positive input end and a negative input end of a differential signal through a grid voltage bootstrap switch; and the other is used for controlling the opening and closing of the top polar plates of the three rows of capacitor arrays and the common-mode level input end.

3. The background calibration-based one-step two-bit successive approximation type analog-to-digital converter according to claim 1, wherein the quantization process comprises:

(1) sampling phase, differential signal positive and negative input terminalsV _ip、V _inRespectively connected with SDAC_p、SDAC_nCapacitor bottom plate connected, SDAC_p、SDAC_nCapacitor top plate and common mode reference level V_CMCommunicating; meanwhile, the bottom plate of the RDAC capacitor is connected to the lower reference level GND, and the top plate of the RDAC capacitor is connected to the common mode reference level V_CM；

(2) Charge redistribution phase, SDAC_p、SDAC_nThe capacitor top plate switch is turned off to a high impedance state and the SDAC bottom plate is coupled to a common mode reference levelV _CMAnd (4) connecting, wherein the information sampled by the SDAC bottom plate is transferred to the SDAC top plate and the SDAC_pThe potential of the top plate is2V _CM -V _ip，SDAC_nPotential of the top plate is 2V _CM-V _in(ii) a Meanwhile, the top plate switch of the RDAC capacitor is switched off and is in a high-impedance state, and the bottom plates of the secondary low-order capacitor, the lowest-order capacitor and the dummy capacitor in the RDAC are switched to the upper reference levelV _refCausing the RDAC top plate level to rise

V _refAt this time, the potential of the RDAC top plate isV _CM +

V _ref；

(3) SDAC generated according to charge redistribution in step (2)_p、SDAC_nRDAC top plate potential, first quantization is carried out, and three comparators CMP are carried out after quantization is finished₂、CMP₁、CMP₀Correspondingly outputting a three-digit thermometer code, and converting digital logic through thermometer code-binary code to obtain a two-digit binary digital code of the highest bit and the next highest bit in the current unaffiliated digital codes;

(4) controlling the SDAC according to the three-digit thermometer code generated by the current quantization in the step (3)_p、SDAC_nRDAC bottom plate logic level switching in SDAC_p、SDAC_nGenerating a new potential by the RDAC top plate;

(5) repeating the steps (3) to (4) according to the SDACp and the SDAC_nAnd carrying out next quantization on the current potential of the RDAC top plate, and generating a new three-bit thermometer code by the three comparators and converting the thermometer code into a binary digital code until the quantization is completed to obtain all digital codes.

4. The background calibration-based one-step two-bit successive approximation type analog-to-digital conversion of claim 3The device is characterized in that in the step (4), the weight of the three-bit thermometer code corresponds to the SDAC_p、SDAC_nA medium capacitance position; if the thermometer code is 1, then SDAC_pEnd-to-end weighted capacitance and upper reference levelV _refConnection, SDAC_nEnd-to-end weighted capacitor andGNDconnecting; if the thermometer code is 0, then SDAC_pEnd-to-end weighted capacitor andGNDconnection, SDAC_nEnd-to-end weighted capacitor andV _refconnecting;

RDAC top plate potential before first quantization isV _CM +

V _ref(ii) a And in analogy, after the x-1 th quantization, the RDAC corresponds to the bottom plate of the capacitorV _refSwitch toGNDSo that the potential of the RDAC top plate before the x-th quantization isV _CM +

V _ref。

5. The background calibration-based one-step two-bit successive approximation type analog-to-digital converter according to claim 3, wherein based on SDAC and RDAC capacitor arrays with completely consistent topological structures and capacitance weights, the redundancy correction logic under the premise of N-bit precision and 1-bit redundancy bit comprises:

and (3) carrying out capacitance grouping according to a binary rule, wherein the capacitance weight distribution on the SDAC and RDAC principles is as follows:2 ^N-2 C、2 ^N-3 C、2 ^N-4 C、2 ^N-5 C、2 ^N-5 C、···、4C、2C、1C、1Cwherein2 ^N-5 CTwo occurrences, representing a redundant bit weight of2 ^N-5 LSB；

According to a one-step two-bit successive approximation type analog-to-digital converter, quantizing each step to output a 3-bit thermometer code, and splitting a capacitor, wherein the capacitor weight is actually distributed in SDAC and RDAC;2 ^N-3 C、2 ^N-3 C、2 ^N-3 C、2 ^N-5 C、2 ^N-5 C、2 ^N-5 C、2 ^N-6 C、2 ^N-6 C、2 ^N- ⁶ C、··· 、4C、4C、4C、1C、1C、1C、1C。

6. the background calibration-based one-step two-bit successive approximation type analog-to-digital converter according to claim 3, wherein actual common mode voltage values obtained by up-sampling SDAC and RDAC of two capacitor arraysV _CMSAnd a theoretical common mode reference levelV _CMWhen error value exists, after each round of quantization is finished, the common mode offset voltage starts to be calibrated, so that the actual common mode voltage valueV _CMSGradual approximation to theoretical common mode reference levelV _CM(ii) a In each quantization period, the digital calibration circuit based on the minimum root mean square algorithm performs one-time iterative calculation, and the calculation result is fed back to the analog control circuit for adjustmentV _CMSA level; after a number of successive quantization periods,V _CMSgradually settling to bring the offset voltage between SDAC and RDAC to zero, completing the calibration.

7. The one-step two-bit successive approximation type analog-to-digital converter based on background calibration as claimed in claim 1, wherein in order to suppress the leakage problem of the dynamic logic, a positive feedback cross-coupling structure is introduced at the output structure of the dynamic logic unit to prevent charge leakage and avoid the logic change of the output level in the latch phase.