CN114614821B - SAR ADC offset error correction method and circuit based on differential structure - Google Patents
SAR ADC offset error correction method and circuit based on differential structure Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
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- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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Abstract
The invention provides a SAR ADC offset error correction method and circuit based on a differential structure, wherein the correction method comprises the following steps: under the drive of a correction logic module, N times of logic switching and judgment are carried out on auxiliary correction capacitors in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array, so that N-bit correction result information is obtained; encoding the correction result information by using a correction logic module to obtain compensation direction information and a correction compensation value; the compensation direction information characterizes the type of compensation; the correction compensation value characterizes the magnitude of the compensated voltage value; and in a normal working stage, correcting the ADC offset error according to the correction compensation value and the correction compensation direction information output by the correction logic module.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a SAR ADC offset error correction method and circuit based on a differential structure.
Background
Because the layout of the chip is difficult to realize complete symmetry of the layout and the wiring, the circuits such as the comparator and the like have process mismatch, the devices have processing deviation in the chip production and manufacturing process, and the disturbance on the circuit board in the application scene is introduced, so that the ADC can generate offset errors. Along with the increasing requirement on ADC precision, the influence of circuit offset and other deviations on ADC performance is more and more obvious, and the offset of the ADC must be corrected and additionally compensated under the high-precision application scene. The current commonly used SAR ADC imbalance correction method mainly comprises the following steps: the offset voltage is compensated and eliminated by adjusting the common mode level of the comparator through the adjustable resistor array, adopting a digital correction method and adopting an additional auxiliary correction capacitor DAC array.
The scheme of adjusting the offset voltage of the ADC through the adjustable resistor array is simple in logic, but the resistor array can introduce additional static power consumption; the digital correction method does not need additional auxiliary correction resistor and capacitor, can reduce the circuit area, but needs complex digital logic design and has convergence problem; the correction method adopting the auxiliary electric correction capacitor array has no static power consumption and no convergence problem. The correction circuit adopting the auxiliary correction capacitor array is of a single-ended structure at present and is easily influenced by common-mode interference and noise which change along with application environment.
Disclosure of Invention
The invention provides a SAR ADC offset error correction method and circuit based on a differential structure, which are used for solving the problem of ADC offset error caused by dynamic common mode interference and noise in chip manufacturing process deviation and application environment change.
According to a first aspect of the present invention, there is provided a method for SAR ADC offset error correction based on a differential structure, comprising:
under the drive of a correction logic module, N times of logic switching and judgment are carried out on auxiliary correction capacitors in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array, so that N-bit correction result information is obtained; the P auxiliary correction capacitor array and the N auxiliary correction capacitor array comprise N auxiliary correction capacitors, and N is a positive integer;
encoding the correction result information by using a correction logic module to obtain compensation direction information and a correction compensation value; the compensation direction information characterizes the type of compensation; the correction compensation value characterizes the magnitude of the compensated voltage value;
and in a normal working stage, correcting the ADC offset error according to the correction compensation value and the correction compensation direction information output by the correction logic module.
Optionally, upper polar plates of all auxiliary correction capacitors in the P auxiliary correction capacitor array are directly connected; the upper polar plates of all auxiliary correction capacitors in the N auxiliary correction capacitor arrays are directly connected.
Optionally, the capacitance values of the N auxiliary correction capacitors in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array all satisfy: sequentially increasing from low level to high level by the power of 2; capacitance value Ca [ i ] of ith capacitor in array]Is taken from (a)The values are: ca [ i ]]＝2 i-1 Cu, wherein Cu represents a unit capacitance, i is a positive integer, and i is more than or equal to 1 and less than or equal to n.
Optionally, the P auxiliary correction capacitor array and the N auxiliary correction capacitor array each include a low-order auxiliary capacitor, and the capacitance Ca 0 of the low-order auxiliary capacitor has the following value: ca [0] =cu, where Cu represents a unit capacitance.
Optionally, the n times of logic switching and judging are performed sequentially from the highest auxiliary capacitor to the lowest auxiliary capacitor, and the numerical value of the corresponding bit in the correction result information is updated after each time of logic switching and judging.
Optionally, each logic switching and judging specifically includes:
under the drive of a correction logic module, upper polar plates of all auxiliary capacitors in the P auxiliary correction capacitor array are connected to a first end of a comparator to be used as a first input signal of the comparator; connecting upper plates of all auxiliary capacitors in the N auxiliary correction capacitor array to a second end of the comparator as a second input signal of the comparator;
the lower electrode plates of auxiliary capacitors of corresponding bits in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array are controlled to be connected to a specified voltage signal;
and obtaining the value of the corresponding bit of the correction result information according to the output result of the comparator.
Optionally, the specified voltage signal is: the first reference voltage or the second reference voltage or the common mode level.
Optionally, the correction logic module is used for encoding the correction result information to obtain compensation direction information and a correction compensation value; the method specifically comprises the following steps:
determining the compensation direction information according to the highest bit of the n-bit correction result information;
and determining the correction compensation value according to the n-bit correction result information and the compensation direction information. Optionally, determining the compensation direction information according to the highest bit of the n-bit correction result information specifically includes:
when the highest bit cal [ n-1] of the correction result information is 1, the compensation direction information is a first compensation direction; the first compensation direction represents a positive compensation direction;
when the highest bit cal [ n-1] of the correction result information is 0, the compensation direction information is a second compensation direction; the second compensation direction represents a negative compensation direction;
wherein the binary value of n bits cal [ n-1:0] represents the correction result information, and cal [ n-1] represents the most significant bit of the correction result information.
Optionally, determining the correction compensation value according to the n-bit correction result information and the compensation direction information specifically includes:
when the compensation direction information is the first compensation direction, the correction compensation value cal_com [ n-1:0] is obtained according to the following formula:
cal_com[n-1:0]＝cal[n-1:0]-2 n-1 ；
when the compensation direction information is the second compensation direction, the correction compensation value cal_com [ n-1:0] is obtained according to the following formula:
cal_com[n-1:0]＝2 n-1 -cal[n-1:0]；
wherein the binary value of n bits cal_com [ n-1:0] represents the correction compensation value.
Optionally, correcting the ADC offset error according to the correction compensation value and the correction compensation direction information output by the correction logic module specifically includes: and determining a voltage signal accessed by a lower polar plate of each auxiliary correction capacitor in the P auxiliary correction array and the N auxiliary correction array according to the value of the corresponding bit in the correction compensation value.
Optionally, the determining the voltage signal accessed by the lower polar plate of each auxiliary correction capacitor in the P auxiliary correction array and the N auxiliary correction array specifically includes:
a certain position of the correction compensation value is 0, and the lower polar plate of the corresponding auxiliary correction capacitor in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array is connected with a common mode level;
if a certain bit of the correction compensation value is 1, then:
when the compensation direction information is the first compensation direction, the lower electrode plate of the auxiliary correction capacitor array representing P is connected with a first reference voltage, and the lower electrode plate of the auxiliary correction capacitor array representing N is connected with a second reference voltage;
and when the compensation direction information is the second compensation direction, the lower electrode plate of the auxiliary correction capacitor of the characterization P auxiliary correction capacitor array is connected with the second reference voltage, and the lower electrode plate of the auxiliary correction capacitor of the N auxiliary correction capacitor array is connected with the first reference voltage.
According to a second aspect of the present invention, there is provided a SAR ADC offset error correction circuit based on a differential structure, which is applied to the correction method provided in the first aspect of the present invention, including:
the auxiliary correction capacitor array comprises a P auxiliary correction capacitor array and an N auxiliary correction capacitor array;
the P auxiliary correction capacitor array and the N auxiliary correction capacitor array comprise N auxiliary correction capacitors and a first voltage selection unit; wherein n is a positive integer;
the first voltage selection unit connects the lower electrode plate of each auxiliary correction capacitor in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array to a first reference voltage or a second reference voltage or a common mode voltage through a plurality of switches;
the main DAC capacitor array comprises a P-end main DAC capacitor array and an N-end main DAC capacitor array;
the P-end main DAC capacitor array and the N-end main DAC capacitor array comprise m main DAC capacitors and a second voltage selection unit; wherein m is a positive integer, and m is not less than n;
the second voltage selection unit controls the lower electrode plate of each main DAC capacitor in the P-end main DAC capacitor array to be connected to the first reference voltage or the first input voltage or the common mode voltage through a plurality of switches, and/or controls the lower electrode plate of each main DAC capacitor in the N-end main DAC capacitor array to be connected to the second reference voltage or the second input voltage or the common mode voltage;
the upper electrode plates of all auxiliary correction capacitors of the P auxiliary correction capacitor array and the upper electrode plates of all main DAC capacitors of the P-end main DAC capacitor array are connected to the first input end of the comparator; upper electrode plates of all auxiliary correction capacitors of the N auxiliary correction capacitor arrays and upper electrode plates of all main DAC capacitors of the N-end main DAC capacitor arrays are connected to the second input end of the comparator;
a third voltage selection unit, configured to connect all auxiliary correction capacitors in the P-side auxiliary correction capacitor array and upper plates of all main DAC capacitors in the P-side main DAC capacitor array to the common mode voltage through a switch;
a fourth voltage selection unit for connecting upper plates of all auxiliary correction capacitors in the N-terminal main DAC capacitor array and all main DAC capacitors in the N-terminal main DAC capacitor array to the common mode voltage through a switch;
the input end of the correction logic module is connected with the output end of the comparator; the output end of the correction logic module is connected with the first voltage selection unit of the P auxiliary correction capacitor array and the N auxiliary correction capacitor array;
the input end of the SAR logic module is connected with the output end of the comparator; and the output end of the SAR logic module is connected with the second voltage selection unit of the P-end main DAC capacitor array and the N-end main DAC capacitor array.
The SAR ADC offset error correction method and circuit based on the differential structure provided by the invention are provided with a differential main capacitor array (a P-end main DAC capacitor array and an N-end main DAC capacitor array) and an N-bit differential auxiliary correction capacitor array (a P auxiliary correction capacitor array and an N auxiliary correction capacitor array), and in the correction stage, under the drive of a correction logic module, the auxiliary correction capacitors in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array are subjected to N times of logic switching and judgment to obtain correction result information; the correction logic module encodes the correction result information to obtain compensation direction information and a correction compensation value, and stores the compensation direction information and the correction compensation value in a register; during normal operation, the corrected compensation value is compensated into the ADC, thereby counteracting the ADC offset error. The auxiliary correction capacitor array with n bits is adopted to completely eliminate ADC offset errors in a certain range, and the differential circuit structure can well inhibit common mode interference and noise in a circuit and an environment.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a flow chart of a method for SAR ADC misalignment error correction based on differential structure, in accordance with an exemplary embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a differential structure-based SAR ADC misalignment error correction circuit in accordance with an exemplary embodiment of the present invention;
FIG. 3 is a flow chart of logic switching and arbitration provided in an exemplary embodiment of the present invention;
fig. 4 is a flow chart of obtaining compensation direction information and correcting compensation values using a correction logic module according to an exemplary embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical scheme of the invention is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
Referring to fig. 1, the method for correcting offset error of SAR ADC based on differential structure provided by the invention includes:
s1: under the drive of a correction logic module, N times of logic switching and judgment are carried out on auxiliary correction capacitors in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array, so that N-bit correction result information is obtained; the P auxiliary correction capacitor array and the N auxiliary correction capacitor array comprise N auxiliary correction capacitors, and N is a positive integer;
s2: encoding the correction result information by using a correction logic module to obtain compensation direction information and a correction compensation value; the compensation direction information characterizes the type of compensation; the correction compensation value characterizes the magnitude of the compensated voltage value;
s3: and in a normal working stage, correcting the ADC offset error according to the correction compensation value and the correction compensation direction information output by the correction logic module.
The SAR ADC is a successive approximation analog-to-digital converter, and in each conversion process, the input signal is compared with all quantized values one by traversing the quantized values and converting the quantized values into analog values, so as to finally obtain a digital signal to be output. A SAR ADC of the capacitive DAC type generates an analog output voltage according to the principle of charge redistribution, the main DAC of which typically comprises an array of a plurality of capacitors arranged in binary weighting and a "blank LSB" capacitor. In this embodiment, the SAR ADC is a capacitive DAC type SAR ADC, and the main DAC capacitor array includes a P-end main DAC capacitor array and an N-end main DAC capacitor array; the P-end main DAC capacitor array and the N-end main DAC capacitor array comprise m main DAC capacitors, m is a positive integer, and m is larger than or equal to N. The SAR ADC of the differential structure based in this embodiment quantizes a set of differential analog input signals VIP, VIN into an m-bit digital signal output by the host.
Referring to fig. 2, the invention provides a SAR ADC offset error correction circuit based on a differential structure, comprising:
an auxiliary correction capacitance array 10 including a P auxiliary correction capacitance array 11 and an N auxiliary correction capacitance array 12;
the P auxiliary correction capacitor array 11 and the N auxiliary correction capacitor array 12 each include N auxiliary correction capacitors and a first voltage selection unit; wherein n is a positive integer;
the first voltage selection unit connects the lower plate of each auxiliary correction capacitor of the P auxiliary correction capacitor array 11 and the N auxiliary correction capacitor array 12 to the first reference voltage V through a plurality of switches REFP Or a second reference voltage V REFN Or common mode voltage V CM ；
A main DAC capacitor array 20 comprising a P-side main DAC capacitor array 21 and an N-side main DAC capacitor array 22;
the P-terminal main DAC capacitor array 21 and the N-terminal main DAC capacitor array 22 each include m main DAC capacitors and a second voltage selection unit; wherein m is a positive integer, and m is not less than n;
the second voltage selection unit controls the lower plate of each main DAC capacitor in the P-end main DAC capacitor array 21 to be connected to the first reference voltage V through a plurality of switches REFP Or a first input voltage V IP Or the common mode voltage V CM And/or controlling the lower plate of each main DAC capacitor in the N-terminal main DAC capacitor array to be connected to the second referenceTest voltage V REFN Or a second input voltage V IN Or the common mode voltage V CM ；
A comparator 30, the upper plates of all auxiliary correction capacitors of the P-side auxiliary correction capacitor array 11 and the upper plates of all main DAC capacitors of the P-side main DAC capacitor array 21 are connected to a first input terminal of the comparator 30; the upper plates of all auxiliary correction capacitors of the N auxiliary correction capacitor array 12 and the upper plates of all main DAC capacitors of the N-terminal main DAC capacitor array 22 are connected to the second input terminal of the comparator 30;
a third voltage selecting unit for connecting the upper plates of all auxiliary correction capacitors in the P-side auxiliary correction capacitor array 11 and all main DAC capacitors in the P-side main DAC capacitor array 21 to the common mode voltage V through a switch CM ；
A fourth voltage selecting unit for connecting the upper plates of all auxiliary correction capacitors in the N-side auxiliary correction capacitor array 12 and all main DAC capacitors in the N-side main DAC capacitor array 22 to the common mode voltage V through a switch CM ；
The input end of the correction logic module 40 is connected with the output end of the comparator 30; the output end of the correction logic module 40 is connected with the first voltage selection unit of the P auxiliary correction capacitor array 11 and the N auxiliary correction capacitor array 21;
the input end of the SAR logic module 50 is connected with the output end of the comparator 30; the output end of the SAR logic module 50 is connected to the second voltage selection unit of the P-terminal main DAC capacitor array 21 and the N-terminal main DAC capacitor array 22.
Because of the processing deviation of the devices in the chip production and manufacturing process and the introduction of interference on the circuit board in the application scene, the ADC can generate offset errors. The present embodiment provides a method and a circuit for correcting offset errors of a SAR ADC based on a differential structure, where the correction circuit includes a set of differential auxiliary correction capacitor arrays, i.e., a P auxiliary correction capacitor array 11 and an N auxiliary correction capacitor array 12. The calibration is typically triggered each time the power is turned on, or when a large change in the operating environment of the chip occurs (e.g., a large change in operating voltage or operating temperature). In the correction stage, the correction logic module 40 drives the auxiliary correction capacitors in the P auxiliary correction capacitor array 11 and the N auxiliary correction capacitor array 12 to perform logic switching and judgment for N times, encodes the correction result information to obtain a correction compensation value and stores the correction compensation value in a register; in the normal working stage, the correction compensation value is read out from the register and is compensated into the ADC through the correction logic circuit, so that the offset error of the internal circuit of the ADC in a certain range is eliminated, and the differential circuit structure can well inhibit common-mode interference and noise in the circuit and the environment.
In one embodiment, the capacitance values of the N auxiliary correction capacitances in the P auxiliary correction capacitance array 11 and the N auxiliary correction capacitance array 12 each satisfy: sequentially increasing from low level to high level by the power of 2; capacitance value Ca [ i ] of ith capacitor in array]The values of (2) are as follows: ca [ i ]]＝2 i-1 Cu, wherein Cu represents a unit capacitance, i is a positive integer, and i is more than or equal to 1 and less than or equal to n.
In one embodiment, in order to ensure linearity of the capacitor array, the P auxiliary correction capacitor array 11 and the N auxiliary correction capacitor array 12 each further have a lowest-order capacitor, and the capacitance Ca [0] of the low-order auxiliary capacitor has the following value: ca [0] =cu, where Cu represents a unit capacitance.
If the unit capacitance selected by the ADC is Cu, the capacitance value of the n-bit auxiliary correction capacitance array is set to be Ca [ n ] = 2n-1Cu, ca [ n-1] = 2n-2Cu, & gt Ca [3] = 22Cu, ca [2] = 2Cu, ca [1] = Cu, ca [0] = Cu; the number of n bits is selected by the trade-off of correction accuracy and cost, the larger the number of correction bits n is, the higher the correction accuracy is, but the more capacitance branches are needed, the larger the circuit area is. The correction bit number n is generally set smaller than the number of bits of the ADC.
In step S1, please refer to fig. 3, the n times of logic switching and determination are performed from the highest auxiliary capacitor to the lowest auxiliary capacitor in sequence, and the value of the corresponding bit in the correction result information is updated after each logic switching and determination. Each logic switching and judging specifically comprises the following steps:
s11: under the driving of the correction logic module 40, upper electrode plates of all auxiliary capacitors in the P auxiliary correction capacitor array 11 are connected to a first end of a comparator as a first input signal of the comparator 30; connecting the upper plates of all auxiliary capacitors in the N auxiliary correction capacitor array 12 to the second end of the comparator as a second input signal to the comparator 30;
in one embodiment, the upper plates of all auxiliary correction capacitors in the P auxiliary correction capacitor array 11 are directly connected; the upper plates of all auxiliary correction capacitors in the N auxiliary correction capacitor array 12 are directly connected. And the upper plates of all auxiliary correction capacitors of the P-side auxiliary correction capacitor array 11 and the upper plates of all main DAC capacitors of the P-side main DAC capacitor array 21 are connected to the first input terminal of the comparator 30; the upper plates of all auxiliary correction capacitors of the N auxiliary correction capacitor array 12 and the upper plates of all main DAC capacitors of the N-terminal main DAC capacitor array 22 are connected to the second input terminal of the comparator 30. Namely the output voltage V of the upper plates of all the capacitors in the P-terminal main DAC capacitor array 21 and the P-side auxiliary correction capacitor array 11 P A voltage at a first input of comparator 30; the upper plate output voltages V of all the capacitors in the N-terminal main DAC capacitor array 22 and the N auxiliary correction capacitor array 12 N Is the voltage at the second input of comparator 30.
S12: the lower electrode plates of the auxiliary capacitors of the corresponding bits in the P auxiliary correction capacitor array 11 and the N auxiliary correction capacitor array 12 are controlled to be connected to a specified voltage signal;
the specified voltage signal is: first reference voltage V REFP Or a second reference voltage V REFN Or common mode level V CM 。
S13: the value of the corresponding bit of the correction result information is obtained from the output result of the comparator 30.
In the logic judgment stage, the upper capacitance plates of the P-end main DAC capacitance array 21 and the N-end main DAC capacitance array 22 are disconnected, and the P-auxiliary correction capacitance array 11 and the N-end main DAC capacitance array 22 are connectedThe lowest capacitance Ca [0] in the N auxiliary calibration capacitor array 12]The lower polar plates of (a) are connected with the common mode level V CM The correction logic circuit controls the capacitor Ca [ n:1] in the P-auxiliary correction capacitor array 11]The lower polar plate of (C) is connected with V in turn REFP Capacitance Ca [ n:1] in N auxiliary correction capacitance array 12]The lower polar plate of (C) is connected with V in turn REFN Successive approximation logic switching and judgment are performed under the control of the correction logic circuit. The specific process is as follows:
first, assume that auxiliary correction capacitor array high-order capacitance control signal S [ n ]]=1, other capacitance control bits S [ n-1:1]Set to 0, i.e., the highest capacitance Ca [ n ] in the P auxiliary correction capacitance array 11]Lower polar plate is connected with V REFP The highest capacitance Ca [ N ] in the N auxiliary correction capacitance array 12]Lower polar plate is connected with V REFN Low-order capacitance Ca [ N-1:1 ] in P-side auxiliary correction capacitance array and N-side auxiliary correction capacitance array]The lower polar plate of (C) is connected with V CM If the result is outputted by the comparator 30 at this time, the P-terminal output voltage V is obtained P Is greater than the output voltage V of the N end N Then the current control bit S [ n ]]Kept at 1 if the voltage V is output at the P terminal P Less than the output voltage V of the N end N Then the current control bit S [ n ]]＝0。
In the most significant position S [ n ]]After the judgment and the value selection are completed, the high order S [ n-1]]Setting 1, namely P-end auxiliary correction capacitor array is used for secondary high-order capacitor Ca n-1]Lower polar plate is connected with V REFP The next higher capacitor Ca N-1 in the N-terminal auxiliary correction capacitor array]Lower polar plate is connected with V REFN . The highest capacitance lower polar plate is judged according to the last judgment result S [ n ]]Voltage switching is performed if S [ n ]]=1, p-terminal highest capacitance connected to V REFP The highest bit capacitor at the N end is connected with V REFN If S [ n ]]=0, switch to common mode level V CM The rest lower polar plates of other capacitors are all connected with V CM 。
The other bit switching and judging process is the same as the highest bit and the next highest bit judging method until the switching and judging of the polar plate under the Ca 1 capacitor are completed, the value of each bit of Sn1 is determined, at this time, a correction judging period is completed, and after the correction judging is completed, the value of the correction result Sn1 is stored in a correction result register cal n-1:0 of n bits.
In order to ensure that the offset voltage is quantized through logic switching during logic judgment in step S1, reset and sampling are required before logic judgment to obtain a constant charge of the upper polar plate. All upper and lower electrode plates of the capacitor are connected with a common mode level V during reset CM The charge in the capacitor is reset to 0. At this time, the charges of the upper electrode plates of the capacitors in the P-end capacitor array and the N-end capacitor array are respectively:
Q P ＝0
Q N ＝0
all the upper capacitance plates float during sampling, and the lower capacitance plates of the P-end main DAC capacitance array 21 and the N-end main DAC capacitance array 22 are connected with a common mode level V CM All the upper capacitance plates of the P-end capacitance array and the N-end capacitance array are short-circuited, and the P-end auxiliary correction of the highest capacitance Ca [ N ] in the capacitance array]And the lowest capacitance Ca 0]Connected with ADC positive reference source V REFP Other bit capacitors are connected with a common mode level V CM The highest capacitance Ca [ N ] in the N-terminal auxiliary correction capacitor array]And the lowest capacitance Ca 0]Connected with the ADC negative reference source V REFN Other bit capacitors are connected with a common mode level V CM . At this time, the charges of the upper electrode plates of the capacitors in the P-end capacitor array and the N-end capacitor array are respectively:
Q P ＝-V CM *C TOT -(V REFP -V CM )*(C a[n[ +C a[0] )
Q N ＝-V CM *C TOT -(V REFN -V CM )*(C a[n] +C a[0] )
wherein C is TOT The sum of the equivalent capacitances of the P end and the N end is equal to the sum of the equivalent capacitances on the output nodes of the capacitor array, and is C TOT 。
The upper plate of the capacitor is kept in charge, i.e. the upper plate charge remains unchanged regardless of the level to which the lower plate of the capacitor is switched throughout. In order to ensure that the charge of the upper electrode plate is unchanged, the voltage of the upper electrode plate is changed, so that in the logic judgment stage, the level of the lower electrode plate of the capacitor in each array is switched and the charge Q can be used P And Q N Calculating the voltage value V of the upper polar plate corresponding to the current time P And V N 。
When the auxiliary correction capacitor array high-order capacitor carries out logic judgment, the voltage V of the output nodes of the P-end capacitor array and the N-end capacitor array P And V N The method comprises the following steps of:
the voltage difference between the output nodes of the P-end capacitor array and the N-end array is as follows:
wherein V is OS For the offset voltage value, 1LSB is the minimum voltage precision of the ADC which can be identified and is equal to the voltage weight value obtained when one unit capacitor is connected with a reference source.
If the offset voltage value V OS Less than or equal to 1LSB and less than-1 LSB, and the comparator 30 correspondingly outputs a result V P <V N The method comprises the steps of carrying out a first treatment on the surface of the Current control bit S [ n ]]Kept at 1; if the offset voltage value V OS Output result V corresponding to comparator 30 > 1LSB P >V N Current control bit S [ n ]]Clear 0.
In one embodiment, referring to fig. 4, step S2 is to encode the correction result information by using the correction logic module 40 to obtain the compensation direction information and the correction compensation value; the method specifically comprises the following steps:
s21: determining the compensation direction information according to the highest bit of the n-bit correction result information;
the highest bit cal [ n-1] of the obtained correction result information]Is a sign bit for indicating the direction of voltage compensation, cal [ n-1]]=1, indicating that forward compensation is required, cal [ n-1]=0, indicating that reverse compensation is required. cal [ n-2:0]For indicating V OS The specific size of the deviation, n correction bits, the range that can be corrected is covered by- (2) n-1 -1)LSB～2 n-1 Within LSBIs a deviation of (2).
In order to improve the correction accuracy, the process of calculating the correction result information in step S1 in this embodiment may be repeated a plurality of times, for example, t times, and the t sets of correction result information may be averaged as final correction result information cal [ n-1:0].
S22, determining the correction compensation value cal_com [ n-1:0] according to the n-bit correction result information and the compensation direction information, wherein the specific coding modes from cal [ n-1:0] to cal_com [ n-1:0] are as follows:
when the compensation direction information is the first compensation direction, i.e. cal [ n-1]]=1, the correction compensation value cal_com [ n-1:0]＝cal[n-1:0]-2 n-1 ；
When the compensation direction information is the second compensation direction, i.e. cal [ n-1]]=0, the correction compensation value cal_com [ n-1:0]＝2 n-1 -cal[n-1:0]。
Taking n=6 as an example, the correction result cal [ n-1:0]Compensation direction flag bit cal_dir, correction compensation value cal_com [ n-1:0]]And V OS The value correspondence of (2) is shown in table 1.
Table 1: correction result cal [ n-1:0]Compensation direction flag bit cal_dir, correction compensation value cal_com [ n-1:0]]And V OS Value correspondence of (2)
Step S2, the n-bit correction result information cal [ n-1:0] obtained in step S1 is encoded in a correction logic circuit to become a correction compensation direction flag signal cal_dir and a correction compensation value cal_com [ n-1:0], and the correction compensation value cal_dir and the correction compensation value cal_com [ n-1:0] are stored in a register, and the compensation value is loaded into the ADC in the normal operation of the ADC in step S3, and the electrode plate level under the auxiliary correction array capacitor is controlled to compensate the offset error. The method specifically comprises the following steps: and determining a voltage signal accessed by a lower polar plate of each auxiliary correction capacitor in the P auxiliary correction array and the N auxiliary correction array according to the value of the corresponding bit in the correction compensation value.
In one embodiment, when the correction compensation value cal_com [ n-1:0]Is 0, and represents the auxiliary correction capacitor array 11 and auxiliary correction capacitor array NThe lower electrode plate of the corresponding auxiliary correction capacitor in the auxiliary correction capacitor array 12 is connected with the common mode level V CM ；
When a bit of the correction compensation value cal_com [ n-1:0] is 1, then:
when the compensation direction information is the first compensation direction, the positive compensation is required, and the lower plate of the auxiliary correction capacitor of the P auxiliary correction capacitor array 11 is connected to the first reference voltage V REFP The lower electrode of the auxiliary correction capacitor of the N auxiliary correction capacitor array 12 is connected with the second reference voltage V REFN ；
When the compensation direction information is the second compensation direction, the need of the reverse compensation is described, and the lower plate of the auxiliary correction capacitor of the P auxiliary correction capacitor array 11 is connected to the second reference voltage V REFN The lower electrode of the auxiliary correction capacitor of the N auxiliary correction capacitor array 12 is connected with the first reference voltage V REFP 。
The correction is generally triggered every time the power is turned on or the working environment of the chip is changed greatly (such as the working voltage or the working temperature is changed greatly), and the compensation direction information and the correction compensation value are stored. In the normal operation phase, the least significant capacitance Ca [0] in the P auxiliary calibration capacitor array 11 and the N auxiliary calibration capacitor array 1212]Always connect V CM Other capacitances Ca [ n ]]～Ca[1]The lower plate voltages of (2) are respectively corrected by the correction logic module 40 according to the correction compensation values cal_com [ n-1:0] of n bits]And controlling the voltage to be connected to the corresponding voltage from large to small in sequence, so as to compensate the correction compensation value into the ADC and counteract the offset error.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (10)
1. The SAR ADC offset error correction method based on the differential structure is characterized by comprising the following steps of:
under the drive of a correction logic module, N times of logic switching and judgment are carried out on auxiliary correction capacitors in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array, so that N-bit correction result information is obtained; the P auxiliary correction capacitor array and the N auxiliary correction capacitor array comprise N auxiliary correction capacitors, and N is a positive integer;
the n times of logic switching and judgment are performed from the highest auxiliary capacitor to the lowest auxiliary capacitor in sequence, and the numerical value of the corresponding bit in the correction result information is updated after each time of logic switching and judgment, and each time of logic switching and judgment specifically comprises:
under the drive of a correction logic module, upper polar plates of all auxiliary capacitors in the P auxiliary correction capacitor array are connected to a first end of a comparator to be used as a first input signal of the comparator; connecting upper plates of all auxiliary capacitors in the N auxiliary correction capacitor array to a second end of the comparator as a second input signal of the comparator;
controlling the lower electrode plate of the auxiliary capacitor of the corresponding bit in the P auxiliary correction capacitor array to be switched between a first reference voltage and a common mode level, and controlling the lower electrode plate of the auxiliary capacitor of the corresponding bit in the N auxiliary correction capacitor array to be switched between a second reference voltage and the common mode level;
obtaining the value of the corresponding bit of the correction result information according to the output result of the comparator;
encoding the correction result information by using a correction logic module to obtain compensation direction information and a correction compensation value; the compensation direction information characterizes the type of compensation; the correction compensation value characterizes the magnitude of the compensated voltage value;
and in a normal working stage, correcting the ADC offset error according to the correction compensation value and the compensation direction information output by the correction logic module.
2. The method for SAR ADC misalignment error correction based on differential structure as claimed in claim 1, wherein,
the upper polar plates of all auxiliary correction capacitors in the P auxiliary correction capacitor array are directly connected; the upper polar plates of all auxiliary correction capacitors in the N auxiliary correction capacitor arrays are directly connected.
3. The SAR ADC offset error correction method based on a differential structure according to claim 2, wherein the capacitance values of N auxiliary correction capacitors in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array each satisfy: sequentially increasing from low level to high level by the power of 2; capacitance value Ca [ i ] of ith capacitor in array]The values of (2) are as follows: ca [ i ]]＝2 i -1 Cu, wherein Cu represents a unit capacitance, i is a positive integer, and i is more than or equal to 1 and less than or equal to n.
4. The method for correcting offset error of SAR ADC based on differential structure according to claim 3, wherein said P auxiliary correction capacitor array and said N auxiliary correction capacitor array each comprise a low auxiliary capacitor, and the capacitance Ca [0] of said low auxiliary capacitor has the following value: ca [0] =cu, where Cu represents a unit capacitance.
5. The method for correcting offset error of SAR ADC based on differential structure according to claim 1, wherein said correction result information is encoded by a correction logic module to obtain compensation direction information and a correction compensation value; the method specifically comprises the following steps:
determining the compensation direction information according to the highest bit of the n-bit correction result information;
and determining the correction compensation value according to the n-bit correction result information and the compensation direction information.
6. The method for correcting offset error of SAR ADC based on differential structure according to claim 5, wherein said compensating direction information is determined according to the most significant bit of said n-bit correction result information, comprising:
when the highest bit cal [ n-1] of the correction result information is 1, the compensation direction information is a first compensation direction; the first compensation direction represents a positive compensation direction;
when the highest bit cal [ n-1] of the correction result information is 0, the compensation direction information is a second compensation direction; the second compensation direction represents a negative compensation direction;
wherein the binary value of n bits cal [ n-1:0] represents the correction result information, and cal [ n-1] represents the most significant bit of the correction result information.
7. The method for correcting offset error of SAR ADC based on differential structure according to claim 6, wherein determining the correction compensation value according to the n-bit correction result information and the compensation direction information, specifically comprises:
when the compensation direction information is the first compensation direction, the correction compensation value cal_com [ n-1:0] is obtained according to the following formula:
cal_com[n-1:0]＝cal[n-1:0]-2 n-1 ；
when the compensation direction information is the second compensation direction, the correction compensation value cal_com [ n-1:0] is obtained according to the following formula:
cal_com[n-1:0]＝2 n-1 -cal[n-1:0]；
wherein the binary value of n bits cal_com [ n-1:0] represents the correction compensation value.
8. The method for correcting an offset error of a SAR ADC based on a differential structure according to claim 7, wherein correcting an offset error of the ADC according to the correction compensation value and the compensation direction information output by the correction logic module, specifically comprises: and determining a voltage signal connected to the lower pole plate of each auxiliary correction capacitor in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array according to the value of the corresponding bit in the correction compensation value.
9. The method for correcting the offset error of the SAR ADC based on the differential structure according to claim 8, wherein determining the voltage signal of the lower plate access of each auxiliary correction capacitor of the P auxiliary correction capacitor array and the N auxiliary correction capacitor array, specifically comprises:
a certain position of the correction compensation value is 0, and the lower polar plate of the corresponding auxiliary correction capacitor in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array is connected with a common mode level;
if a certain bit of the correction compensation value is 1, then:
when the compensation direction information is the first compensation direction, the lower electrode plate of the auxiliary correction capacitor array representing P is connected with a first reference voltage, and the lower electrode plate of the auxiliary correction capacitor array representing N is connected with a second reference voltage;
and when the compensation direction information is the second compensation direction, the lower electrode plate of the auxiliary correction capacitor of the characterization P auxiliary correction capacitor array is connected with the second reference voltage, and the lower electrode plate of the auxiliary correction capacitor of the N auxiliary correction capacitor array is connected with the first reference voltage.
10. A SAR ADC offset error correction circuit based on a differential structure, applied to the correction method of any one of claims 1-9, comprising:
the auxiliary correction capacitor array comprises a P auxiliary correction capacitor array and an N auxiliary correction capacitor array;
the P auxiliary correction capacitor array and the N auxiliary correction capacitor array comprise N auxiliary correction capacitors and a first voltage selection unit; wherein n is a positive integer;
the first voltage selection unit connects the lower electrode plate of each auxiliary correction capacitor in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array to a first reference voltage or a second reference voltage or a common mode voltage through a plurality of switches;
the main DAC capacitor array comprises a P-end main DAC capacitor array and an N-end main DAC capacitor array;
the P-end main DAC capacitor array and the N-end main DAC capacitor array comprise m main DAC capacitors and a second voltage selection unit; wherein m is a positive integer, and m is not less than n;
the second voltage selection unit controls the lower electrode plate of each main DAC capacitor in the P-end main DAC capacitor array to be connected to the first reference voltage or the first input voltage or the common mode voltage through a plurality of switches, and/or controls the lower electrode plate of each main DAC capacitor in the N-end main DAC capacitor array to be connected to the second reference voltage or the second input voltage or the common mode voltage;
the upper electrode plates of all auxiliary correction capacitors of the P auxiliary correction capacitor array and the upper electrode plates of all main DAC capacitors of the P-end main DAC capacitor array are connected to the first input end of the comparator; upper electrode plates of all auxiliary correction capacitors of the N auxiliary correction capacitor arrays and upper electrode plates of all main DAC capacitors of the N-end main DAC capacitor arrays are connected to the second input end of the comparator;
a third voltage selection unit, configured to connect all auxiliary correction capacitors in the P-side auxiliary correction capacitor array and upper plates of all main DAC capacitors in the P-side main DAC capacitor array to the common mode voltage through a switch;
a fourth voltage selection unit for connecting upper plates of all auxiliary correction capacitors in the N-terminal main DAC capacitor array and all main DAC capacitors in the N-terminal main DAC capacitor array to the common mode voltage through a switch;
the input end of the correction logic module is connected with the output end of the comparator; the output end of the correction logic module is connected with the first voltage selection unit of the P auxiliary correction capacitor array and the N auxiliary correction capacitor array;
the input end of the SAR logic module is connected with the output end of the comparator; and the output end of the SAR logic module is connected with the second voltage selection unit of the P-end main DAC capacitor array and the N-end main DAC capacitor array.
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