CN114614821A - SAR ADC offset error correction method and circuit based on differential structure - Google Patents
SAR ADC offset error correction method and circuit based on differential structure Download PDFInfo
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Abstract
The invention provides a SAR ADC offset error correction method and circuit based on a differential structure, wherein the correction method comprises the following steps: under the drive of the correction logic module, N-bit correction result information is obtained by performing N-time logic switching and judgment on auxiliary correction capacitors in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array; coding the correction result information by using a correction logic module to obtain compensation direction information and a correction compensation value; the compensation direction information represents the type of compensation; the correction compensation value represents the magnitude of the compensated voltage value; and in a normal working stage, correcting the offset error of the ADC according to the correction compensation value and the correction compensation direction information output by the correction logic module.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a SAR ADC offset error correction method and circuit based on a differential structure.
Background
Because the layout of the chip is difficult to realize that the layout and the wiring of the circuit are completely symmetrical, the circuits such as a comparator and the like have process mismatch, devices have processing deviation in the chip production and manufacturing process, and interference introduction on a circuit board in an application scene can cause the ADC to generate offset errors. With the requirement on the precision of the ADC higher and higher, the influence of deviations such as circuit offset on the performance of the ADC is more and more obvious, and the offset of the ADC must be corrected and compensated under the high-precision application scene. Currently, commonly used SAR ADC imbalance correction methods mainly include: the common mode level of the comparator is adjusted through an adjustable resistor array, the offset voltage is compensated and eliminated by adopting a digital correction method and an additional auxiliary correction capacitor DAC array.
The scheme of adjusting the offset voltage of the ADC through the adjustable resistor array is simple in logic, but extra static power consumption can be introduced into the resistor array; the method adopting digital correction does not need additional auxiliary correction resistor and capacitor, can reduce the circuit area, but needs complex digital logic design and has the problem of convergence; the correction method adopting the auxiliary electric correction capacitor array has no static power consumption and no convergence problem. The existing correction circuit adopting the auxiliary correction capacitor array is of a single-ended structure and is easily influenced by common-mode interference and noise which change along with the application environment.
Disclosure of Invention
The invention provides a method and a circuit for correcting offset errors of an SAR ADC (synthetic aperture radar) based on a differential structure, which aim to solve the problem of offset errors of the ADC caused by dynamic common mode interference and noise in chip manufacturing process deviation and application environment change.
According to a first aspect of the present invention, there is provided a method for correcting an offset error of a SAR ADC based on a differential structure, comprising:
under the drive of the correction logic module, N-bit correction result information is obtained by performing N-time logic switching and judgment on auxiliary correction capacitors in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array; wherein the P auxiliary correction capacitor array and the N auxiliary correction capacitor array each comprise N auxiliary correction capacitors, and N is a positive integer;
coding the correction result information by using a correction logic module to obtain compensation direction information and a correction compensation value; the compensation direction information represents the type of compensation; the correction compensation value represents the magnitude of the compensated voltage value;
and in a normal working stage, correcting the offset error of the ADC according to the correction compensation value and the correction compensation direction information output by the correction logic module.
Optionally, the upper plates of all the auxiliary correction capacitors in the P auxiliary correction capacitor array are directly connected; and the upper plates of all the auxiliary correction capacitors in the N auxiliary correction capacitor arrays are directly connected.
Optionally, the capacitance values of N auxiliary correction capacitors in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array both satisfy: sequentially increasing by the power of 2 from the low position to the high position; capacitance value Ca [ i ] of ith capacitor in array]The values of (A) are as follows: ca [ i ]]＝2i-1Cu, wherein Cu represents unit capacitance, i is a positive integer, and i is more than or equal to 1 and less than or equal to n.
Optionally, the P auxiliary correction capacitor array and the N auxiliary correction capacitor array both include a lower auxiliary capacitor, and a value of a capacitance Ca [0] of the lower auxiliary capacitor is: ca [0] ═ Cu, where Cu represents a unit capacitance.
Optionally, the n times of logic switching and determination are performed from the highest order auxiliary capacitor to the lowest order auxiliary capacitor, and the value of the corresponding bit in the correction result information is updated after each time of logic switching and determination.
Optionally, each logic switching and determining specifically includes:
under the drive of a correction logic module, connecting the upper plates of all auxiliary capacitors in the P auxiliary correction capacitor array to a first end of a comparator to serve as a first input signal of the comparator; connecting the upper plates of all the auxiliary capacitors in the N auxiliary correction capacitor array to the second end of the comparator to serve as a second input signal of the comparator;
controlling the lower plates of the auxiliary capacitors of the corresponding bits in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array to be connected to a specified voltage signal;
and obtaining the value of the corresponding bit of the correction result information according to the output result of the comparator.
Optionally, the specified voltage signal is: a first reference voltage or a second reference voltage or a common mode level.
Optionally, the correction logic module is used for encoding the correction result information to obtain compensation direction information and a correction compensation value; the method specifically comprises the following steps:
determining the compensation direction information according to the highest bit of the n-bit correction result information;
and determining the correction compensation value according to the n-bit correction result information and the compensation direction information. Optionally, determining the compensation direction information according to the highest bit of the n-bit correction result information specifically includes:
when the most significant bit cal [ n-1] of the correction result information is 1, the compensation direction information is a first compensation direction; the first compensation direction represents a positive compensation direction;
when the most significant bit cal [ n-1] of the correction result information is 0, the compensation direction information is a second compensation direction; the second compensation direction represents a negative compensation direction;
wherein a binary value cal [ n-1:0] of n bits represents the correction result information, and cal [ n-1] represents the most significant bit of the correction result information.
Optionally, determining the correction compensation value according to the n-bit correction result information and the compensation direction information specifically includes:
when the compensation direction information is the first compensation direction, the correction compensation value cal _ com [ n-1:0] is obtained according to the following formula:
cal_com[n-1:0]＝cal[n-1:0]-2n-1；
when the compensation direction information is the second compensation direction, the correction compensation value cal _ com [ n-1:0] is obtained according to the following formula:
cal_com[n-1:0]＝2n-1-cal[n-1:0]；
wherein a binary value cal _ com [ n-1:0] of n bits represents the correction compensation value.
Optionally, the correcting the ADC offset error according to the correction compensation value and the correction compensation direction information output by the correction logic module specifically includes: and determining a voltage signal connected to the lower plate of each auxiliary correction capacitor in the P auxiliary correction array and the N auxiliary correction array according to the value of the corresponding bit in the correction compensation value.
Optionally, the determining a voltage signal connected to a lower plate of each auxiliary correction capacitor in the P auxiliary correction array and the N auxiliary correction array specifically includes:
a certain bit of the correction compensation value is 0, and the lower electrode plates of the auxiliary correction capacitors corresponding to the P auxiliary correction capacitor array and the N auxiliary correction capacitor array are connected with a common mode level;
if a bit of the correction compensation value is 1, then:
when the compensation direction information is the first compensation direction, representing that the lower plate of the auxiliary correction capacitor of the P auxiliary correction capacitor array is connected with a first reference voltage, and the lower plate of the auxiliary correction capacitor of the N auxiliary correction capacitor array is connected with a second reference voltage;
and when the compensation direction information is the second compensation direction, characterizing that the lower plate of the auxiliary correction capacitor of the P auxiliary correction capacitor array is connected with a second reference voltage, and the lower plate of the auxiliary correction capacitor of the N auxiliary correction capacitor array is connected with a first reference voltage.
According to a second aspect of the present invention, there is provided a differential structure-based SAR ADC offset error correction circuit, which is applied to the correction method provided by the first aspect of the present invention, and includes:
the auxiliary correction capacitor array comprises a P auxiliary correction capacitor array and an N auxiliary correction capacitor array;
the P auxiliary correction capacitor array and the N auxiliary correction capacitor array respectively comprise N auxiliary correction capacitors and a first voltage selection unit; wherein n is a positive integer;
the first voltage selection unit connects the lower plate of each auxiliary correction capacitor in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array to a first reference voltage or a second reference voltage or a common mode voltage through a plurality of switches;
the main DAC capacitor array comprises a P-end main DAC capacitor array and an N-end main DAC capacitor array;
the P-end main DAC capacitor array and the N-end main DAC capacitor array respectively comprise m main DAC capacitors and a second voltage selection unit; wherein m is a positive integer, and m is more than or equal to n;
the second voltage selection unit controls the lower plate of each main DAC capacitor in the P-terminal main DAC capacitor array to be connected to the first reference voltage or the first input voltage or the common mode voltage through a plurality of switches, and/or controls the lower plate of each main DAC capacitor in the N-terminal main DAC capacitor array to be connected to the second reference voltage or the second input voltage or the common mode voltage;
the upper plates of all auxiliary correction capacitors of the P-auxiliary correction capacitor array and the upper plates of all main DAC capacitors of the P-end main DAC capacitor array are connected to a first input end of the comparator; the upper plates of all auxiliary correction capacitors of the N-auxiliary correction capacitor array and the upper plates of all main DAC capacitors of the N-terminal main DAC capacitor array are connected to the second input end of the comparator;
a third voltage selection unit, configured to connect upper plates of all auxiliary correction capacitors in the P-auxiliary correction capacitor array and all main DAC capacitors in the P-side main DAC capacitor array to the common mode voltage through a switch;
a fourth voltage selection unit, configured to connect upper plates of all the auxiliary correction capacitors in the N-auxiliary correction capacitor array and all the main DAC capacitors in the N-terminal main DAC capacitor array to the common mode voltage through a switch;
the input end of the correction logic module is connected with the output end of the comparator; the output end of the correction logic module is connected with the first voltage selection unit of the P auxiliary correction capacitor array and the first voltage selection unit of the N auxiliary correction capacitor array;
the input end of the SAR logic module is connected with the output end of the comparator; and the output end of the SAR logic module is connected with the second voltage selection unit of the P-end main DAC capacitor array and the N-end main DAC capacitor array.
The SAR ADC offset error correction method and circuit based on the differential structure, provided by the invention, have a differential main capacitor array (a P-end main DAC capacitor array and an N-end main DAC capacitor array) and an N-bit differential auxiliary correction capacitor array (a P-auxiliary correction capacitor array and an N-auxiliary correction capacitor array), and in a correction stage, under the drive of a correction logic module, N times of logic switching and judgment are carried out on auxiliary correction capacitors in the P-auxiliary correction capacitor array and the N-auxiliary correction capacitor array to obtain correction result information; the correction logic module encodes the correction result information to obtain compensation direction information and a correction compensation value, and stores the compensation direction information and the correction compensation value in a register; and compensating the correction compensation value into the ADC in a normal working stage so as to offset ADC offset error. The auxiliary correction capacitor array with n-bit assistance can completely eliminate ADC offset errors within a certain range, and the differential circuit structure can well inhibit common-mode interference and noise in circuits and the environment.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic flowchart of a SAR ADC offset error correction method based on a differential structure according to an exemplary embodiment of the present invention;
fig. 2 is a schematic circuit diagram of a differential-structure-based SAR ADC offset error correction circuit provided in an exemplary embodiment of the present invention;
FIG. 3 is a flow chart illustrating logical switching and arbitration provided in an exemplary embodiment of the present invention;
fig. 4 is a schematic flow chart illustrating obtaining compensation direction information and a correction compensation value by using a correction logic module according to an exemplary embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Referring to fig. 1, a method for correcting an offset error of an SAR ADC based on a differential structure provided by the present invention includes:
s1: under the drive of the correction logic module, N-bit correction result information is obtained by performing N-time logic switching and judgment on auxiliary correction capacitors in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array; wherein the P auxiliary correction capacitor array and the N auxiliary correction capacitor array each comprise N auxiliary correction capacitors, and N is a positive integer;
s2: coding the correction result information by using a correction logic module to obtain compensation direction information and a correction compensation value; the compensation direction information represents the type of compensation; the correction compensation value represents the magnitude of the compensated voltage value;
s3: and in a normal working stage, correcting the offset error of the ADC according to the correction compensation value and the correction compensation direction information output by the correction logic module.
In each conversion process, all quantized values are traversed and converted into analog values, and input signals are compared with the analog values one by one to finally obtain digital signals to be output. A SAR ADC of the capacitive DAC type generates an analog output voltage according to the principle of charge redistribution, the main DAC of which usually comprises an array of a plurality of capacitors arranged in binary weights and a "null LSB" capacitor. In the embodiment, the SAR ADC is a capacitance DAC type SAR ADC, and the main DAC capacitor array comprises a P-end main DAC capacitor array and an N-end main DAC capacitor array; the P-end main DAC capacitor array and the N-end main DAC capacitor array respectively comprise m main DAC capacitors, m is a positive integer and is larger than or equal to N. The differential structure based SAR ADC in this embodiment quantizes a set of differential analog input signals VIP and VIN into a digital signal output with m bits.
Referring to fig. 2, the present invention provides a differential structure based SAR ADC offset error correction circuit, including:
an auxiliary correction capacitor array 10 including a P auxiliary correction capacitor array 11 and an N auxiliary correction capacitor array 12;
the P auxiliary correction capacitor array 11 and the N auxiliary correction capacitor array 12 each include N auxiliary correction capacitors and a first voltage selection unit; wherein n is a positive integer;
the first voltage selection unit connects the lower plate of each of the P auxiliary correction capacitors 11 and the N auxiliary correction capacitors 12 to the first reference voltage V through a plurality of switchesREFPOr a second reference voltage VREFNOr a common mode voltage VCM；
The main DAC capacitor array 20 comprises a P-end main DAC capacitor array 21 and an N-end main DAC capacitor array 22;
the P-end main DAC capacitor array 21 and the N-end main DAC capacitor array 22 respectively comprise m main DAC capacitors and a second voltage selection unit; wherein m is a positive integer, and m is more than or equal to n;
the second voltage selection unit controls the lower plate of each main DAC capacitor in the P-end main DAC capacitor array 21 to be connected to the first reference voltage V through a plurality of switchesREFPOr the first input voltage VIPOr the common mode voltage VCMAnd/or controlling the lower plate of each main DAC capacitor in the N-terminal main DAC capacitor array to be connected to the second reference voltage VREFNOr a second input voltage VINOr the common mode voltage VCM；
A comparator 30, the upper plates of all the auxiliary correction capacitors of the P-auxiliary correction capacitor array 11 and the upper plates of all the main DAC capacitors of the P-side main DAC capacitor array 21 are connected to a first input end of the comparator 30; the upper plates of all the auxiliary correction capacitors of the N-auxiliary correction capacitor array 12 and the upper plates of all the main DAC capacitors of the N-terminal main DAC capacitor array 22 are connected to the second input terminal of the comparator 30;
a third voltage selection unit for connecting the upper plates of all auxiliary correction capacitors in the P-auxiliary correction capacitor array 11 and all main DAC capacitors in the P-terminal main DAC capacitor array 21 to the common mode voltage V through switchesCM；
A fourth voltage selection unit for connecting the upper plates of all the auxiliary correction capacitors in the N-auxiliary correction capacitor array 12 and all the main DAC capacitors in the N-terminal main DAC capacitor array 22 to the common mode voltage V through switchesCM；
A correction logic module 40, wherein an input end of the correction logic module 40 is connected with an output end of the comparator 30; the output end of the correction logic module 40 is connected to the first voltage selection unit of the P auxiliary correction capacitor array 11 and the N auxiliary correction capacitor array 21;
an input end of the SAR logic module 50 is connected with an output end of the comparator 30; the output end of the SAR logic module 50 is connected to the second voltage selection unit of the P-side main DAC capacitor array 21 and the N-side main DAC capacitor array 22.
Due to the processing deviation of devices in the chip production and manufacturing process and the introduction of interference on a circuit board in an application scene, the offset error of the ADC can be caused. The embodiment provides a SAR ADC offset error correction method and a correction circuit based on a differential structure, wherein the correction circuit comprises a group of differential auxiliary correction capacitor arrays, namely a P auxiliary correction capacitor array 11 and an N auxiliary correction capacitor array 12. The calibration is generally triggered to be performed each time the chip is turned on or when the chip operating environment changes greatly (for example, the operating voltage or the operating temperature changes greatly). In the correction stage, the correction logic module 40 drives the auxiliary correction capacitors in the P auxiliary correction capacitor array 11 and the N auxiliary correction capacitor array 12 to perform logic switching and judgment for N times, and encodes the correction result information to obtain a correction compensation value and stores the correction compensation value in a register; in the normal working stage, the correction compensation value is read out from the register and compensated into the ADC through the correction logic circuit, so that the offset error of the ADC internal circuit within a certain range is eliminated, and the differential circuit structure can well inhibit common-mode interference and noise in the circuit and the environment.
In one embodiment, the capacitance values of N auxiliary correction capacitors in the P auxiliary correction capacitor array 11 and the N auxiliary correction capacitor array 12 each satisfy: sequentially increasing by the power of 2 from the low position to the high position; capacitance value Ca [ i ] of ith capacitor in array]The values of (A) are as follows: ca [ i ]]＝2i-1Cu, wherein Cu represents unit capacitance, i is a positive integer, and i is more than or equal to 1 and less than or equal to n.
In one embodiment, in order to ensure the linearity of the capacitor array, there is a lowest-order capacitor in each of the P-auxiliary correction capacitor array 11 and the N-auxiliary correction capacitor array 12, and the capacitance value Ca [0] of the lower-order auxiliary capacitor is: ca [0] ═ Cu, where Cu represents a unit capacitance.
If the unit capacitor selected for the ADC is Cu, the capacitance value of the n-bit auxiliary correction capacitor array is set to Ca [ n ] ═ 2n-1Cu, Ca [ n-1] ═ 2n-2Cu,.. Ca [3] ═ 22Cu, Ca [2] ═ 2Cu, Ca [1] ═ Cu, Ca [0] ═ Cu; the number of the n bits is selected by the compromise of correction precision and cost, the larger the correction number of the n bits is, the higher the correction precision is, but the more the needed capacitor branches are, the larger the circuit area is. The number of correction bits n is generally set to be smaller than the number of bits of the ADC.
In step S1, referring to fig. 3, the n times of logic switching and determination are performed from the highest auxiliary capacitor to the lowest auxiliary capacitor in sequence, and the value of the corresponding bit in the correction result information is updated after each logic switching and determination. Wherein each logic switching and judging specifically comprises:
s11: under the driving of a correction logic module 40, connecting the upper plates of all the auxiliary capacitors in the P auxiliary correction capacitor array 11 to a first end of a comparator as a first input signal of the comparator 30; connecting the upper plates of all the auxiliary capacitors in the N auxiliary correction capacitor array 12 to the second end of the comparator as a second input signal of the comparator 30;
in one embodiment, the upper plates of all the auxiliary correction capacitors in the P auxiliary correction capacitor array 11 are directly connected; the upper plates of all the auxiliary correction capacitors in the N auxiliary correction capacitor arrays 12 are directly connected. And the upper plates of all auxiliary correction capacitors of the P-auxiliary correction capacitor array 11 and the upper plates of all main DAC capacitors of the P-terminal main DAC capacitor array 21 are connected to the first input terminal of the comparator 30; the upper plates of all the auxiliary correction capacitors of the N-auxiliary correction capacitor array 12 and the upper plates of all the main DAC capacitors of the N-terminal main DAC capacitor array 22 are connected to the second input terminal of the comparator 30. Namely, the output voltage V of the upper plates of all capacitors in the P-side main DAC capacitor array 21 and the P-side auxiliary correction capacitor array 11PIs the first input voltage of comparator 30; the upper plate output voltage V of all capacitors in the N-terminal main DAC capacitor array 22 and the N-auxiliary correction capacitor array 12NIs the voltage at the second input of comparator 30.
S12: controlling the lower plates of the auxiliary capacitors of the corresponding bits in the P auxiliary correction capacitor array 11 and the N auxiliary correction capacitor array 12 to be connected to a specified voltage signal;
the specified voltage signals are: a first reference voltage VREFPOr a second reference voltage VREFNOr common mode level VCM。
S13: the value of the corresponding bit of the correction result information is obtained according to the output result of the comparator 30.
In the logic judgment stage, the capacitor upper plates of the P-side main DAC capacitor array 21 and the N-side main DAC capacitor array 22 are disconnected, and the lowest-order capacitor Ca [0] in the P-auxiliary correction capacitor array 11 and the N-auxiliary correction capacitor array 12]All the lower polar plates are connected with a common mode level VCMThe correction logic circuit controls the capacitance Ca [ n:1] in the P-assisted correction capacitor array 11]The lower polar plate is sequentially connected with VREFPN auxiliary correction of the capacitance Ca [ N:1] in the capacitor array 12]The lower polar plate is sequentially connected with VREFNAnd carrying out successive approximation logic switching and judgment under the control of a correction logic circuit. The specific process is as follows:
first, assume the auxiliary correction capacitor array high-order capacitor control signal S [ n ]]1, other capacitance control bits S [ n-1:1]Set to 0, i.e. the highest order capacitor Ca [ n ] in the P-assisted correction capacitor array 11]Lower polar plate connects VREFPN auxiliary correction capacitor array 12 highest order capacitor Ca [ N ]]Lower polar plate connects VREFNLow level capacitor Ca [ N-1: 1] in P-terminal auxiliary correction capacitor array and N-terminal auxiliary correction capacitor array]All the lower polar plates are connected with VCMIf the result is output by the comparator 30 at this time, the output voltage V at the P terminal is obtainedPGreater than the output voltage V of the N terminalNThen the current control bit S [ n ]]Remains at 1 if the P terminal outputs voltage V at the momentPLess than N-terminal output voltage VNThen the current control bit S [ n ]]＝0。
At the highest position S [ n ]]After the judgment and value selection are completed, the high order S [ n-1] is set]Setting 1, i.e. P terminal auxiliary correction capacitor array]Lower polar plate connects VREFPN-terminal auxiliary correction capacitor array]Lower polar plate connects VREFN. The lower plate of the highest capacitor is judged according to the last time]Voltage switching is performed if S [ n ]]1, the highest capacitance of P terminal is connected with VREFPThe highest capacitor at N end is connected to VREFNIf S [ n ]]0, switchingTo a common mode level VCMThe lower electrode plates of the rest capacitors at other positions are all connected with VCM。
The switching and judging process of other bits is the same as the judging method of the most significant bit and the second most significant bit, until the switching and judging of the lower plate of the Ca 1 capacitor is completed, the value of each bit of S [ n:1] is determined, at this moment, a correction judging period is completed, and after the correction judging is completed, the value of the current correction result S [ n:1] is stored in a correction result register cal [ n-1:0] of n bits.
In order to ensure that the offset voltage is quantified by logic switching at the logic judgment of step S1, reset and sampling are required before the logic judgment to obtain a constant charge of the upper plate. All the capacitor upper and lower plates are connected to common mode level V during resetCMThe charge in the capacitor is reset to 0. At this time, the charges of the capacitor upper electrode plates in the P-end capacitor array and the N-end capacitor array are respectively as follows:
QP＝0
QN＝0
during sampling, all capacitor upper plates are floating, and capacitor lower plates of the P-end main DAC capacitor array 21 and the N-end main DAC capacitor array 22 are connected with a common-mode level VCMAll capacitor upper electrode plates of the P-end capacitor array and the N-end capacitor array are in short circuit, and the P-end auxiliary correction capacitor array corrects the highest-order capacitor Ca [ N ]]And the lowest order capacitor Ca [0]]Is connected with an ADC positive reference source VREFPThe other bit capacitors are connected to a common mode level VCMN-terminal auxiliary correction capacitor array with highest capacitance Ca [ N ]]And the lowest order capacitor Ca [0]]Is connected with an ADC negative reference source VREFNThe other bit capacitors are connected to a common mode level VCM. At this time, the charges of the capacitor upper electrode plates in the P-end capacitor array and the N-end capacitor array are respectively as follows:
QP＝-VCM*CTOT-(VREFP-VCM)*(Ca[n[+Ca[0])
QN＝-VCM*CTOT-(VREFN-VCM)*(Ca[n]+Ca[0])
wherein C isTOTThe sum of equivalent capacitances at the output nodes of the capacitor array, the equivalent of the P terminal and the N terminalThe sum of the capacitances is equal to CTOT。
The charge of the upper plate of the capacitor is conserved, namely the charge of the upper plate is kept unchanged no matter which level the lower plate of the capacitor is switched to in the whole process. In order to meet the requirement that the charge of the upper polar plate is unchanged, the voltage of the upper polar plate can be changed along with the charge of the upper polar plate, so that the level of the lower polar plate of the capacitor in the array is switched every time in the logic judgment stage, and the lower polar plate of the capacitor can pass through the charge QPAnd QNCalculating the current corresponding upper plate voltage value VPAnd VN。
When the auxiliary correction capacitor array high-order capacitor carries out logic judgment, the voltage V of the output nodes of the P-end capacitor array and the N-end arrayPAnd VNRespectively as follows:
the voltage difference between the output nodes of the P-end capacitor array and the N-end array is as follows:
wherein VOSThe offset voltage value is 1LSB which is the minimum voltage precision of the ADC which can be identified and is equal to the voltage weight value obtained when a unit capacitor is connected with a reference source.
If the offset voltage value V isOSLess than or equal to 1LSB and less than-1 LSB, and the output result V corresponding to the comparator 30P<VN(ii) a Current control bit S [ n ]]Kept at 1; if the offset voltage value V isOSGreater than 1LSB, and the corresponding output result V of the comparator 30P>VNCurrent control bit S [ n ]]And (5) clearing 0.
In one embodiment, referring to fig. 4, in step S2, the correction result information is encoded by the correction logic module 40 to obtain compensation direction information and a correction compensation value; the method specifically comprises the following steps:
s21: determining the compensation direction information according to the highest bit of the n-bit correction result information;
the highest bit cal n-1 of the obtained correction result information]Is a sign bit, which indicates the direction of voltage compensation, cal [ n-1]]1, indicates that forward compensation is required, cal [ n-1]0 indicates that reverse compensation is required. cal [ n-2:0]For indicating VOSThe specific size of the deviation, n correction bits, the correctable range covers- (2)n-1-1)LSB～2n-1Deviation within LSB.
In order to improve the correction accuracy, the process of calculating the correction result information in step S1 in this embodiment may be repeated a plurality of times, for example, t times, and the t groups of correction result information may be averaged to obtain the final correction result information cal [ n-1:0 ].
S22, determining the correction compensation value cal _ com [ n-1:0] according to the n-bit correction result information and the compensation direction information, wherein the specific coding mode from cal [ n-1:0] to cal _ com [ n-1:0] is as follows:
when the compensation direction information is the first compensation direction, i.e. cal [ n-1]]1, the correction compensation value cal _ com [ n-1:0]＝cal[n-1:0]-2n-1；
When the compensation direction information is the second compensation direction, i.e. cal [ n-1]]0, the correction compensation value cal _ com [ n-1: 0%]＝2n-1-cal[n-1:0]。
Taking n as an example, the correction result cal [ n-1:0 ═ 6]A compensation direction flag bit cal _ dir and a correction compensation value cal _ com [ n-1:0]And VOSThe value correspondence of (a) is shown in table 1.
Table 1: correction result cal [ n-1:0]A compensation direction flag bit cal _ dir and a correction compensation value cal _ com [ n-1:0]And VOSValue correspondence of (a)
Step S2 is to encode the n-bit correction result information cal [ n-1:0] obtained in step S1 in the correction logic circuit into a correction compensation direction flag signal cal _ dir and a correction compensation value cal _ com [ n-1:0] and store them in a register, and step S3 is to load the compensation value into the ADC when the ADC is normally operating, and control the auxiliary correction array capacitor bottom plate level to compensate the offset error. The method specifically comprises the following steps: and determining a voltage signal connected to the lower plate of each auxiliary correction capacitor in the P auxiliary correction array and the N auxiliary correction array according to the value of the corresponding bit in the correction compensation value.
In one embodiment, when the correction compensation value cal _ com [ n-1:0] is used]Is 0, and represents that the lower plate of the corresponding auxiliary correction capacitor in the P auxiliary correction capacitor array 11 and the N auxiliary correction capacitor array 12 is connected to the common mode level VCM；
When a certain bit of the correction compensation value cal _ com [ n-1:0] is 1, then:
when the compensation direction information is the first compensation direction, it indicates that forward compensation is required, and at this time, the lower plate of the auxiliary correction capacitor of the P auxiliary correction capacitor array 11 is connected to the first reference voltage VREFPThe lower plate of the auxiliary correction capacitor of the N auxiliary correction capacitor array 12 is connected with a second reference voltage VREFN；
When the compensation direction information is the second compensation direction, it indicates that reverse compensation is required, and at this time, the lower plate of the auxiliary correction capacitor of the P auxiliary correction capacitor array 11 is connected to the second reference voltage VREFNThe lower plate of the auxiliary correction capacitor of the N auxiliary correction capacitor array 12 is connected with a first reference voltage VREFP。
The calibration is generally triggered to be performed each time the chip is turned on or the chip operating environment is greatly changed (for example, the operating voltage or the operating temperature is greatly changed), and the compensation direction information and the calibration compensation value are stored. In the normal operation stage, the lowest level capacitor Ca [0] in the P auxiliary calibration capacitor array 11 and the N auxiliary calibration capacitor array 1212]Beginning and end VCMOther capacitance Ca [ n ]]～Ca[1]Is respectively corrected by the correction logic module 40 according to the correction compensation value cal _ com [ n-1:0 of n bits]Controlling the voltage to be connected to corresponding voltage in a one-to-one correspondence from large to small in sequence, thereby compensating the correction compensation value into the ADC to counteract offset error。
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and these modifications or substitutions do not depart from the spirit of the corresponding technical solutions of the embodiments of the present invention.
Claims (13)
1. A SAR ADC offset error correction method based on a differential structure is characterized by comprising the following steps:
under the drive of the correction logic module, N-bit correction result information is obtained by performing N-time logic switching and judgment on auxiliary correction capacitors in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array; wherein the P auxiliary correction capacitor array and the N auxiliary correction capacitor array each comprise N auxiliary correction capacitors, and N is a positive integer;
coding the correction result information by using a correction logic module to obtain compensation direction information and a correction compensation value; the compensation direction information represents the type of compensation; the correction compensation value represents the magnitude of the compensated voltage value;
and in a normal working stage, correcting the offset error of the ADC according to the correction compensation value and the correction compensation direction information output by the correction logic module.
2. The SAR ADC offset error correction method based on the differential structure of claim 1,
the upper electrode plates of all auxiliary correction capacitors in the P auxiliary correction capacitor array are directly connected; and the upper plates of all the auxiliary correction capacitors in the N auxiliary correction capacitor arrays are directly connected.
3. The differential architecture based SAR ADC offset error correction of claim 2The method is characterized in that the capacitance values of N auxiliary correction capacitors in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array both satisfy: sequentially increasing by the power of 2 from the low position to the high position; capacitance value Ca [ i ] of ith capacitor in array]The values of (A) are as follows: ca [ i ]]＝2i -1Cu, wherein Cu represents unit capacitance, i is a positive integer, and i is more than or equal to 1 and less than or equal to n.
4. The SAR ADC offset error correction method based on differential structure of claim 3, wherein the P auxiliary correction capacitor array and the N auxiliary correction capacitor array both comprise a lower auxiliary capacitor, and the capacitance Ca [0] of the lower auxiliary capacitor takes on the following value: ca [0] ═ Cu, where Cu represents a unit capacitance.
5. The SAR ADC offset error correction method based on the differential structure as claimed in claim 1, wherein the n times of logic switching and judgment are performed from the highest auxiliary capacitor to the lowest auxiliary capacitor in sequence, and the value of the corresponding bit in the correction result information is updated after each time of logic switching and judgment.
6. The SAR ADC offset error correction method based on the differential structure of claim 5, wherein each logic switching and judging specifically comprises:
under the drive of a correction logic module, connecting the upper plates of all auxiliary capacitors in the P auxiliary correction capacitor array to a first end of a comparator to serve as a first input signal of the comparator; connecting the upper plates of all the auxiliary capacitors in the N auxiliary correction capacitor array to the second end of the comparator to serve as a second input signal of the comparator;
controlling the lower plates of the auxiliary capacitors of the corresponding bits in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array to be connected to a specified voltage signal;
and obtaining the value of the corresponding bit of the correction result information according to the output result of the comparator.
7. The differential structure-based SAR ADC offset error correction method of claim 6, wherein the specified voltage signal is: a first reference voltage or a second reference voltage or a common mode level.
8. The SAR ADC offset error correction method based on the differential structure according to claim 1, wherein the correction result information is encoded by using a correction logic module to obtain compensation direction information and a correction compensation value; the method specifically comprises the following steps:
determining the compensation direction information according to the highest bit of the n-bit correction result information;
and determining the correction compensation value according to the n-bit correction result information and the compensation direction information.
9. The SAR ADC offset error correction method according to claim 8, wherein determining the compensation direction information according to the most significant bit of the n-bit correction result information specifically comprises:
when the most significant bit cal [ n-1] of the correction result information is 1, the compensation direction information is a first compensation direction; the first compensation direction represents a positive compensation direction;
when the most significant bit cal [ n-1] of the correction result information is 0, the compensation direction information is a second compensation direction; the second compensation direction represents a negative compensation direction;
wherein a binary value cal [ n-1:0] of n bits represents the correction result information, and cal [ n-1] represents the most significant bit of the correction result information.
10. The method for SAR ADC offset error correction based on differential architecture of claim 9, wherein determining the correction compensation value according to the n-bit correction result information and the compensation direction information specifically comprises:
when the compensation direction information is the first compensation direction, the correction compensation value cal _ com [ n-1:0] is obtained according to the following formula:
cal_com[n-1:0]＝cal[n-1:0]-2n-1；
when the compensation direction information is the second compensation direction, the correction compensation value cal _ com [ n-1:0] is obtained according to the following formula:
cal_com[n-1:0]＝2n-1-cal[n-1:0]；
wherein a binary value cal _ com [ n-1:0] of n bits represents the correction compensation value.
11. The method for correcting the offset error of the SAR ADC based on the differential structure according to any one of claims 1 to 10, wherein the correcting the offset error of the ADC according to the correction compensation value and the correction compensation direction information output by the correction logic module specifically comprises: and determining a voltage signal connected to the lower plate of each auxiliary correction capacitor in the P auxiliary correction array and the N auxiliary correction array according to the value of the corresponding bit in the correction compensation value.
12. The method according to claim 11, wherein the determining a voltage signal applied to a lower plate of each of the P-auxiliary correction array and the N-auxiliary correction array specifically includes:
a certain bit of the correction compensation value is 0, and the lower electrode plates of the auxiliary correction capacitors corresponding to the P auxiliary correction capacitor array and the N auxiliary correction capacitor array are connected with a common mode level;
if a bit of the correction compensation value is 1, then:
when the compensation direction information is the first compensation direction, representing that the lower plate of the auxiliary correction capacitor of the P auxiliary correction capacitor array is connected with a first reference voltage, and the lower plate of the auxiliary correction capacitor of the N auxiliary correction capacitor array is connected with a second reference voltage;
and when the compensation direction information is the second compensation direction, characterizing that the lower plate of the auxiliary correction capacitor of the P auxiliary correction capacitor array is connected with a second reference voltage, and the lower plate of the auxiliary correction capacitor of the N auxiliary correction capacitor array is connected with a first reference voltage.
13. A SAR ADC offset error correction circuit based on a differential structure is applied to the correction method of any one of claims 1-12, and is characterized by comprising the following steps:
the auxiliary correction capacitor array comprises a P auxiliary correction capacitor array and an N auxiliary correction capacitor array;
the P auxiliary correction capacitor array and the N auxiliary correction capacitor array respectively comprise N auxiliary correction capacitors and a first voltage selection unit; wherein n is a positive integer;
the first voltage selection unit connects the lower plate of each auxiliary correction capacitor in the P auxiliary correction capacitor array and the N auxiliary correction capacitor array to a first reference voltage or a second reference voltage or a common mode voltage through a plurality of switches;
the main DAC capacitor array comprises a P-end main DAC capacitor array and an N-end main DAC capacitor array;
the P-end main DAC capacitor array and the N-end main DAC capacitor array respectively comprise m main DAC capacitors and a second voltage selection unit; wherein m is a positive integer, and m is more than or equal to n;
the second voltage selection unit controls the lower plate of each main DAC capacitor in the P-terminal main DAC capacitor array to be connected to the first reference voltage or the first input voltage or the common mode voltage through a plurality of switches, and/or controls the lower plate of each main DAC capacitor in the N-terminal main DAC capacitor array to be connected to the second reference voltage or the second input voltage or the common mode voltage;
the upper plates of all auxiliary correction capacitors of the P-auxiliary correction capacitor array and the upper plates of all main DAC capacitors of the P-end main DAC capacitor array are connected to a first input end of the comparator; the upper plates of all auxiliary correction capacitors of the N-auxiliary correction capacitor array and the upper plates of all main DAC capacitors of the N-terminal main DAC capacitor array are connected to the second input end of the comparator;
a third voltage selection unit, configured to connect upper plates of all auxiliary correction capacitors in the P-auxiliary correction capacitor array and all main DAC capacitors in the P-side main DAC capacitor array to the common mode voltage through a switch;
a fourth voltage selection unit, configured to connect upper plates of all the auxiliary correction capacitors in the N-auxiliary correction capacitor array and all the main DAC capacitors in the N-terminal main DAC capacitor array to the common mode voltage through a switch;
the input end of the correction logic module is connected with the output end of the comparator; the output end of the correction logic module is connected with the first voltage selection unit of the P auxiliary correction capacitor array and the first voltage selection unit of the N auxiliary correction capacitor array;
the input end of the SAR logic module is connected with the output end of the comparator; and the output end of the SAR logic module is connected with the second voltage selection unit of the P-end main DAC capacitor array and the N-end main DAC capacitor array.
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