CN108983857A - 基准电压电路及半导体装置 - Google Patents

基准电压电路及半导体装置 Download PDF

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CN108983857A
CN108983857A CN201810535941.3A CN201810535941A CN108983857A CN 108983857 A CN108983857 A CN 108983857A CN 201810535941 A CN201810535941 A CN 201810535941A CN 108983857 A CN108983857 A CN 108983857A
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transistor
reference voltage
voltage circuit
depletion mode
enhancement
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杉浦正
杉浦正一
前谷文彦
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Ablic Inc
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    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/265—Current mirrors using bipolar transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0883—Combination of depletion and enhancement field effect transistors

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Abstract

基准电压电路及半导体装置。在基准电压电路中，由多个晶体管构成耗尽型晶体管和/或增强型晶体管，将耗尽型晶体管和增强型晶体管配置在共质心(公共重心)，避免了半导体装置的树脂密封等的应力引起特性变动的影响，并且产品差异少。

Description

基准电压电路及半导体装置
技术领域
本发明涉及基准电压电路及半导体装置。
背景技术
作为基准电压电路，公知图7所示的组合耗尽型晶体管与增强型晶体管而成的基准电压电路700(例如参照日本特表2012-531825号专利文献1)。
基准电压电路700具备耗尽型晶体管710、增强型晶体管720、以及输出基准电压VREF的端子730。
参照图8，对基准电压电路700的动作进行说明。将晶体管710的阈值电压设为VTND，则该晶体管710的电压与电流的关系如特性801那样表示。将晶体管720的阈值电压设为VTNE，则该晶体管720的电压与电流的关系如特性802那样表示。将等于特性801的截距值的电流流入增强型晶体管720而产生的电压作为基准电压VREF向端子730输出。
专利文献1：日本特表2012-531825号公报
发明内容
一般而言，公知半导体装置由于树脂密封(封装)产生的应力的影响而引起特性变动。
例如，当在x轴方向配置有晶体管710和晶体管720的半导体装置被树脂密封时，在x轴方向上施加应力时，晶体管710和晶体管720的特性变动可能产生偏差。即，特性801和特性802可能相对于期望的特性产生偏差。
本发明是为了避免半导体装置的树脂密封等的应力产生的特性变动的影响而完成的，提供具备产品差异少的基准电压电路的半导体装置。
用于解决课题的手段
本发明的基准电压电路的特征在于：耗尽型晶体管和/或增强型晶体管由多个晶体管构成，耗尽型晶体管与增强型晶体管以共质心(common centroid)的方式配置，该共质心是公共重心。
发明效果
根据本发明的基准电压电路，能够提供一种半导体装置，其具备避免导体装置的树脂密封等的应力引起的特性变动的影响且产品差异少的基准电压电路。
附图说明
图1是示出本发明的第一实施方式的基准电压电路的说明图。
图2是示出第一实施方式的基准电压电路的其他例子的说明图。
图3是示出第一实施方式的基准电压电路的其他例子的说明图。
图4是示出第一实施方式的基准电压电路的其他例子的说明图。
图5是示出第一实施方式的基准电压电路的其他例子的说明图。
图6是示出本发明的第二实施方式的基准电压电路的说明图。
图7是示出一般的基准电压电路的电路图。
图8是图7的基准电压电路的动作说明图。
标号说明
110、210、410、610：耗尽型晶体管；120、220、420、620：增强型晶体管；640、650：晶体管；130：端子。
具体实施方式
图1是示出本发明的第一实施方式的基准电压电路的说明图。
基准电压电路100具备耗尽型晶体管110、增强型晶体管120、以及输出基准电压VREF的端子130。
晶体管110通过串联连接2个耗尽型晶体管111及112而构成。晶体管120通过串联连接2个增强型晶体管121及122而构成。
基准电压电路100的动作与一般的由耗尽型晶体管110以及增强型晶体管120构成的基准电压电路同样，将基准电压VREF向端子130输出。
此处，基准电压电路100的晶体管111和晶体管112为相同尺寸(W长和L长)，晶体管121和晶体管122为相同尺寸(W长和L长)。并且，如图1所示，晶体管111、112、121、122以在半导体装置上大致共质心(公共重心)的方式配置。
即，晶体管111、112、121、122配置成点对称，实现共质心(公共重心)。
在如上述配置的基准电压电路100中，即使由于树脂密封等的应力而使得在x轴方向或y轴方向上晶体管的特性变化，晶体管110与晶体管120也受到相同的影响。因此，晶体管110和晶体管120能够产生相同的特性变动，因此，具有能够减少变动后的特性相对于期望的电压电流特性的偏差的效果。
如上所述，在基准电压电路100中，晶体管110和晶体管120以在半导体装置上大致共质心的方式配置，因此，能够提供一种半导体装置，其具备避免半导体装置的树脂密封等的应力引起的特性变动的影响且产品差异少的基准电压电路。
图2是示出第一实施方式的基准电压电路的其他例子的说明图。
在基准电压电路200中，各自由3个晶体管构成耗尽型晶体管210和增强型晶体管220。
晶体管210通过串联连接3个耗尽型晶体管211、212及213而构成。晶体管220通过串联连接3个晶体管221、222及223而构成。
此处，与基准电压电路100同样地构成各晶体管，如图2所示那样以在半导体装置上大致共质心(公共重心)的方式配置。这样构成的基准电压电路200也能够得到同样的效果。
此外，基准电压电路200也可以如图3所示那样以在半导体装置上大致共质心(公共重心)的方式配置。即，将晶体管211、212、223与晶体管213、221、222配置成线对称，从而实现共质心(公共重心)。
图4是示出第一实施方式的基准电压电路的其他例子的说明图。
在基准电压电路400中，各自由2个晶体管构成耗尽型晶体管410和增强型晶体管420。
晶体管410通过并联连接2个耗尽型晶体管411及412构成。晶体管420通过并联连接2个增强型晶体管421及422而构成。
基准电压电路400与图1的基准电压电路100同样地以在半导体装置上大致共质心(公共重心)的方式配置。这样构成的基准电压电路400也能够得到同样的效果。
另外，在基准电压电路400中，各晶体管并联连接2个晶体管而构成，但也可以并联连接2个以上，将它们以在半导体装置上大致共质心(公共重心)的方式配置。
图5是示出第一实施方式的基准电压电路的其他例子的说明图。
基准电压电路500具备耗尽型晶体管110、增强型晶体管120、以及输出基准电压VREF的端子130。晶体管120通过串联连接2个增强型晶体管121及122而构成。
在图1的基准电压电路100中，耗尽型晶体管110通过串联连接2个耗尽型的晶体管111及112而构成，但如图5所示，即使由1个晶体管构成，也能够以在半导体装置上大致共质心(公共重心)的方式配置。
另外，在图5的基准电压电路500中，说明了耗尽型晶体管110由1个晶体管构成的例子，但可以由1个晶体管构成增强型晶体管120。
以上说明的第一实施方式的基准电压电路用1个～3个晶体管构成各晶体管，但也可以串联或并联连接3个以上，将它们以在半导体装置上大致共质心(公共重心)的方式配置。
图6是示出本发明的第二实施方式的基准电压电路的说明图。
基准电压电路600具备耗尽型晶体管610、增强型晶体管620、以及构成电流镜电路的晶体管640及晶体管650。基准电压电路600是通过电流镜电路将晶体管610与晶体管620结合而构成的，基本的动作与第一实施方式的基准电压电路相同。基准电压电路600与第一实施方式的基准电压电路同样地由多个晶体管构成。
晶体管610通过串联连接2个耗尽型晶体管611及612而构成。晶体管620通过串联连接2个晶体管621及622而构成。晶体管640通过串联连接2个晶体管641及642而构成。晶体管650通过串联连接2个晶体管651及652而构成。
各晶体管与第一实施方式的基准电压电路同样地构成。并且，例如与基准电压电路100同样地，将晶体管610和晶体管620以在半导体装置上大致共质心(公共重心)的方式配置，将晶体管640和晶体管650以在半导体装置上大致共质心(公共重心)的方式配置。这样构成的基准电压电路600也能够的得到同样的效果。
另外，在第二实施方式的基准电压电路600中，由2个晶体管构成各晶体管，但也可以与第一实施方式同样地串联或者并联连接2个以上，将它们以在半导体装置上大致共质心(公共重心)的方式配置。

Claims (10)

1.一种基准电压电路，该基准电压电路具备作为电流源的耗尽型晶体管和作为负载的增强型晶体管，其特征在于，
所述耗尽型晶体管和/或所述增强型晶体管由多个晶体管构成，
所述耗尽型晶体管与所述增强型晶体管以共质心的方式配置，该共质心是公共重心。
2.根据权利要求1所述的基准电压电路，其中，
所述耗尽型晶体管与所述增强型晶体管配置成点对称。
3.根据权利要求1所述的基准电压电路，其特征在于，
所述耗尽型晶体管与所述增强型晶体管配置成线对称。
4.根据权利要求1所述的基准电压电路，其特征在于，
所述耗尽型晶体管与所述增强型晶体管经由电流镜电路连接。
5.根据权利要求2所述的基准电压电路，其特征在于，
所述耗尽型晶体管与所述增强型晶体管经由电流镜电路连接。
6.根据权利要求3所述的基准电压电路，其特征在于，
所述耗尽型晶体管与所述增强型晶体管经由电流镜电路连接。
7.根据权利要求4所述的基准电压电路，其特征在于，
构成所述电流镜电路的晶体管由多个晶体管构成，
所述多个晶体管以共质心的方式配置，该共质心是公共重心。
8.根据权利要求5所述的基准电压电路，其特征在于，
构成所述电流镜电路的晶体管由多个晶体管构成，
所述多个晶体管以共质心的方式配置，该共质心是公共重心。
9.根据权利要求6所述的基准电压电路，其特征在于，
构成所述电流镜电路的晶体管由多个晶体管构成，
所述多个晶体管以共质心的方式配置，该共质心是公共重心。
10.一种半导体装置，其具备权利要求1至9中的任意一项所述的基准电压电路。
CN201810535941.3A 2017-06-01 2018-05-30 基准电压电路及半导体装置 Pending CN108983857A (zh)

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KR102130322B1 (ko) * 2019-01-03 2020-07-06 청주대학교 산학협력단 박막 트랜지스터 논리회로 및 그 제조방법

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