CN108735736B - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- CN108735736B CN108735736B CN201810361018.2A CN201810361018A CN108735736B CN 108735736 B CN108735736 B CN 108735736B CN 201810361018 A CN201810361018 A CN 201810361018A CN 108735736 B CN108735736 B CN 108735736B
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Abstract
提供一种半导体装置,该半导体装置能够确保体二极管的可靠性,能够确保器件动作的稳定性。具有:有源区域,其设置于第1导电型的半导体层,在有源区域形成有在半导体层的厚度方向流过主电流的MOS晶体管;以及终端区域,其设置于有源区域的周围,终端区域具有沿有源区域而设置的缺陷检测器件,缺陷检测器件由具有第1主电极和第2主电极的二极管构成,该第1主电极是在半导体层的第1主面之上沿有源区域而设置的,该第2主电极设置于半导体层的第2主面侧。
Description
技术领域
本发明涉及半导体装置,特别是涉及使用了宽带隙半导体的宽带隙半导体装置。
背景技术
为了实现逆变器等功率电子设备的省电化,需要降低绝缘栅型双极晶体管(Insulated Gate Bipolar Transistor:IGBT)以及金属/氧化物/半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor:MOSFET)这样的开关器件的电力损耗。
电力损耗由开关器件的导通时的损耗以及通断切换时的损耗决定,因此为了使上述损耗降低,正在推进使用了碳化硅(SiC)、氮化镓(GaN)等宽带隙半导体的宽带隙半导体装置的开发。
在使用功率MOSFET作为开关器件的情况下,能够使环流电流(续流电流)流过功率MOSFET的寄生二极管(称为体二极管)。已知通过利用体二极管,从而能够将与功率MOSFET并联配置的续流二极管小型化或省略,已被应用于电力变换电路。
SiC半导体装置存在下述问题,即,如果使用p型载流子和n型载流子而进行双极动作,则由于载流子的复合能而导致晶体缺陷扩展,电阻增大。该问题在上述的使环流电流流过体二极管的情况下也会发生,由功率MOSFET的导通电阻增大引起的电力损耗的增大以及动作故障的发生等成为问题。
专利文献1中公开了在SiC-MOSFET流过大电流而施加电流应力,使晶体缺陷扩展而进行筛选的方法。就该现有技术的筛选方法而言,采用了下述方法,即,将芯片状态的双极器件的温度设定为150~230℃,在双极器件持续流过电流密度120~400A/cm2的正向电流,从而使体二极管的晶体缺陷扩展至饱和状态,然后,判别正向电阻的变化程度。
专利文献1:日本再表2014/148294号公报
就SiC-MOSFET而言,为了确保器件动作的稳定性,保证市场中的可靠性,重要的是提高体二极管的可靠性。通过如专利文献1那样,以芯片状态对体二极管通电,在使晶体缺陷扩展之后对正向特性测定而进行评价,从而能够确保体二极管的可靠性,能够确保器件动作的稳定性。
但是,在专利文献1的筛选方法中,难以通过电流应力使在SiC-MOSFET的有源区域的外侧设置的终端区域处的晶体缺陷充分地扩展。作为其原因,被认为是复合能难以到达至在有源区域的外侧设置的终端区域的晶体缺陷,不会向晶体缺陷施加所设想的应力,另外,就由胡萝卜缺陷(carrot defect)这样的宏观缺陷引起的晶体缺陷而言,不会扩展至饱和状态。
在后者的情况下,在宏观缺陷处于SiC-MOSFET的有源区域内的情况下,能够通过测试工序的耐压特性评价进行判别,但在有源区域之外存在宏观缺陷,且通过向体二极管的电流应力无法达到缺陷扩展所需的复合能的情况下,无法评价在将体二极管用作续流二极管的期间,有源区域之外的晶体缺陷是否发生扩展而对体二极管造成影响,可知在专利文献1的筛选方法的情况下,无法充分地确保体二极管的可靠性。
发明内容
本发明就是为了解决上述问题而提出的,其目的在于提供能够确保体二极管的可靠性,能够确保器件动作的稳定性的半导体装置。
本发明涉及的半导体装置具有:有源区域,其设置于第1导电型的半导体层,在该有源区域形成有在所述半导体层的厚度方向流过主电流的MOS晶体管;以及终端区域,其设置于所述有源区域的周围,所述终端区域具有沿所述有源区域而设置的缺陷检测器件,所述缺陷检测器件由具有第1主电极和第2主电极的二极管构成,该第1主电极是在所述半导体层的第1主面之上沿所述有源区域而设置的,该第2主电极设置于所述半导体层的第2主面侧。
发明的效果
可以得到能够确保MOS晶体管的体二极管的可靠性,能够确保器件动作的稳定性的半导体装置。
附图说明
图1是表示本发明涉及的实施方式1的半导体装置的上表面结构的俯视图。
图2是表示本发明涉及的实施方式1的半导体装置的剖面结构的剖视图。
图3是表示二极管的上升波形的图。
图4是表示二极管的耐压波形的图。
图5是表示本发明涉及的实施方式1的半导体装置的制造工序的剖视图。
图6是表示本发明涉及的实施方式1的半导体装置的制造工序的剖视图。
图7是表示本发明涉及的实施方式1的半导体装置的制造工序的剖视图。
图8是表示本发明涉及的实施方式1的半导体装置的制造工序的剖视图。
图9是表示本发明涉及的实施方式1的半导体装置的制造工序的剖视图。
图10是表示本发明涉及的实施方式1的半导体装置的变形例1的上表面结构的俯视图。
图11是表示本发明涉及的实施方式1的半导体装置的变形例2的上表面结构的俯视图。
图12是表示本发明涉及的实施方式1的半导体装置的变形例2的剖面结构的剖视图。
图13是表示本发明涉及的实施方式1的半导体装置的变形例2的剖面结构的剖视图。
图14是表示本发明涉及的实施方式1的半导体装置的变形例3的上表面结构的俯视图。
图15是表示本发明涉及的实施方式1的半导体装置的变形例3的晶片状态下的配置例的图。
图16是表示本发明涉及的实施方式1的半导体装置的变形例4的剖面结构的剖视图。
图17是表示本发明涉及的实施方式2的半导体装置的剖面结构的剖视图。
图18是表示本发明涉及的实施方式2的半导体装置的剖面结构的剖视图。
标号的说明
12 外延层,25 漏极电极,26 电极焊盘,27 阳极电极,34 绝缘膜,35 凹槽部,102缺陷检测器件。
具体实施方式
<前言>
“MOS”这一术语以前用于金属/氧化物/半导体的接合构造,采用了Metal-Oxide-Semiconductor的首字母。然而,特别是就具有MOS构造的场效应晶体管(以下,简称为“MOS晶体管”)而言,从近年来的集成化、制造工艺的改善等观点出发,改善了栅极绝缘膜、栅极电极的材料。
例如就MOS晶体管而言,主要从以自对准的方式形成源极、漏极的观点出发,作为栅极电极的材料,取代金属而采用了多晶硅。另外,从改善电气特性的观点出发,作为栅极绝缘膜的材料,采用了高介电常数的材料,但该材料并不一定限定于氧化物。
因此,“MOS”这一术语并不一定是仅限定于金属/氧化物/半导体的层叠构造而采用的,本说明书中也不会以上述限定作为前提。即,鉴于技术常识,在这里,“MOS”不仅作为源于其词源的简称,广义地具有还包含导电体/绝缘体/半导体的层叠构造的意义。
另外,在以下的记载中,关于杂质的导电型,通常将n型定义为“第1导电型”,将p型定义为“第2导电型”,但也可以是其相反的定义。
<实施方式1>
<装置结构>
图1是表示本发明涉及的半导体装置的实施方式1的半导体装置100的上表面结构的俯视图。此外,半导体装置100具有向碳化硅MOS晶体管(SiC-MOSFET)101附加了缺陷检测器件102的结构。
如图1所示,半导体装置100在具有矩形外形的半导体装置100的中央设置有SiC-MOSFET 101,沿SiC-MOSFET 101的外周设置有缺陷检测器件102。
在半导体装置100的中央部设置有SiC-MOSFET 101的源极电极24,源极电极24的俯视观察形状呈矩形的一边的中央部向内侧凹陷的形状,以进入至源极电极24的向内侧凹陷的部分的方式,设置有栅极焊盘31。另外,源极电极24的4个角部中的1个角部,即,图1的例子中的设置有栅极焊盘31的那一侧的1个角部被切成“L”字状而成为切口部,从栅极焊盘31延伸出的栅极配线32是沿源极电极24的外形而设置的,源极电极24由栅极配线32包围。
在图1的区域“X”,出于方便起见,将源极电极24的一部分省略,从而示出在源极电极24的下方设置的单位单元(unit cell)UC。栅极焊盘31是被从外部的控制电路(未图示)施加栅极电压的部位,在此施加的栅极电压经过栅极配线32而供给至SiC-MOSFET 101的最小单位构造即单位单元UC的栅极电极(未图示)。
源极电极24设置于配置有多个单位单元UC的有源区域之上,成为将各单位单元UC的源极区域(未图示)进行电并联连接的结构。因此,可以说是源极电极24的俯视观察形状与有源区域的俯视观察形状相同。
此外,在本发明中,“有源区域”是指在半导体装置的接通状态下主电流流过的区域,“终端区域”是指有源区域的周围的区域,栅极焊盘31以及栅极配线32的配置区域也包含于“终端区域”。另外,“杂质浓度”表示的是各区域的杂质浓度的峰值。并且,在以下部分,“外周侧”是指在图1所示的半导体装置100的俯视观察方向(俯视方向)上,朝向半导体装置100外的方向,“内周侧”是与“外周侧”相反的方向。
在栅极配线32的更外周侧,与栅极配线32隔开间隔而设置有缺陷检测器件102的阳极电极27(第1主电极)。阳极电极27是从在半导体装置100的1个角部设置的俯视观察形状为四边形状的电极焊盘26延伸,沿栅极配线32而设置的。此外,电极焊盘26设置为进入至源极电极24的切口部。
此外,源极电极24的俯视观察形状、栅极焊盘31的配置以及俯视观察形状、电极焊盘26的配置以及俯视观察形状并不限定于上述内容。
图2中示出了图1中的A-A线所示的有源区域的剖面结构、和B-B线所示的终端区域的剖面结构。
如图2的有源区域所示那样,SiC-MOSFET 101具有:包含n型杂质的SiC外延层12(半导体层),其设置在包含n型杂质的SiC基板11的主面之上;p型阱区域13,其选择性地在外延层12的上层部设置多个;以及n型(第1导电型)源极区域14及p型(第2导电型)阱接触区域15,其设置于阱区域13的上层部。
阱接触区域15是为了通过使源极区域14与阱区域13的电位相同,由此使通断特性稳定而设置的,在剖视观察时设置为被源极区域14夹着。
在图2的终端区域,在阱区域13的外周侧的外延层12的上层部设置有用于确保耐压的耐压保持区域16。耐压保持区域16由多个p型杂质区域构成,在阱区域13的外周侧,设置为朝向外延层12的俯视方向的端部隔开间隔而延伸。此外,多个p型杂质区域的配置间隔、配置宽度以及杂质浓度是基于SiC-MOSFET 101的耐压等产品额定值而设定的。
如图2的有源区域所示,在外延层12的第1主面之上,以从相邻的阱区域13之间起覆盖于阱区域13的端缘部之上以及源极区域14的端缘部之上的方式设置栅极绝缘膜21,在栅极绝缘膜21之上设置有栅极电极22。
栅极绝缘膜21以及栅极电极22被层间绝缘膜23覆盖,以与源极电极24接触的方式设置在未被层间绝缘膜23覆盖的源极区域14以及阱接触区域15的上部。此外,层间绝缘膜23也设置于终端区域,将延伸至终端区域为止的栅极电极22覆盖。栅极电极22在终端区域,与以将层间绝缘膜23贯穿而到达至栅极电极22的方式设置的栅极配线32连接。
另外,以源极区域14、阱接触区域15与源极电极24进行欧姆接触的方式,在未被层间绝缘膜23覆盖的源极区域14以及阱接触区域15的上部设置例如硅化镍膜,但省略了图示。
在外延层12的第2主面侧、更具体而言在SiC基板11的与设置有外延层12的那一侧相反侧的主面(背面)之上,设置有漏极电极25。漏极电极25也设置于终端区域,在设置于终端区域最外周的缺陷检测器件102处,作为阴极电极(第2主电极)起作用。
缺陷检测器件102具有阳极电极27,该阳极电极27设置于外延层12之上,与外延层12进行肖特基接触,该缺陷检测器件102是将漏极电极25用作阴极电极的肖特基势垒二极管。
这样,通过将阳极电极27与电极焊盘26连接,从而容易经由电极焊盘26对终端区域处的晶体缺陷进行检测。
<动作>
首先,对半导体装置100中的SiC-MOSFET 101的动作进行说明。就SiC-MOSFET 101而言,如果对栅极电极22施加大于或等于阈值的正的电压,则在阱区域13的表层形成作为主电流的路径的沟道。如果在该状态下对漏极电极25施加正的电压,则主電流从漏极电极25经由外延层12、阱区域13的表层(沟道)、源极区域14而流过源极电极24。
另一方面,如果使栅极电极22的正的电压小于阈值、或向栅极电极22施加负的电压,则沟道消失。由此,即使向漏极电极25施加高电压,也不会在漏极-源极之间流过电流。另外,由于设置有耐压保持区域16,因此能够缓和向终端区域的电场集中。
接下来,对基于缺陷检测器件102的筛选方法进行说明。如果对阳极电极27施加正的电压(正向电压)而不断增大该电压,则在阳极电极27的附近没有宏观缺陷的情况下,得到由肖特基势垒引起的二极管的上升波形。另一方面,如果在阳极电极27的附近存在如胡萝卜缺陷这样较大的缺陷,则在该部分无法适当地形成肖特基势垒,因此无法得到二极管的上升波形。图3是表示二极管的上升波形的图,在横轴示出阳极电压(V),在纵轴示出阳极电流(A),将没有宏观缺陷的情况下的特性C1以实线示出,将存在宏观缺陷的情况下的特性C2以虚线示出。根据图3可知,在没有宏观缺陷的情况下,示出二极管的正向特性,即,直至阳极电压达到导通电压为止不会流动阳极电流,如果达到导通电压,则阳极电流急剧地开始流动,但在存在宏观缺陷的情况下,在阳极电压达到导通电压之前就会有阳极电流流动,不会作为二极管起作用。
这样,在得到二极管的上升波形的情况下,判定为在终端区域不存在如胡萝卜缺陷这样较大的缺陷,在无法得到二极管的上升波形的情况下,判定为在终端区域存在如胡萝卜缺陷这样较大的缺陷。当在终端区域存在胡萝卜缺陷等的情况下,评价为有可能在将体二极管用作续流二极管的期间,该晶体缺陷扩展而对体二极管造成影响,将被作出上述评价的半导体装置作为无法确保体二极管的可靠性的装置而排除在产品之外。
此外,在使用肖特基势垒二极管作为缺陷检测器件102的情况下,具有下述特征,即,正向动作成为单极动作,因此如图3所示成为具有电阻成分的上升波形,容易掌握缺陷扩展后的情况下的特性变动。
接下来,如果向阳极电极27施加负的电压或向阴极电极25施加正的电压,使反向电压不断增大,则在阳极电极27的附近没有宏观缺陷的情况下,得到由肖特基势垒产生的二极管的耐压波形(泄漏电流波形)。另一方面,如果在阳极电极27的附近存在如胡萝卜缺陷这样较大的缺陷,则无法得到二极管的耐压波形。图4是表示二极管的耐压波形的图,在横轴示出阴极电压(V),在纵轴示出泄漏电流(mA),将没有宏观缺陷的情况下的特性C3以实线示出,将存在宏观缺陷的情况下的特性C4以虚线示出。根据图4可知,在没有宏观缺陷的情况下,示出二极管的反向特性,即,直至达到击穿电压为止,仅流动微小的泄漏电流,如果达到击穿电压,则急剧地流过泄漏电流,但在存在宏观缺陷的情况下,在阴极电压达到击穿电压之前就有大的泄漏电流流动,二极管不具有耐压性。
这样,在得到二极管的耐压波形的情况下,判定为在终端区域不存在如胡萝卜缺陷这样较大的缺陷,在无法得到二极管的耐压波形的情况下,判定为在终端区域存在如胡萝卜缺陷这样较大的缺陷。当在终端区域存在胡萝卜缺陷等的情况下,评价为有可能在将体二极管用作续流二极管的期间,该晶体缺陷扩展而对体二极管造成影响,将被作出上述评价的半导体装置作为无法确保体二极管的可靠性的装置而排除在产品之外。
通过利用如上所述通过缺陷检测器件102所检测的二极管的正向特性以及反向特性中的至少一者,从而能够对通过针对SiC-MOSFET 101的有源区域处的体二极管的电流应力测试无法检测的终端区域处的晶体缺陷进行检测。由此,能够对下述半导体装置100进行判定,即,由于诸如在SiC-MOSFET 101的有源区域处的体二极管流过环流电流等的、针对体二极管的应力,有可能由于在终端区域处晶体缺陷扩展而无法确保器件动作的稳定性。
此外,对于终端区域处的晶体缺陷的扩展而言,不仅是在有源区域处的体二极管流过环流电流的情况下的双极动作对该扩展作出贡献,经由终端区域处的阱接触区域15而流过环流电流的情况下的双极动作也对该扩展作出贡献。
此外,上述筛选既可以对晶片状态的半导体装置100进行,也可以对在切割工序中切割成各个芯片之后的芯片状态的半导体装置100进行。
缺陷检测器件102通过以将SiC-MOSFET 101包围的方式配置而得到以下的效果。即,在对二极管的正向特性进行检测的情况下,需要在对晶体缺陷进行检测的部分存在肖特基结,因此通过以将SiC-MOSFET 101包围的方式设置,从而能够抑制晶体缺陷的检测遗漏,能够进行有效的判定。
在对二极管的反向特性(耐压特性)进行检测的情况下,通过负偏置使耗尽层扩展至缺陷区域,从而对耐压特性的故障进行检测。如果以将SiC-MOSFET 101包围的方式配置,则即使在施加较低电压,耗尽层不大的情况下,也能够抑制晶体缺陷的检测遗漏,能够进行有效的判定。
另外,通过以将SiC-MOSFET 101包围的方式配置缺陷检测器件102,从而能够抑制半导体装置100的有效面积的减少,能够有效地实现通过设置缺陷检测器件102而带来的效果。
此外,缺陷检测器件102也可以不将SiC-MOSFET 101完全包围,例如也可以采用阳极电极27在中途中断的结构。
缺陷检测器件102优选充分地远离,以不与从耐压保持区域16产生的耗尽层进行干涉,由此,在向SiC-MOSFET 101的漏极电极25施加了高电压的情况下不造成影响。外延层12的厚度有时设计为与耗尽层扩展的区域相同程度,从耐压保持区域16的最外周至缺陷检测器件102为止的距离可以设计为与外延层12的厚度相同程度。
<制造方法>
接下来,对实施方式1的半导体装置100的制造方法,使用依次示出制造工序的剖视图即图5~图9进行说明。此外,以下的制造方法为一个例子,特别是对于步骤等而言,在不产生障碍的范围即使进行变更也没有问题。
首先,在图5所示的工序中,准备SiC基板11,在SiC基板11之上通过公知的外延生长法形成n型外延层12。该SiC基板11处于切割前的晶片状态。SiC基板11使用的是包含n型杂质的电阻率为0.015~0.028Ωcm的基板,但并不限定于此,例如也可以使用电阻率为几MΩcm的半绝缘性基板。通过使用半绝缘性基板,能够降低寄生电阻。
SiC是带隙比Si大的宽带隙半导体,将宽带隙半导体作为基板材料而构成的开关器件以及二极管的耐压高,容许电流密度也高,因此与硅半导体装置相比,能够实现小型化,通过使用上述小型化的开关器件以及二极管,从而能够实现装有上述器件的半导体装置模块的小型化。
另外,耐热性也高,因此也能够实现散热器的散热鳍片的小型化,能够基于风冷进行冷却而非水冷,能够实现半导体装置模块的进一步小型化。
外延层12的n型杂质的浓度例如是1×1013cm-3~1×1018cm-3,厚度是4μm~200μm,但并不限定于此,能够与半导体装置100的额定值相对应地进行适当设定。
接下来,使用公知的光刻技术,在外延层12之上形成与阱区域13对应的部分成为开口部的抗蚀掩模,经由该抗蚀掩模进行铝(Al)等p型杂质的离子注入,形成图6示出的阱区域13。阱区域13的深度是0.3μm~2.0μm,杂质浓度是1×1015cm-3~1×1018cm-3。
同样地,使用公知的光刻技术,在外延层12之上形成与源极区域14对应的部分成为开口部的抗蚀掩模,经由该抗蚀掩模进行氮(N)等n型杂质的离子注入,形成图6示出的源极区域14。源极区域14的深度设为底面不超出阱区域13的底面的深度,使杂质浓度超过阱区域13的杂质浓度,例如设为1×1017cm-3~1×1021cm-3。
另外,使用公知的光刻技术,在外延层12之上形成与阱接触区域15对应的部分成为开口部的抗蚀掩模,经由该抗蚀掩模进行Al等p型杂质的离子注入,形成图6示出的阱接触区域15。阱接触区域15的杂质浓度设为1×1017cm-3~1×1021cm-3,深度设为0.3μm~1.0μm,使该阱接触区域15与阱区域13电连接。此外,在形成阱接触区域15时,优选将基板温度设为大于或等于150℃而进行离子注入。
另外,使用公知的光刻技术,在外延层12之上形成与耐压保持区域16对应的部分成为开口部的抗蚀掩模,经由该抗蚀掩模进行Al等p型杂质的离子注入,形成图6示出的耐压保持区域16。耐压保持区域16的杂质浓度设为1×1013cm-3~1×1018cm-3,深度设为0.3μm~2.0μm。耐压保持区域16如图6所示由多个p型杂质区域构成,各杂质区域的宽度以及间隔也可以阶段性地变化以抑制电场集中。另外,也可以朝向半导体装置100的外周侧使杂质浓度阶段性地降低。此外,当在阱区域13和耐压保持区域16使杂质浓度相同的情况下,也可以通过相同的工序形成两者。
另外,在上述部分中,说明了为了选择性地形成杂质区域而使用抗蚀掩模,但也可以将氧化硅膜用作掩模。在形成氧化硅膜制的掩模的情况下,将氧化硅膜形成于外延层12之上,然后经过光刻工序以及蚀刻工序,将用于进行杂质注入的开口部形成于氧化硅膜而作为掩模。
将形成杂质区域之后的晶片状态的SiC基板11搭载于热处理装置,在Ar气等非活性气体气氛中进行退火。退火例如以1300℃~1900℃的温度,进行30秒~1小时。通过该退火,使所离子注入的N等n型杂质以及Al等p型杂质激活。
接下来,在图7所示的工序中,在外延层12之上形成氧化硅膜OX。氧化硅膜OX例如是使用热氧化法或CVD(chemical vapor deposition)法等沉积法而形成的,然后实施氮、氨、NO以及N2O等气氛中的热处理。此外,氧化硅膜OX以成为作为栅极绝缘膜起作用的厚度的方式形成,但在终端区域,在氧化硅膜OX的形成之前形成有比栅极绝缘膜厚的场绝缘膜,其通过氧化硅膜OX的形成工序进一步变厚而成为场绝缘膜FX。此外,在终端区域的形成缺陷检测器件的区域,不形成场绝缘膜FX。
接下来,如图7所示,在氧化硅膜OX以及场绝缘膜FX之上,例如通过CVD法形成多晶硅膜ML。在多晶硅膜ML中也可以含有如磷(P)以及硼(B)这样的杂质。通过含有杂质,从而能够实现低薄层电阻。此外,在终端区域的形成缺陷检测器件的区域,不形成多晶硅膜ML。
接下来,在图8所示的工序中,使用公知的光刻技术,在多晶硅膜ML之上,形成将与栅极电极22对应的部分覆盖的抗蚀掩模,将该抗蚀掩模作为蚀刻掩模,通过蚀刻将多晶硅膜ML选择性地去除,从而形成栅极电极22。
然后,将栅极电极22以及其之上的抗蚀掩模作为蚀刻掩模,通过蚀刻将氧化硅膜OX选择性地去除,从而形成栅极绝缘膜21。此外,在终端区域,场绝缘膜FX也被去除了与氧化硅膜OX的厚度相当的厚度,但与场绝缘膜FX的厚度相比,氧化硅膜OX的厚度薄,后续通过层间绝缘膜的形成工序来弥补。
接下来,以将栅极绝缘膜21以及栅极电极22覆盖的方式,例如通过CVD法形成氧化硅膜而作为层间绝缘膜23。此外,在终端区域,是在场绝缘膜FX之上形成层间绝缘膜23,但两者成为一体,因此称为层间绝缘膜23。
然后,如图8所示,将抗蚀掩模作为蚀刻掩模,在有源区域,形成使源极区域14以及阱接触区域15的至少一部分露出于底面的开口部OP1,在终端区域,形成使栅极电极22露出于底面的开口部OP2、和在形成缺陷检测器件的区域使外延层12露出于底面的开口部OP3。
然后,为了使通过蚀刻而露出的源极区域14、阱接触区域15与源极电极24进行欧姆接触,在层间绝缘膜23之上,在整个面例如通过溅射法或蒸镀法形成镍(Ni)膜,然后进行600℃~1000℃的热处理,从而形成硅化镍。层间绝缘膜23之上的未反应的Ni膜通过湿式蚀刻进行去除。另外,即使在形成缺陷检测器件的区域,也在开口部OP3的底面形成硅化镍,但硅化镍与外延层12进行肖特基接触,从而形成肖特基势垒二极管。另外,形成缺陷检测器件的区域在本工序的时刻处于被场绝缘膜FX以及层间绝缘膜23覆盖的状态,没有露出,从而不会形成硅化镍。然后,在下一导电膜的形成工序之前使形成缺陷检测器件的区域露出,从而能够形成与导电膜的肖特基接触。此外,就硅化镍而言,为了简化而省略图示。
接下来,在层间绝缘膜23之上通过溅射法或蒸镀法形成导电膜,以该导电膜将开口部OP1、OP2以及OP3填埋。该导电膜既可以是铝(Al)、铜(Cu)、钛(Ti)、镍(Ni)、钼(Mo)、钨(W)以及钽(Ta)等的金属膜,也可以是上述金属的氮化膜、或将上述金属作为主要成分而添加了大于或等于1种其他元素的合金膜。在这里,主要成分的元素表示构成合金的元素中的含量最多的元素。此外,层间绝缘膜23之上的导电膜也可以不是单层膜,而是包含大于或等于2层上述金属膜、氮化膜以及合金膜的层叠膜。
然后,通过蚀刻将层间绝缘膜23之上的导电膜进行图案化,从而如图9所示,形成与栅极电极22连接的栅极配线32、源极电极24以及阳极电极27。此外,阳极电极27也可以通过与栅极配线32以及源极电极24不同的工序而形成。
最后,在SiC基板11的背面形成漏极电极25,从而完成图2所示的半导体装置100。漏极电极25能够通过溅射法或蒸镀法形成钛(Ti)、镍(Ni)、银(Ag)、金(Au)等金属膜而得到。
<变形例1>
就图1示出的半导体装置100的俯视图而言,源极电极24与具有矩形外形的半导体装置100同样地具有带棱角的轮廓形状,栅极配线32也是沿源极电极24的外形而设置的,因此与源极电极24同样地具有带棱角的轮廓形状。
图10是表示实施方式1的变形例1涉及的半导体装置100A的上表面结构的俯视图。此外,在图10中,对于与使用图1而说明的半导体装置100相同的结构标注相同的标号,省略重复的说明。
如图10所示,就半导体装置100A而言,以抑制电场集中为目的,源极电极24的4个角部成为具有曲率的曲率部,栅极配线32也是沿源极电极24的外形而设置的,从而与源极电极24同样地具有曲率部。另外,阳极电极27的4个角部也成为曲率部,在通过将角部消除而产生的曲率部与曲率部之间的空间配置有电极焊盘26。
因此,与将源极电极24的4个角部中的1个角部设为切口部,在该切口部的空间配置有电极焊盘26的实施方式1的半导体装置100相比,能够以不使SiC-MOSFET的有效面积减少的状态实现与实施方式1同样的效果,并且实现耐压的提高。
另外,栅极配线32也是沿源极电极24的外形而设置的,从而与源极电极24同样地具有曲率部,能够抑制角部处的电场集中。
此外,在图10中,将电极焊盘26设为四边形状,当然也可以将该部分构成为圆形、椭圆形等,不具有角部。这对于图1示出的半导体装置100也是相同的。
<变形例2>
图11是表示实施方式1的变形例2涉及的半导体装置100B的上表面结构的俯视图。另外,在图12中,示出图11中的B-B线所示的终端区域的剖面结构,在图13中,示出图11中的C-C线所示的终端区域的剖面结构。此外,在图11~图13中,对与使用图1以及图2而说明的半导体装置100相同的结构标注相同的标号,省略重复的说明。
如图11~图13所示,半导体装置100B除了源极电极24的中央部分、栅极焊盘31的中央部分以及电极焊盘26的外侧角部的上部以外,被绝缘膜34覆盖。
绝缘膜34是为了在测试工序中对耐压特性进行测定时抑制来自外周部的沿面放电而配置的,例如由聚酰亚胺等树脂构成。
缺陷检测器件102之上大致被绝缘膜34覆盖,但在电极焊盘26的至少一部分上部,设置将绝缘膜34贯穿而到达至电极焊盘26的开口部OP13,从而能够从外部将检测端子等与电极焊盘26连接,能够进行测试工序中的耐压特性的评价测试。
另外,在源极电极24之上,设置将绝缘膜34贯穿而到达至源极电极24的开口部OP11,在栅极焊盘31之上,设置将绝缘膜34贯穿而到达至栅极焊盘31的开口部OP12,从而分别能够与外部设备电连接,能够将半导体装置100B用作SiC-MOSFET。
此外,图11所示的半导体装置100B具有图1示出的半导体装置100的上表面结构,但也可以设为图10示出的半导体装置100A的上表面结构。通过将源极电极24的4个角部设为曲率部,从而能够抑制电场集中,能够实现耐压的提高。
<变形例3>
图14是表示实施方式1的变形例3涉及的半导体装置100C的上表面结构的俯视图。此外,在图14中,对与使用图1而说明的半导体装置100相同的结构标注相同的标号,省略重复的说明。
如图14所示,就半导体装置100C而言,在以抑制电场集中为目的,源极电极24的4角具有曲率这一点上与图10示出的半导体装置100A相同,但并非是在通过将源极电极24的角部消除而产生的空间配置电极焊盘26,而是将阳极电极27也设为4角成为曲率部的形状,以从其中的1个角部的外缘延伸至半导体装置100C的对应的角部的外缘的方式配置有电极焊盘26。
并且,电极焊盘26是以越过半导体装置100C的角部的方式,即,以越过切割线而延伸的方式设置的。在图14中,出于方便起见以虚线示出半导体装置100C的端缘,但这是为了虚拟地表示晶片状态下的切割线,在晶片状态下,电极焊盘26是越过切割线而配置的。
通常,半导体装置在半导体晶片之上形成多个,在切割工序中切割成各个芯片而使它们分离,成为独立的半导体装置。图15是表示晶片状态下的半导体装置100C的配置的一个例子的图,是表示晶片WH的上表面结构的俯视图。
如图15所示,半导体装置100C的电极焊盘26以其一部分从半导体装置100C的角部凸出而越过切割线DL的方式设置,成为存在于晶片状态下的半导体装置100C的排列间隙处的结构。
就使用了缺陷检测器件102的终端区域处的晶体缺陷的检测而言,即使在晶片状态下也能够进行,因此通过从外部将检测端子与电极焊盘26连接,从而能够进行晶体缺陷的评价。
测试工序结束后,晶片WH在切割工序中被切割成各个芯片,因此越过切割线DL的电极焊盘26被去除,但就芯片状态的半导体装置100C而言,从阳极电极27的1个曲率部的外缘至半导体装置100C的对应的角部的外缘为止的部分残留下来。
这样,通过以电极焊盘26的一部分越过切割线DL的方式配置电极焊盘26,从而将由于设置电极焊盘26而引起的SiC-MOSFET 101的有效面积的减少抑制为最低限度。
另外,半导体装置100C在晶片状态下适于进行筛选,但如上所述,切割后仍残留有电极焊盘26,因此也可以针对在切割工序中切割成各个芯片之后的芯片状态的半导体装置100C进行。
此外,电极焊盘26的配置位置不限定于阳极电极27的4角这些位置,只要不与在晶片状态下相邻的半导体装置100C的阳极电极27接触,也可以在阳极电极27的直线部分设置。
<变形例4>
图16是表示实施方式1的变形例4涉及的半导体装置100D的终端区域处的结构的剖视图。此外,在图16中,对与使用图2而说明的半导体装置100的终端区域处的结构相同的结构标注相同的标号,省略重复的说明。
如图16所示,缺陷检测器件102的阳极电极27以底面侧***至形成于外延层12的凹槽部35的方式配置。凹槽部35处于其底面与外延层12的主面位置相比后退至外延层12内的位置,通过在此配置阳极电极27,从而阳极电极27的底面以及侧面与外延层12的比主面位置深的部分接触。
与该凹槽部35接触的阳极电极27的底面以及侧面成为对晶体缺陷进行检测的区域,与仅阳极电极27的底面与外延层12接触的半导体装置100相比,对晶体缺陷进行检测的区域变大。
另外,通过设置凹槽部35,从而阳极电极27的底面与外延层12的主面位置相比位于外延层12内,能够与存在于外延层12内的晶体缺陷更近。因此,还会实现晶体缺陷的检测变得更容易的效果。
此外,凹槽部35的深度能够任意地设定,但在形成了深凹槽的情况下,为了提高阳极电极27的覆盖度,在基于溅射来形成导电膜时对晶片进行加热即可。
<实施方式2>
在以上说明的实施方式1以及其变形例中,对使用肖特基势垒二极管作为缺陷检测器件102的例子进行了说明,但也可以使用PiN二极管作为缺陷检测器件102。
图17是表示本发明涉及的半导体装置的实施方式2的半导体装置200的终端区域处的结构的剖视图。此外,在图17中,对与使用图2而说明的半导体装置100的终端区域处的结构相同的结构标注相同的标号,省略重复的说明。另外,有源区域的结构与半导体装置100的有源区域相同,因此省略图示。
如图17所示,在半导体装置200中,通过PiN二极管构成缺陷检测器件102。即,缺陷检测器件102具有:阳极电极27,其设置于外延层12之上;p型阳极区域41,其与阳极电极27接触,选择性地设置于外延层12的上层部;以及p型接触区域42,其设置于阳极区域41的上层部。
阳极区域41以及接触区域42能够分别通过与有源区域的阱区域13以及阱接触区域15相同的工序形成,阳极区域41的深度为0.3μm~2.0μm,杂质浓度为1×1015cm-3~1×1018cm-3。另外,接触区域42的杂质浓度为1×1017cm-3~1×1021cm-3,深度为0.3μm~1.0μm。
此外,阳极区域41以及接触区域42也可以分别通过与有源区域的阱区域13以及阱接触区域15不同的工序形成,在该情况下,能够将各自的深度以及杂质浓度独立地进行设定。
在这里,如果将外延层12的n型杂质的浓度设为1×1013cm-3~1×1015cm-3左右,则外延层12能够称为i(Intrinsic)层,由阳极区域41、外延层12以及SiC基板11构成PiN二极管。
通过由PiN二极管构成缺陷检测器件102,从而能够在向缺陷检测器件102施加双极应力的基础上对特性变动进行检测。
此外,如果将外延层12的n型杂质的浓度设为1×1018cm-3左右,则外延层12不会成为i(Intrinsic)层,能够将缺陷检测器件102设为PN二极管。
<实施方式3>
在如上述说明的实施方式2中,对使用PiN二极管作为缺陷检测器件102的例子进行了说明,但也可以使用具有PiN二极管区域和肖特基势垒二极管区域的二极管作为缺陷检测器件102。
图18是表示本发明涉及的半导体装置的实施方式3的半导体装置300的终端区域处的结构的剖视图。此外,在图18中,对与使用图2而说明的半导体装置100的终端区域处的结构相同的结构标注相同的标号,省略重复的说明。另外,有源区域的结构与半导体装置100的有源区域相同,因此省略图示。
如图18所示,在半导体装置300中,缺陷检测器件102具有PiN二极管区域和肖特基势垒二极管区域。即,缺陷检测器件102具有:在外延层12之上设置的阳极电极27与选择性地设置于外延层12的上层部的p型阳极区域43、设置于阳极区域43的上层部的p型接触区域44接触的区域;以及在外延层12之上设置的阳极电极27与外延层12接触的区域。
在这里,如果将外延层12的n型杂质的浓度设为1×1013cm-3~1×1015cm-3左右,则外延层12能够称为i(Intrinsic)层,由阳极区域43、外延层12以及SiC基板11构成PiN二极管区域。
另外,阳极电极27与外延层12进行肖特基接触,从而由阳极电极27和外延层12构成肖特基势垒二极管区域。
这样,缺陷检测器件102具有PiN二极管区域和肖特基势垒二极管区域,从而能够在向缺陷检测器件102施加双极应力的基础上,对单极动作区域处的特性变动进行检测。
此外,如果将外延层12的n型杂质的浓度设为1×1018cm-3左右,则外延层12不会成为i(Intrinsic)层,能够将PiN二极管区域设为PN二极管区域。
<实施方式4>
就在实施方式1中所说明的基于缺陷检测器件102的筛选方法而言,虽然对下述内容进行了说明,即,通过利用由缺陷检测器件102检测的二极管的正向特性以及反向特性中的至少一者,从而对通过针对SiC-MOSFET 101的有源区域处的体二极管的电流应力测试无法检测的终端区域处的晶体缺陷进行检测,但也可以与如专利文献1公开那样的公知的筛选方法进行组合。
例如,通过持续流过电流密度120~400A/cm2的正向电流,从而向有源区域处的SiC-MOSFET 101的体二极管施加双极电流应力。基于其前后的通过缺陷检测器件102检测的二极管的正向特性以及反向特性中的至少一者的变动值,进行半导体装置的可靠性的判定以及分选。
例如,在向SiC-MOSFET 101的体二极管施加双极电流应力之前,得到作为图3的特性C1示出那样的二极管的正向特性,与此相对,在施加双极电流应力之后,在得到作为图3的特性C2示出那样的特性的情况下,能够判定为有由体二极管的晶体缺陷的扩展引起的对终端区域的晶体缺陷的影响。另外,如果由于晶体缺陷的扩展而对电流造成妨碍,则与同一阳极电压对应的阳极电流变小,因此有时也会确认到阳极-阴极间的电阻值的上升,在该情况下,能够以电阻值进行判定。
通过采用上述方法,从而能够进行将下述影响考虑在内的筛选,即,由于体二极管的晶体缺陷扩展到饱和状态而对终端区域的晶体缺陷造成的影响。
另外,在如实施方式2的半导体装置200那样由PiN二极管(或PN二极管)构成缺陷检测器件102的情况下以及如实施方式3的半导体装置300那样缺陷检测器件102具有PiN二极管区域(或PN二极管区域)和肖特基势垒二极管区域的情况下,也可以对缺陷检测器件102本身施加上述的双极电流应力。基于其前后的通过缺陷检测器件102检测的二极管的正向特性以及反向特性中的至少一者的变动值,进行半导体装置的可靠性的判定以及分选。
例如,在向缺陷检测器件102施加双极电流应力之前,得到作为图3的特性C1示出那样的二极管的正向特性,与此相对,在施加双极电流应力之后,在得到作为图3的特性C2示出那样的特性的情况下,能够判定为终端区域的晶体缺陷发生了扩展。另外,如果由于晶体缺陷的扩展而对电流造成妨碍,则与同一阳极电压对应的阳极电流变小,因此有时也会确认到阳极-阴极间的电阻值的上升,在该情况下,能够以电阻值进行判定。
通过采用上述方法,从而能够对由于终端区域的晶体缺陷扩展而造成的特性变动进行评价,能够进一步提高半导体装置的可靠性的判定的精度。
<其他应用例>
在如上述说明的实施方式1~4中,示出了将本发明应用于SiC半导体装置的结构,但本发明的应用并不限定于此,也可以应用于使用了氮化镓(GaN)等其他宽带隙半导体的宽带隙半导体装置。
另外,本发明也能够应用于通过机械方法、化学方法或其他方法将SiC基板11去除,仅由外延层12构成的自支撑基板(free-standing substrate)。
此外,本发明能够在该发明的范围内对各实施方式自由地进行组合,或对各实施方式适当地进行变形、省略。
Claims (10)
1.一种半导体装置,其具有:
有源区域,其设置于第1导电型的半导体层,在该有源区域形成有在所述半导体层的厚度方向流过主电流的MOS晶体管;以及
终端区域,其设置于所述有源区域的周围,
所述终端区域具有沿所述有源区域而设置的缺陷检测器件,
所述缺陷检测器件由具有第1主电极和第2主电极的二极管构成,
该第1主电极是在所述半导体层的第1主面之上沿所述有源区域而设置的,
该第2主电极设置于所述半导体层的第2主面侧,
所述二极管是所述第1主电极与所述半导体层进行肖特基接触的肖特基势垒二极管。
2.一种半导体装置,其具有:
有源区域,其设置于第1导电型的半导体层,在该有源区域形成有在所述半导体层的厚度方向流过主电流的MOS晶体管;以及
终端区域,其设置于所述有源区域的周围,
所述终端区域具有沿所述有源区域而设置的缺陷检测器件,
所述缺陷检测器件由具有第1主电极和第2主电极的二极管构成,
该第1主电极是在所述半导体层的第1主面之上沿所述有源区域而设置的,
该第2主电极设置于所述半导体层的第2主面侧,
所述二极管具有:
PN二极管区域或PiN二极管区域,其具有以与所述第1主电极接触的方式在所述半导体层的上层部选择性地设置的第2导电型的杂质区域;以及
所述第1主电极与所述半导体层进行肖特基接触的肖特基势垒二极管区域。
3.根据权利要求1或2所述的半导体装置,其中,
所述二极管具有与所述第1主电极的一部分连接的电极焊盘,
所述电极焊盘与所述有源区域电分离。
4.根据权利要求3所述的半导体装置,其中,
所述有源区域在俯视观察时呈角部成为曲率部的四边形状,
所述第1主电极在与所述有源区域的曲率部对应的部分具有曲率部,
所述电极焊盘配置于所述有源区域的曲率部与所述第1主电极的曲率部之间。
5.根据权利要求3所述的半导体装置,其中,
还具有绝缘膜,该绝缘膜是以至少将所述终端区域覆盖的方式设置的,
所述绝缘膜具有设置于所述电极焊盘的至少一部分上部,到达至所述电极焊盘的开口部。
6.根据权利要求3所述的半导体装置,其中,
所述电极焊盘配置为从所述第1主电极的外缘到达至所述半导体层的外缘。
7.根据权利要求1或2所述的半导体装置,其中,
所述二极管构成为,所述第1主电极的底面侧***至在所述半导体层的所述第1主面设置的凹槽部。
8.根据权利要求1或2所述的半导体装置,其中,
所述半导体层是碳化硅半导体层。
9.一种半导体装置的制造方法,其具有下述工序:
将多个半导体装置形成于半导体晶片之上的工序,该半导体装置具有有源区域以及终端区域,该有源区域设置于第1导电型的半导体层,在该有源区域形成有在所述半导体层的厚度方向流过主电流的MOS晶体管,该终端区域设置于所述有源区域的周围,所述终端区域具有沿所述有源区域而设置的缺陷检测器件,所述缺陷检测器件由具有第1主电极和第2主电极的二极管构成,该第1主电极是在所述半导体层的第1主面之上沿所述有源区域而设置的,该第2主电极设置于所述半导体层的第2主面侧;
对所述缺陷检测器件的正向特性以及反向特性中的至少一者进行测定的工序;以及
基于所述正向特性以及所述反向特性中的至少一者,进行所述半导体装置的可靠性的判定以及分选的工序,
所述二极管具有与所述第1主电极的一部分连接的电极焊盘,
所述电极焊盘是以下述方式配置的,即,与所述有源区域电分离,从所述第1主电极的外缘越过所述半导体晶片的切割线而延伸至所述半导体装置的排列间隙,
对所述缺陷检测器件的正向特性以及反向特性中的至少一者进行测定的工序包含在晶片状态下对所述电极焊盘与所述第2主电极之间的电流进行测定的工序。
10.根据权利要求9所述的半导体装置的制造方法,其中,
所述半导体层是碳化硅半导体层。
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