JP7346902B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7346902B2 JP7346902B2 JP2019091726A JP2019091726A JP7346902B2 JP 7346902 B2 JP7346902 B2 JP 7346902B2 JP 2019091726 A JP2019091726 A JP 2019091726A JP 2019091726 A JP2019091726 A JP 2019091726A JP 7346902 B2 JP7346902 B2 JP 7346902B2
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Description
実施の形態1にかかる半導体装置は、シリコン(Si)よりもバンドギャップが広い半導体(ワイドバンドギャップ半導体)を半導体材料として用いて構成される。実施の形態1にかかる半導体装置の構造について、ワイドバンドギャップ半導体として例えば炭化珪素(SiC)を用いた場合を例に説明する。図1は、実施の形態1にかかる半導体装置を半導体基板のおもて面側から見たレイアウトを示す平面図である。図1には、センス有効領域(第2有効領域)12aのp型ベース領域(第2の第2導電型領域)34bと、メイン無効領域1bのp-型低ドーズ領域(第3の第2導電型領域)63と、を異なるハッチングで示す(図12~17においても同様)。
次に、実施の形態2にかかる半導体装置について説明する。図12は、実施の形態2にかかる半導体装置を半導体基板のおもて面側から見たレイアウトを示す平面図である。実施の形態2にかかる半導体装置91が実施の形態1にかかる半導体装置20(図1~4参照)と異なる点は、同一の半導体基板10の活性領域1に、メイン半導体素子11および電流センス部12のみを備える点である。
次に、実施の形態3にかかる半導体装置について説明する。図13は、実施の形態3にかかる半導体装置を半導体基板のおもて面側から見たレイアウトを示す平面図である。実施の形態3にかかる半導体装置92が実施の形態2にかかる半導体装置91(図12参照)と異なる点は、OCパッド22の直下にのみ、p型低ドーズ領域63’が設けられている点である。ゲートパッド21bの直下には、p型低ドーズ領域63’と離れて、p型ベース領域34b’が設けられている。
次に、実施の形態4にかかる半導体装置について説明する。図14は、実施の形態4にかかる半導体装置を半導体基板のおもて面側から見たレイアウトを示す平面図である。実施の形態4にかかる半導体装置20’が実施の形態1にかかる半導体装置20(図1~4参照)と異なる点は、メイン無効領域1b付近のn-型ドリフト領域32中で発生した正孔電流を接地電位の接地点GNDへ引き抜く金属電極(以下、引き抜き電極とする)18を備える点である。
次に、実施の形態5にかかる半導体装置について説明する。図17は、実施の形態5にかかる半導体装置を半導体基板のおもて面側から見たレイアウトを示す平面図である。図18は、図17の活性領域の断面構造を示す断面図である。図18には、メイン有効領域1aおよび電流センス部12の断面構造(切断線X1-X2-X3’-X4’-X5における断面構造)を示す。図18の切断線X1-X2および切断線X4’-X5の断面構造は図2の切断線X1-X2および切断線X4-X5の断面構造と同様である。
次に、実施の形態6にかかる半導体装置について説明する。図19は、実施の形態6にかかる半導体装置の構成を示す断面図である。実施の形態6にかかる半導体装置を半導体基板のおもて面側から見たレイアウトは、実施の形態1(図1)と同様である。図19では、温度センス部13のアノードパッド23aおよびカソードパッド23b直下における断面構造を図示省略するが、アノードパッド23aおよびカソードパッド23b直下の断面構造はゲートパッド21b直下の断面構造と同じである。センス有効領域12aを図示省略するが、電流センス部12の断面構造は、実施の形態1(図2参照)と同様である。
次に、実施の形態1にかかる半導体装置20の逆回復耐量について検討した。図20は、実施例の逆回復耐量による遮断電流の電流量を示す特性図である。上述した実施の形態1にかかる半導体装置20(以下、実施例とする:図1参照)と、従来の半導体装置120(以下、従来例とする:図21参照)と、で活性領域の寄生ダイオードのターンオフ時に、メイン有効領域のp型ベース領域を通ってソースパッドへ引き抜かれる正孔電流(遮断電流)の電流量を比較した結果を図20に示す。
1a,1a’ メイン有効領域
1b メイン無効領域
2 エッジ終端領域
10 半導体基板
11 メイン半導体素子
12 電流センス部
12a センス有効領域
12b センス無効領域
13 温度センス部
14 ゲートパッド部
15 抵抗体
16,16a,16b メイン半導体素子の寄生ダイオード
17 電流センス部の寄生ダイオード
18 引き抜き電極
19,36a,36b,36c p++型コンタクト領域
20,20’,91,91’,92,92’,93,94 半導体装置
21a ソースパッド(電極パッド)
21b ゲートパッド(電極パッド)
22 OCパッド(電極パッド)
23a アノードパッド(電極パッド)
23b カソードパッド(電極パッド)
31 n+型出発基板
32 n-型ドリフト領域
32b n-型領域
33a,33b n型電流拡散領域
34a,34b,34b’ p型ベース領域
34a’ p型領域
35a,35b n+型ソース領域
37a,37b トレンチ
38a,38b ゲート絶縁膜
39a,39b ゲート電極
40 層間絶縁膜
40a,40b コンタクトホール
41a,41b NiSi膜
42a~42c 第1TiN膜
43a~43c 第1Ti膜
44a~44c 第2TiN膜
45a~45c 第2Ti膜
46a~46c バリアメタル
47a~47c めっき膜
48a~48c 端子ピン
49a~49c 第1保護膜
50a~50c 第2保護膜
51 ドレイン電極
61a,61b,62a,62b,81,83 p+型領域
63,63’ p型低ドーズ領域
64,64’ p-型領域
65 第1p型低ドーズ領域
66 第2p型低ドーズ領域
70 フィールド絶縁膜
71 n-型炭化珪素層
71a n-型炭化珪素層の厚さを増した部分
72 p型炭化珪素層
82,84 n型領域
GND 接地点
X 半導体チップのおもて面に平行な方向(第1方向)
Y 半導体チップのおもて面に平行でかつ第1方向と直交する方向(第2方向)
Z 深さ方向
d1 p+型領域の深さ
d2 p+型領域間の距離
d3 n型領域の深さ
t11 n-型炭化珪素層の、n+型出発基板上に最初に積層する厚さ
t12 n-型炭化珪素層の、厚さを増した部分の厚さ
t13 p型炭化珪素層の厚さ
w1 p型低ドーズ領域とセンス有効領域のp型ベース領域との距離
w1’ 第1p型低ドーズ領域とセンス有効領域のp型ベース領域との距離
Claims (11)
- シリコンよりもバンドギャップの広い半導体からなる半導体基板と、
前記半導体基板の内部に設けられた第1の第1導電型領域と、
前記半導体基板の第1主面と前記第1の第1導電型領域との間に設けられた第1の第2導電型領域と、
前記第1の第1導電型領域をドリフト領域とし、前記第1の第2導電型領域をベース領域とする第1絶縁ゲート型電界効果トランジスタと、
前記半導体基板の第1主面上に設けられ、前記第1の第2導電型領域に電気的に接続された、前記第1絶縁ゲート型電界効果トランジスタの第1ソースパッドと、
前記半導体基板の第1主面と前記第1の第1導電型領域との間であって、前記第1の第2導電型領域とは異なる領域に設けられた第2の第2導電型領域と、
前記第1の第1導電型領域をドリフト領域とし、前記第2の第2導電型領域をベース領域とし、前記第1絶縁ゲート型電界効果トランジスタと同じセル構造の複数のセルを、前記第1絶縁ゲート型電界効果トランジスタよりも少ない個数で有する第2絶縁ゲート型電界効果トランジスタと、
前記半導体基板の第1主面上に前記第1ソースパッドと離れて設けられ、前記第2の第2導電型領域に電気的に接続された、前記第2絶縁ゲート型電界効果トランジスタの第2ソースパッドと、
前記第1絶縁ゲート型電界効果トランジスタのセルが配置された第1有効領域と、前記第2絶縁ゲート型電界効果トランジスタのセルが配置された第2有効領域と、を除く無効領域において、前記半導体基板の第1主面と前記第1の第1導電型領域との間に、前記第2有効領域と離れて設けられ、前記第2有効領域の周囲を囲み、かつ前記第1の第2導電型領域に電気的に接続された第3の第2導電型領域と、
前記半導体基板の第2主面に電気的に接続された、前記第1絶縁ゲート型電界効果トランジスタおよび前記第2絶縁ゲート型電界効果トランジスタに共通のドレイン電極と、
を備え、
前記第3の第2導電型領域の総ドーズ量は、前記半導体基板の第1主面と前記第1の第1導電型領域との間に設けられた、前記第1絶縁ゲート型電界効果トランジスタの単位セルを構成する第4の第2導電型領域の総ドーズ量よりも低く、
前記半導体基板の第1主面から前記第1の第2導電型領域を貫通して前記第1の第1導電型領域に達するトレンチと、
隣り合う前記トレンチの間において、前記第1の第2導電型領域と前記第1の第1導電型領域との間に、前記第1の第2導電型領域および前記第1の第1導電型領域に接して設けられた、前記第1の第2導電型領域よりも不純物濃度の高い第2導電型高濃度領域と、
をさらに備え、
前記第4の第2導電型領域は、前記第1の第2導電型領域および前記第2導電型高濃度領域で構成されていることを特徴とする半導体装置。 - 前記第3の第2導電型領域の総ドーズ量は、前記第4の第2導電型領域の総ドーズ量の15%以下であることを特徴とする請求項1に記載の半導体装置。
- 前記第3の第2導電型領域の総ドーズ量は、前記第4の第2導電型領域の総ドーズ量の5%以下であることを特徴とする請求項2に記載の半導体装置。
- 前記第3の第2導電型領域は、
前記第2有効領域の周囲を囲む第5の第2導電型領域と、
前記第5の第2導電型領域に接し、前記第5の第2導電型領域の周囲を囲む第6の第2導電型領域と、を有し、
前記第5の第2導電型領域の総ドーズ量は、前記第6の第2導電型領域の総ドーズ量よりも低いことを特徴とする請求項1に記載の半導体装置。 - 前記第5の第2導電型領域の総ドーズ量は、前記第4の第2導電型領域の総ドーズ量よりも低いことを特徴とする請求項4に記載の半導体装置。
- 前記第5の第2導電型領域の総ドーズ量は、前記第4の第2導電型領域の総ドーズ量の15%以下であることを特徴とする請求項5に記載の半導体装置。
- 前記第5の第2導電型領域の総ドーズ量は、前記第4の第2導電型領域の総ドーズ量の5%以下であることを特徴とする請求項6に記載の半導体装置。
- 前記第2の第2導電型領域と前記第3の第2導電型領域との間に設けられ、前記第2の第2導電型領域の周囲を囲む第2の第1導電型領域をさらに備えることを特徴とする請求項1~7のいずれか一つに記載の半導体装置。
- 前記無効領域において前記半導体基板の第1主面上に、前記第1ソースパッドおよび前記第2ソースパッドと離れて設けられた1つ以上の電極パッドをさらに備え、
前記第3の第2導電型領域は、前記無効領域の、前記第2の第1導電型領域を除く領域の全域に延在して、前記電極パッドの直下に位置することを特徴とする請求項8に記載の半導体装置。 - 前記第2有効領域は、前記第2ソースパッドの直下の一部の領域であり、
前記第3の第2導電型領域は、前記第2ソースパッドの直下の、前記第2有効領域を除く領域に設けられていることを特徴とする請求項1~9のいずれか一つに記載の半導体装置。 - 前記第2絶縁ゲート型電界効果トランジスタは、前記第1絶縁ゲート型電界効果トランジスタに流れる過電流を検出することを特徴とする請求項1~10のいずれか一つに記載の半導体装置。
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