CN108398978A - A kind of voltage reference circuit with anti-process corner variation and Width funtion tracking range - Google Patents
A kind of voltage reference circuit with anti-process corner variation and Width funtion tracking range Download PDFInfo
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- CN108398978A CN108398978A CN201810175390.4A CN201810175390A CN108398978A CN 108398978 A CN108398978 A CN 108398978A CN 201810175390 A CN201810175390 A CN 201810175390A CN 108398978 A CN108398978 A CN 108398978A
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- voltage
- generating circuit
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- voltage generating
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Control Of Electrical Variables (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a kind of reference voltage circuits with anti-process corner variation and Width funtion tracking range, including bias-voltage generating circuit, Unity-gain buffer circuit, reference voltage generating circuit.Bias-voltage generating circuit can generate the voltage not changed with process corner, after Unity-gain buffer circuit, on the basis of voltage generation circuit stable bias voltage is provided so that reference voltage generating circuit exports the reference voltage of anti-process corner variation；Output voltage can linearly follow the variation of supply voltage in wide-voltage range；Output voltage all has low-down temperature coefficient under different operating voltages.It is disclosed by the invention have many advantages, such as the reference voltage circuit of the variation of anti-process corner and Width funtion tracking range have simple in structure, unrelated with process corner, voltage track accurately, temperature coefficient is low, non-resistance, without bipolar transistor.
Description
Technical field
The present invention relates to analog power fields more particularly to a kind of with the variation of anti-process corner and Width funtion tracking range
Reference voltage circuit.
Background technology
In general, coefficient very little of the reference voltage with mains voltage variations, but not necessarily closed in certain certain applications
It is suitable, it such as tracks and uses as the voltage inside power management chip.Power management chip is generally all integrated with battery real voltage
Tracer technique, the true electricity in tracking battery core inside, prevents voltage deviation caused by charge and discharge.Existing power supply managing chip usually exists
When voltage is less than 3V or so, corona discharge is closed, and charging is proceeded by.Mean that voltage tracking can generally track 3V or so.
With the progress of technique, portable electronic device is just strided forward towards low-voltage and low-power dissipation direction, and power management chip is also such.Cause
This, exploitation has great importance suitable for the high-performance voltage tracking reference voltage source circuit of supply voltage.
Invention content
According to above-mentioned trend, the present invention provides a kind of voltage bases with anti-process corner variation and Width funtion tracking range
Quasi- circuit can well track mains voltage variations, and the characteristic changed with anti-process corner when down to 0.6V,
To reduce the deviation that integrated circuit is brought in the fabrication process.
In order to achieve the above object, the embodiment provides one kind having the variation of anti-process corner and Width funtion tracking
The voltage reference circuit of range, the circuit include bias-voltage generating circuit, Unity-gain buffer circuit, reference voltage generation electricity
Road.
Wherein, bias-voltage generating circuit output port is connected with amplifier positive input terminal, amplifier output end port and benchmark
Voltage generation circuit input port is connected, and the output port of reference voltage generating circuit is described a kind of with the variation of anti-process corner
With the output port of the voltage reference circuit of Width funtion tracking range.
Wherein, bias-voltage generating circuit includes：First PMOS tube, the second PMOS tube, third PMOS tube, the 4th PMOS
Pipe.
Wherein, the first PMOS source end is connected with power supply terminal, and substrate terminal is connected with source, and grid end is connected with drain terminal, leakage
End is connected with the second PMOS source end with substrate terminal；Second PMOS tube substrate terminal is connected with source, and grid end is connected with drain terminal, drain terminal
It is connected with third PMOS source end with substrate terminal；Third PMOS tube substrate terminal is connected with source, and grid end is connected with drain terminal, drain terminal and
4th PMOS source end is connected with substrate terminal；4th PMOS tube substrate terminal is connected with source, and grid end is connected with drain terminal, drain terminal and connects
Ground terminal is connected.
Wherein, Unity-gain buffer circuit includes an operational amplifier, positive input terminal and bias-voltage generating circuit
Third PMOS tube grid end is connected, and negative input end is connected with its output end, output end and the first NMOS tube of reference voltage generating circuit
Grid end is connected.
Wherein, reference voltage generating circuit includes the first NMOS tube, the second NMOS tube, wherein the first draining end of NMOS tube with
Supply voltage is connected, and substrate terminal is connected to the ground, source and second draining end of NMOS tube, the voltage reference circuit output end phase
Even；Second draining end of NMOS tube is connected with its grid end, and substrate terminal and source are connected to the ground simultaneously.
The said program of the present invention includes at least following advantageous effect：
In an embodiment of the present invention, due to bias-voltage generating circuit can generate one have anti-process corner variation and
The voltage of mains voltage variations is tracked, therefore, last reference output voltage will have anti-process corner variation characteristic and voltage to chase after
Track characteristic.
Description of the drawings
Fig. 1 is the voltage reference circuit with anti-process corner variation and Width funtion tracking range in the specific embodiment of the invention
Structural schematic diagram.
Fig. 2 is the structural schematic diagram of bias-voltage generating circuit in the specific embodiment of the invention.
Fig. 3 is the structural schematic diagram of Unity-gain buffer circuit in the specific embodiment of the invention.
Fig. 4 is the structural schematic diagram of reference voltage generating circuit in the specific embodiment of the invention.
Fig. 5 is PMOS tube and NMOS tube schematic diagram
Reference sign：
1 bias-voltage generating circuit
2 Unity-gain buffer circuits
3 reference voltage generating circuits
4 power supply terminals
5 reference voltage output end mouths
6 bias-voltage generating circuit output ports
7 Unity-gain buffer circuit input end mouths
8 Unity-gain buffer circuit output ports
9 reference voltage generating circuit input ports
10 bias-voltage generating circuit first ports
11 bias-voltage generating circuit second ports
12 reference voltage generating circuit first ports
13 reference voltage generating circuit second ports
14 ground terminals
The first PMOS tube of P1
The second PMOS tube of P2
P3 third PMOS tube
The 4th PMOS tube of P4
The first NMOS tubes of N1
The second NMOS tubes of N2
Vref circuit outputs port
Specific implementation mode
The exemplary embodiment of the disclosure is more fully described below with reference to accompanying drawings.Although showing the disclosure in attached drawing
Exemplary embodiment, however, it is to be appreciated that may be realized in various forms the disclosure without by embodiments set forth here institute
Limitation.
As shown in Figures 1 to 5, a kind of voltage reference circuit with anti-process corner variation and Width funtion tracking range,
Including bias-voltage generating circuit 1, Unity-gain buffer circuit 2, reference voltage generating circuit 3.
Wherein, 1 first port 10 of bias-voltage generating circuit is connect with power supply terminal 4, bias-voltage generating circuit 1 second
Port 11 is connect with ground terminal 14,1 output port 6 of bias-voltage generating circuit and 2 input port 7 of Unity-gain buffer circuit
Connection, 2 output port 8 of Unity-gain buffer circuit are connect with 3 input port 9 of reference voltage generating circuit, and reference voltage generates
3 first port 12 of circuit is connect with power supply terminal 4, and 3 second port 13 of reference voltage generating circuit is connect with ground terminal 4, base
3 output port 5 of quasi- voltage generation circuit is connect with circuit output port Vref.
Wherein, in a specific embodiment of the present invention, bias-voltage generating circuit 1 is mainly for generation of a biased electrical
Pressure, the voltage change or vary less little with the deviation of process corner in CMOS technology, meanwhile, which has certain
Temperature coefficient.The bias voltage size of generation linearly changes with supply voltage, therefore can reach the characteristic of voltage tracking, when changing
Become four PMOS tube in bias-voltage generating circuit 1, P1, P2, when the size of P3, P4, the offset voltage temperature characteristic of generation
Also it can change correspondingly, temperature coefficient is adjusted with this, can be compensated with circuit below, to obtain a temperature coefficient very little
Reference output voltage.
Wherein, in a specific embodiment of the present invention, bias-voltage generating circuit 1 is using four PMOS tube, and
The substrate terminal of POMS pipes is connected with its source in specific embodiments of the present invention.It can be to avoid the influence of bulk effect with this.
Wherein, in a specific embodiment of the present invention, Unity-gain buffer circuit 2 is used for extracting bias-voltage generating circuit
1 output bias voltage makes it avoid the influence of load effect, meanwhile, Unity-gain buffer circuit output port 8 can obtain again
One with the almost consistent voltage of bias-voltage generating circuit output port 6.
Wherein, in a specific embodiment of the present invention, reference voltage generating circuit 3 generates benchmark using two NMOS tubes
Output voltage.The threshold voltage V of MOS transistorTHAs temperature increases and linear decrease, with the aforementioned biasing with positive temperature coefficient
Voltage compensates, to generate a temperature independent reference output voltage.
The above is the preferred embodiment of the present invention, it is noted that for those skilled in the art
For, without departing from the principles of the present invention, several improvements and modifications can also be made, these improvements and modifications
It should be regarded as protection scope of the present invention.
Claims (1)
1. a kind of voltage reference circuit with the variation of anti-process corner and Width funtion tracking range includes：Bias voltage generates electricity
Road, unit buffer circuit, reference voltage generating circuit；It is characterized in that, bias-voltage generating circuit includes：First PMOS tube,
Second PMOS tube, third PMOS tube, the 4th PMOS tube, reference voltage generating circuit include the first NMOS tube, the second NMOS tube,
Wherein, four PMOS tube in the bias-voltage generating circuit are required to independent N traps biasing；First PMOS source end with
Power supply terminal is connected, and substrate terminal is connected with source, and grid end is connected with drain terminal, drain terminal and the second PMOS source end and substrate terminal phase
Even；The second PMOS tube substrate terminal is connected with source, and grid end is connected with drain terminal, drain terminal and third PMOS source end and substrate terminal
It is connected；The third PMOS tube substrate terminal is connected with source, and grid end is connected with drain terminal, drain terminal and the 4th PMOS source end and substrate
End is connected；The 4th PMOS tube substrate terminal is connected with source, and grid end is connected with drain terminal, and drain terminal is connected with ground terminal；It is described
Unit buffer circuit includes an operational amplifier, positive input terminal and the bias-voltage generating circuit third PMOS tube grid end
It is connected, negative input end is connected with its output end, and output end is connected with the reference voltage generating circuit the first NMOS tube grid end；Institute
It states the first draining end of NMOS tube with supply voltage to be connected, substrate terminal is connected to the ground, source and second draining end of NMOS tube, the electricity
Reference circuit output end is pressed to be connected；Second draining end of NMOS tube is connected with its grid end, and substrate terminal and source are connected to the ground simultaneously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810175390.4A CN108398978A (en) | 2018-03-02 | 2018-03-02 | A kind of voltage reference circuit with anti-process corner variation and Width funtion tracking range |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810175390.4A CN108398978A (en) | 2018-03-02 | 2018-03-02 | A kind of voltage reference circuit with anti-process corner variation and Width funtion tracking range |
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| Publication Number | Publication Date |
|---|---|
| CN108398978A true CN108398978A (en) | 2018-08-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810175390.4A Pending CN108398978A (en) | 2018-03-02 | 2018-03-02 | A kind of voltage reference circuit with anti-process corner variation and Width funtion tracking range |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021115147A1 (en) * | 2019-12-09 | 2021-06-17 | 北京集创北方科技股份有限公司 | Buffer apparatus, chip and electronic device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102483634A (en) * | 2009-06-26 | 2012-05-30 | 密执安州立大学董事会 | Reference voltage generator having a two transistor design |
| KR20140030552A (en) * | 2012-08-31 | 2014-03-12 | 에스케이하이닉스 주식회사 | Reference voltage generator |
| CN105824348A (en) * | 2016-05-12 | 2016-08-03 | 中国电子科技集团公司第二十四研究所 | Reference-voltage circuit |
| JP2017173878A (en) * | 2016-03-18 | 2017-09-28 | エスアイアイ・セミコンダクタ株式会社 | Reference voltage generating circuit |
| CN107608441A (en) * | 2017-10-26 | 2018-01-19 | 中国科学院上海高等研究院 | A kind of high-performance reference voltage source |
-
2018
- 2018-03-02 CN CN201810175390.4A patent/CN108398978A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102483634A (en) * | 2009-06-26 | 2012-05-30 | 密执安州立大学董事会 | Reference voltage generator having a two transistor design |
| KR20140030552A (en) * | 2012-08-31 | 2014-03-12 | 에스케이하이닉스 주식회사 | Reference voltage generator |
| JP2017173878A (en) * | 2016-03-18 | 2017-09-28 | エスアイアイ・セミコンダクタ株式会社 | Reference voltage generating circuit |
| CN105824348A (en) * | 2016-05-12 | 2016-08-03 | 中国电子科技集团公司第二十四研究所 | Reference-voltage circuit |
| CN107608441A (en) * | 2017-10-26 | 2018-01-19 | 中国科学院上海高等研究院 | A kind of high-performance reference voltage source |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021115147A1 (en) * | 2019-12-09 | 2021-06-17 | 北京集创北方科技股份有限公司 | Buffer apparatus, chip and electronic device |
| US11936375B2 (en) | 2019-12-09 | 2024-03-19 | Chipone Technology (Beijing) Co., Ltd. | Buffer apparatus, chip and electronic device |
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