CN203491978U - Output stage circuit, class AB amplifier and electronic device - Google Patents
Output stage circuit, class AB amplifier and electronic device Download PDFInfo
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- CN203491978U CN203491978U CN201320390535.5U CN201320390535U CN203491978U CN 203491978 U CN203491978 U CN 203491978U CN 201320390535 U CN201320390535 U CN 201320390535U CN 203491978 U CN203491978 U CN 203491978U
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Abstract
This utility model discloses an output stage circuit, comprising a power supply, a quiescent current control circuit and an output terminal circuit. The output stage circuit also comprises a quiescent current equalization circuit which is configured to reduce or increase the quiescent current passing through a quiescent current bias circuit in the quiescent current control circuit when the change in voltage of the power supply is detected in order to keep the quiescent current passing through the output terminal circuit constant. The utility model also discloses a class AM amplifier and an electronic device. In use, when the voltage of the power supply rises, the quiescent current passing through the output terminal circuit of the output stage circuit is kept constant, so that the power supply rejection ratio (PSRR) of the current of the output terminal circuit can be effectively increased and the power consumption can be reduced.
Description
Technical field
The utility model relates to the output-stage circuit technology of amplifier, relates in particular to a kind of output-stage circuit, class ab ammplifier and electronic equipment.
Background technology
Amplifier is can be the device of the voltage of input signal or power amplification.In amplifier, owing to having, efficiency is high, distortion is less, power discharging transistor power consumption is less and the advantage such as good heat dissipation for class ab ammplifier, becomes the type that current amplifier is conventional.
Fig. 1 is the output-stage circuit schematic diagram of traditional class ab ammplifier, as shown in Figure 1, after the voltage of power supply VCC raises, due to channel-length modulation, the circuit of output terminal of output-stage circuit of can making to flow through is that the quiescent current of MP1 and MN1 increases, and so, can reduce the Power Supply Rejection Ratio (PSRR of circuit of output terminal, and increase the power consumption of equipment Power Supply Rejection Ratio).
Utility model content
In order to solve the problems of the prior art, the utility model provides a kind of output-stage circuit, class ab ammplifier and electronic equipment.
For achieving the above object, the technical solution of the utility model is achieved in that
The utility model provides a kind of output-stage circuit, comprise: power supply, quiescent current control circuit and circuit of output terminal, described output-stage circuit also comprises: quiescent current equalizing circuit, when the voltage that is configured to detect described power supply changes, reduce or increase the quiescent current of the quiescent current bias circuit of flowing through in described quiescent current control circuit, it is constant that the quiescent current of the described circuit of output terminal that makes to flow through keeps.
The utility model also provides a kind of class ab ammplifier, comprising: output-stage circuit; Described output-stage circuit comprises power supply, quiescent current control circuit and circuit of output terminal, described output-stage circuit also comprises: quiescent current equalizing circuit, when the voltage that is configured to detect described power supply changes, reduce or increase the quiescent current of the quiescent current bias circuit of flowing through in described quiescent current control circuit, the described pleased quiescent current that goes out terminal circuit that makes to flow through keeps constant.
The utility model provides again a kind of electronic equipment, comprise: mainboard, shell and class ab ammplifier, described output-stage circuit comprises power supply, quiescent current control circuit and circuit of output terminal, described output-stage circuit also comprises: quiescent current equalizing circuit, when the voltage that is configured to detect described power supply changes, reduce the to flow through quiescent current of the quiescent current bias circuit in described quiescent current control circuit, the quiescent current of the described circuit of output terminal that makes to flow through keeps constant.
The output-stage circuit that the utility model provides, class ab ammplifier and electronic equipment, when the voltage that power supply detected changes, reduce or increase the quiescent current of the quiescent current bias circuit of flowing through in quiescent current control circuit, the quiescent current of circuit of output terminal of making to flow through keeps constant, when the voltage of power supply raises, the quiescent current of circuit of output terminal of output-stage circuit of making to flow through keeps constant, so, the PSRR of the circuit of output terminal that can effectively raise, reduces the power consumption of equipment.
In addition, in implementation of the present utility model, when the voltage of power supply raises, the increase of the drain-source voltage of the metal oxide semiconductor field effect tube of quiescent current equalizing circuit (MOS), cause the quiescent current of the quiescent biasing circuit of the quiescent current control circuit of flowing through to reduce, it is constant that thereby the quiescent current of the circuit of output terminal that makes to flow through keeps, so, when the voltage of power supply raises, the quiescent current of circuit of output terminal of output-stage circuit of effectively keeping flowing through is constant, thereby the PSRR of the electric current of the circuit of output terminal that can effectively raise, the power consumption of reduction equipment.
And implementation of the present utility model is simple, convenient, be easy to realize; In the various equipment with different power supply voltages.
Accompanying drawing explanation
Fig. 1 is the output-stage circuit structural representation of traditional class ab ammplifier;
Fig. 2 is for adopting the simulation result schematic diagram of existing technical scheme;
Fig. 3 is the utility model output-stage circuit structural representation;
Fig. 4 is output-stage circuit structural representation in the utility model practical application;
Fig. 5 is for adopting the simulation result schematic diagram of the technical solution of the utility model.
Embodiment
Conventionally, if the function realizing from each circuit is divided, the output-stage circuit of traditional class ab ammplifier comprises: quiescent current control circuit and circuit of output terminal, as shown in Figure 1; Wherein, quiescent current control circuit, is configured to the quiescent current size of control output end circuit, and realizes the working method of AB class.Here, described quiescent current control circuit comprises: MP2, MP3, MP4, MN2, MN3, MN4, two the first reference current source I
0and two the second reference current source I
1; Described circuit of output terminal comprises: MP1 and MN1; The working method of the described AB of realization class refers to: when static state, have the quiescent current of the less circuit of output terminal of flowing through; When dynamic, can export larger electric current to load, and there is higher delivery efficiency, less intermodulation distortion.
If divided from the type of the MOS that adopts, as shown in Figure 1, the output-stage circuit of traditional class ab ammplifier can comprise: by four the P-channel metal-oxide-semiconductor field effect transistor (PMOS) that comprise MP1, MP2, MP3 and MP4, a first reference current source I
0an and second reference current source I
1the first circuit forming; And by four the N NMOS N-channel MOS N field effect transistor (NMOS) that comprise MN1, MN2, MN3 and MN4, a first reference current source I
0an and second current source I
1the second circuit forming; Wherein, described the first circuit and described second circuit include quiescent current bias circuit; The quiescent current bias circuit of described the first circuit comprises MP2, MP3 and a first reference current source I
0, described second quiescent current bias circuit comprises: MN2, MN3 and a first reference current source I
0.Here, described quiescent current bias circuit, is configured to the quiescent current of circuit of output terminal to produce biasing, and the quiescent current of the circuit of output terminal that makes to flow through is self the mirror image of quiescent current of flowing through.
The first circuit take below as example, describe the principle of quiescent current size of circuit of output terminal of the output-stage circuit of traditional class ab ammplifier of flowing through.
As shown in Figure 1, in the output-stage circuit of traditional class ab ammplifier, exist: V
gsMP1+ V
gsMP4=V
gsMP2+ V
gsMP3; Wherein, V
gsMP1the gate source voltage that represents MP1, V
gsMP4the gate source voltage that represents MP4, V
gsMP2the gate source voltage that represents MP2, V
gsMP3the gate source voltage that represents MP3; And MP1 has identical grid with MP2 and refers to size (finger size), meanwhile, MP3 has identical finger size with MP4, so, the quiescent current of the MP1 that flows through be flow through MP2 quiescent current N doubly; Wherein, N represents that the grid of MP1 refer to the ratio of the finger number of number (finger number) and MP2, here, described MP1 has identical finger size with MP2 and refers to: MP1 and MP2 are grid and refer to (finger) structure, and MP1 is identical with the breadth length ratio of every finger of MP2.
The principle of described second circuit is identical with the principle of described the first circuit, repeats no more here.
Therefore, in the ideal case, the quiescent current of circuit of output terminal of flowing through be flow through quiescent current bias circuit quiescent current N doubly, after the value of N is determined, the quiescent current of circuit of output terminal of flowing through is the fixedly multiple of quiescent current of quiescent current bias circuit of flowing through, that is to say the quiescent current constant magnitude of the circuit of output terminal of flowing through.Here, the quiescent current bias circuit that described quiescent current bias circuit can be described the first circuit, can be also the quiescent current bias circuit of described second circuit.
But, as shown in Figure 2, due to channel-length modulation, the voltage that the Static Electro of circuit of output terminal of flowing through fails to be convened for lack of a quorum along with power supply VCC raises and increases, simulation result shows: the voltage at power supply VCC rises to the process of 5.5V from 2.5V, and the quiescent current of the circuit of output terminal of flowing through increases to 610uA from 418uA; The quiescent current of circuit of output terminal of flowing through while being 2.5V with the voltage of power supply VCC is compared, and the quiescent current of the circuit of output terminal of flowing through when the voltage of power supply VCC is 5.5V has increased 50%.
Channel-length modulation causes flowing through the quiescent current of circuit of output terminal along with the voltage of power supply VCC raises and the main manifestations that increases comprises:
The first, in the output-stage circuit of traditional class ab ammplifier, due to V
dsMP1+ V
dsMN1=V
vCCso,, when the voltage of power supply VCC changes, V
dsMP1+ V
dsMN1also can change.Wherein, V
dsMP1the drain-source voltage that represents MP1, V
dsMN1the drain-source voltage that represents MN1, V
vCCthe voltage that represents power supply VCC.Therefore, due to channel-length modulation, when the voltage of power supply VCC changes, because the drain-source voltage of circuit of output terminal produces mismatch with the variation of the voltage of power supply VCC, the quiescent current of circuit of output terminal of making to flow through is no longer a fixed value with the ratio of the quiescent current of the quiescent current bias circuit of flowing through, that is: the flow through quiescent current of circuit of output terminal is no longer constant, but can change.Here, the quiescent current bias circuit that described quiescent current bias circuit can be described the first circuit, can be also the quiescent current bias circuit of described second circuit.
The second, in the output-stage circuit of traditional class ab ammplifier, when the voltage of power supply VCC raises, due to channel-length modulation, make the first reference current source I
0drain-source voltage
become large, thereby cause the first reference current source I
0quiescent current increase, and then cause the quiescent current of the circuit of output terminal of flowing through obviously to increase.
Based on this, basic thought of the present utility model is: when the voltage that power supply detected changes, reduce or increase the quiescent current of the quiescent current bias circuit of flowing through in quiescent current control circuit, the quiescent current of the circuit of output terminal that makes to flow through keeps constant.
Below in conjunction with drawings and the specific embodiments, the utility model is described in further detail.
The output-stage circuit that the utility model provides, as shown in Figure 3, comprising: power supply 31, quiescent current equalizing circuit 32, quiescent current control circuit 33 and circuit of output terminal 34; Wherein,
Power supply 31, is configured to as quiescent current control circuit 33 and circuit of output terminal 34 power supplies;
Quiescent current equalizing circuit 32, when the voltage that is configured to detect power supply 31 changes, reduces or increases the quiescent current of the quiescent current bias circuit of flowing through in quiescent current control circuit 32, and the quiescent current of the circuit of output terminal 34 that makes to flow through keeps constant;
Quiescent current control circuit 33, is configured to the quiescent current of control output end circuit 34, and realizes the working method of AB class.
Here, the voltage that power supply 31 detected changes and refers to: the voltage that power supply 31 current times detected is not identical with upper one voltage constantly; Wherein, when practical application, the described voltage that power supply 31 current times detected and upper one voltage is constantly identical referring to not: in circuit design, outside allowing the scope changing, that is: outside error range, the voltage that power supply 31 current times detected is not identical with the voltage in a upper moment.
Accordingly, when practical application, described in make the to flow through quiescent current of circuit of output terminal 34 keep constant referring to: when practical application, in circuit design, the variation of the quiescent current of the circuit of output terminal 34 of flowing through is in allowing the scope changing.
When the described voltage that power supply 31 detected changes, reduce or increase the quiescent current of the quiescent current bias circuit of flowing through in quiescent current control circuit 32, it is constant that the quiescent current of the circuit of output terminal 34 that makes to flow through keeps, and is specially:
When the voltage that power supply 31 detected raises, the quiescent current of the quiescent current bias circuit in quiescent current control circuit 32 that reduces to flow through, the quiescent current of the circuit of output terminal 34 that makes to flow through keeps constant; While the lower voltage of power supply 31 being detected, increase the quiescent current of the quiescent current bias circuit in quiescent current control circuit 32 of flowing through, the quiescent current of the circuit of output terminal 34 that makes to flow through keeps constant.
Wherein, by the quiescent current of the quiescent current bias circuit in quiescent current control circuit 33 that reduces to flow through, can offset the quiescent current of the circuit of output terminal 34 of flowing through and the mismatch of the quiescent current of the described quiescent current bias circuit of flowing through that the variation by the drain-source voltage of circuit of output terminal 34 causes, thereby it is constant that the quiescent current of the circuit of output terminal 34 that makes to flow through keeps, the correlation of quiescent current and power supply 31 voltages of the circuit of output terminal 34 that reduced to flow through.
The working method of the described AB of realization class refers to: when static state, the quiescent current with the less circuit of output terminal of flowing through is less; When dynamic, can export larger electric current to load, and there is higher delivery efficiency, less intermodulation distortion.
Described quiescent current equalizing circuit 32 reduces or increases the quiescent current of the quiescent current bias circuit of flowing through in quiescent current control circuit 32, the quiescent current of circuit of output terminal 34 of making to flow through keeps constant, be specially: self the quiescent current of increasing or reduce to flow through, the quiescent current of the circuit of output terminal 34 that makes to flow through keeps constant.
Here, described quiescent current equalizing circuit 32 is by flow through self quiescent current of increase, with the quiescent current of the quiescent current bias circuit in quiescent current control circuit 32 that reduces to flow through; Described quiescent current equalizing circuit 32 is by reducing to flow through self quiescent current, to increase the quiescent current of the quiescent current bias circuit of flowing through in quiescent current control circuit 32.
By increasing or the quiescent current of the quiescent current equalizing circuit 32 that reduces to flow through, can reduce or increase the quiescent current of the quiescent current bias circuit of flowing through in quiescent current control circuit 33, thereby the quiescent current of the circuit of output terminal 34 of flowing through and the mismatch of the quiescent current of the described quiescent current bias circuit of flowing through that the variation by the drain-source voltage of circuit of output terminal 34 causes have been offset, and then the quiescent current of the circuit of output terminal 34 that makes to flow through keeps constant, that is: in circuit design, flow through the variation of quiescent current of circuit of output terminal 34 in the scope allow changing, reduced the correlation of circuit of output terminal quiescent current and supply voltage.
Described quiescent current control circuit 33, as shown in Figure 4, when practical application, may further include: the first quiescent current bias circuit 331, the second quiescent current bias circuit 332 and floating empty voltage offset electric circuit 333, the first quiescent current bias circuit 331 and the second quiescent current bias circuit 332 form quiescent current bias circuit; Wherein, the first quiescent current bias circuit 331 can comprise: a PMOS P1, the 2nd PMOS P2, the 6th NMOS N6, the first reference current source I
0, and the first reference voltage source V
0, the second quiescent current bias circuit 332 can comprise: a NMOS N1, the 2nd NMOS N2, the 6th PMOSP6, the second reference current source I
1and the second reference voltage source V
1, floating empty voltage offset electric circuit 333 can comprise: the 3rd PMOS P3, the 3rd NMOS N3, the 3rd reference current source I
2and the 4th reference current source I
3; Wherein, the first quiescent current bias circuit 331 and the second quiescent current bias circuit 332, be configured to the quiescent current of circuit of output terminal 34 to produce biasing, and the quiescent current of the circuit of output terminal that makes to flow through is self the mirror image of quiescent current of flowing through; Floating empty voltage offset electric circuit 333, is configured to the voltage of circuit of output terminal 34 to produce biasing.
Described quiescent current equalizing circuit 32, as shown in Figure 4, can comprise: the balanced electronic circuit 321 of the first quiescent current and the balanced electronic circuit 322 of the second quiescent current; The balanced electronic circuit 321 of described the first quiescent current comprises: the 5th PMOS P5, the balanced electronic circuit 322 of described two quiescent currents comprises: the 5th NMOS N5.Here, when practical application, in the circuit of design, described quiescent current equalizing circuit 32 can only comprise the balanced electronic circuit 321 of the first quiescent current, or, can only comprise the balanced electronic circuit 322 of the second quiescent current, or, the balanced electronic circuit 321 of the first quiescent current and the balanced electronic circuit 322 of the second quiescent current can be comprised simultaneously.
As shown in Figure 4, described circuit of output terminal 34 can comprise: the 4th PMOS P4 and the 4th NMOS N4.
The annexation of each parts of the output-stage circuit shown in Fig. 4 is:
In the first quiescent current bias circuit 331, the grid of the one PMOS P1 and drain electrode are all connected with the grid of the 5th PMOS P5 and the source electrode of the 2nd PMOS P2 in the balanced electronic circuit 321 of the first quiescent current, the source electrode of the one PMOS P1 connects power supply 31, the grid of the 2nd PMOS P2 is all connected with the grid of the 3rd PMOS P3 and the drain electrode of the 6th NMOS N6 in floating empty voltage offset electric circuit 333 with drain electrode, and the grid of the 6th NMOS N6 connects the first reference voltage source V
0one end, drain electrode and the first reference current source I of the source electrode of the 6th NMOS N6 and the 5th PMOS P5 in the balanced electronic circuit 321 of the first quiescent current
0one end connect, the first reference current source I
0the other end connect earth point VSS, the first reference voltage source V
0the other end connect earth point VSS;
In the second quiescent current bias circuit 332, the grid of the one NMOS N1 and drain electrode are all connected with the grid of the 5th NMOS N5 and the source electrode of the 2nd NMOS N2 in the balanced electronic circuit 322 of the second quiescent current, the source electrode of the one NMOS N1 connects earth point VSS, the grid of the 2nd NMOS N2 and drain electrode all with float the grid of the 3rd NMOS P3 in empty voltage offset electric circuit 333, the drain electrode of the 6th PMOS P6 is connected, the grid of the 6th PMOS P6 connects the second reference voltage source V
1one end, drain electrode and the second reference current source I of the source electrode of the 6th PMOS P6 and the 5th NMOS N5 in the balanced electronic circuit 322 of the second quiescent current
1one end connect, the second reference current source I
1the other end connect power supply 31, the second reference voltage source V
0the other end connect power supply 31;
In floating empty voltage offset electric circuit 333, the source electrode of the 3rd PMOS P3 and the 3rd reference current source I
2one end, the drain electrode of the 3rd NMOS N3 and the formed tie point of grid of the 4th PMOS P4 in circuit of output terminal 34 be connected, the drain electrode of the 3rd NMOS N3 and the 4th reference current source I
3one end, the source electrode of the 3rd NMOS N3 and the formed tie point of grid of the 4th NMOS N4 be connected, the 3rd reference current source I
2the other end connect power supply 31, the four reference current source I
3the other end connect earth point VSS;
In circuit of output terminal 34, the source electrode of the 4th PMOS P4 connects the drain electrode that connects the 4th NMOS N4 for the drain electrode of power supply 31, the four PMOSP4, and the source electrode of the 4th NMOS N4 connects earth point VSS;
In the balanced electronic circuit 321 of the first quiescent current, the source electrode of the 5th PMOS P5 connects power supply 31;
In the balanced electronic circuit 322 of the second quiescent current, the source electrode of the 5th NMOS N5 connects earth point VSS.
The operation principle of the balanced electronic circuit 321 of described the first quiescent current is:
When the voltage of power supply 31 raises, due to
and
substantially remain unchanged, so, V
dsP5increase, cause the quiescent current of the 5th PMOS P5 that flows through to increase; And,
and the 5th PMOS P5 and a PMOS P1 are current mirrors, therefore, when the voltage of power supply 31 raises, I
p5increase make I
p5?
in ratio increase, thereby the quiescent current of the PMOS P1 that makes to flow through reduces, the quiescent current of the first quiescent current bias circuit 331 of flowing through reduces with the rising of the voltage of power supply 31.
As shown in Figure 4, due to V
dsP1=V
gsP1, and V
dsP4but relevant with the voltage of power supply 31 power supplys, so, there is mismatch in make the to flow through quiescent current of a PMOS P1 and the quiescent current of the 4th PMOS P4 that flows through, therefore, by the 5th PMOS be used for offset shown in the impact of mismatch, thereby make the electric current of the 4th PMOS P4 keep constant.
Wherein, V
dsP5the drain-source voltage that represents the 5th PMOS P5,
represent the first reference voltage source V
0voltage, V
gsN6the gate source voltage that represents the 6th NMOS N6, V
vCCthe voltage that represents power supply 31, V
gsP1the gate source voltage that represents a PMOS P1, V
gsP5the gate source voltage that represents the 5th PMOS P5,
represent the first reference current source I
0electric current, I
p5represent the to flow through quiescent current of the 5th PMOS P5, I
p1represent the to flow through quiescent current of a PMOS P1, the quiescent current of the first quiescent current bias circuit 331 of flowing through, V
dsP1the drain-source voltage that represents a PMOS P1, V
dsP4the drain-source voltage that represents the 4th PMOS P4.
When the voltage drop of power supply 31, the operation principle of the balanced operation principle of electronic circuit 321 of described the first quiescent current during with the rising of the voltage of power supply 31 is contrary, repeats no more here.
The operation principle of the balanced electronic circuit 322 of the second quiescent current is identical with the operation principle of the balanced electronic circuit 321 of described the first quiescent current, repeats no more here.
Based on above-mentioned output-stage circuit, the utility model also provides a kind of quiescent current equalization methods, the method comprises: when the voltage that power supply detected changes, reduce or increase the quiescent current of the quiescent current bias circuit of flowing through in quiescent current control circuit, it is constant that the quiescent current of the circuit of output terminal that makes to flow through keeps.
Particularly, quiescent current equalizing circuit is set;
When the voltage that power supply detected changes, increase or the quiescent current of the described quiescent current equalizing circuit that reduces to flow through, the quiescent current of the circuit of output terminal that makes to flow through keeps constant.
Based on above-mentioned output-stage circuit, the utility model also provides a kind of class ab ammplifier, comprise: output-stage circuit, as shown in Figure 3, described output-stage circuit comprises: power supply 31, quiescent current equalizing circuit 32, quiescent current control circuit 33 and circuit of output terminal 34; Wherein,
Power supply 31, is configured to as quiescent current control circuit 33 and circuit of output terminal 34 power supplies;
Quiescent current equalizing circuit 32, when the voltage that is configured to detect power supply 31 changes, reduces or increases the quiescent current of the quiescent current bias circuit of flowing through in quiescent current control circuit 32, and the quiescent current of the circuit of output terminal 34 that makes to flow through keeps constant;
Quiescent current control circuit 33, is configured to the quiescent current of control output end circuit 34, and realizes the working method of AB class.
Here, the voltage that power supply 31 detected changes and refers to: the voltage that power supply 31 current times detected is not identical with upper one voltage constantly; Wherein, when practical application, the described voltage that power supply 31 current times detected and upper one voltage is constantly identical referring to not: in circuit design, outside allowing the scope changing, that is: outside error range, the voltage that power supply 31 current times detected is not identical with the voltage in a upper moment.
Accordingly, when practical application, described in make the to flow through quiescent current of circuit of output terminal 34 keep constant referring to: when practical application, in circuit design, the variation of the quiescent current of the circuit of output terminal 34 of flowing through is in allowing the scope changing.
When the described voltage that power supply 31 detected changes, reduce or increase the quiescent current of the quiescent current bias circuit of flowing through in quiescent current control circuit 32, it is constant that the quiescent current of the circuit of output terminal 34 that makes to flow through keeps, and is specially:
When the voltage that power supply 31 detected raises, the quiescent current of the quiescent current bias circuit in quiescent current control circuit 32 that reduces to flow through, the quiescent current of the circuit of output terminal 34 that makes to flow through keeps constant; While the lower voltage of power supply 31 being detected, increase the quiescent current of the quiescent current bias circuit in quiescent current control circuit 32 of flowing through, the quiescent current of the circuit of output terminal 34 that makes to flow through keeps constant.
Wherein, by the quiescent current of the quiescent current bias circuit in quiescent current control circuit 33 that reduces to flow through, can offset the quiescent current of the circuit of output terminal 34 of flowing through and the mismatch of the quiescent current of the described quiescent current bias circuit of flowing through that the variation by the drain-source voltage of circuit of output terminal 34 causes, thereby it is constant that the quiescent current of the circuit of output terminal 34 that makes to flow through keeps, the correlation of quiescent current and power supply 31 voltages of the circuit of output terminal 34 that reduced to flow through.
The working method of the described AB of realization class refers to: when static state, the quiescent current with the less circuit of output terminal of flowing through is less; When dynamic, can export larger electric current to load, and there is higher delivery efficiency, less intermodulation distortion.
Described quiescent current equalizing circuit 32 reduces or increases the quiescent current of the quiescent current bias circuit of flowing through in quiescent current control circuit 32, the quiescent current of circuit of output terminal 34 of making to flow through keeps constant, be specially: self the quiescent current of increasing or reduce to flow through, the quiescent current of the circuit of output terminal 34 that makes to flow through keeps constant.
Here, described quiescent current equalizing circuit 32 is by flow through self quiescent current of increase, with the quiescent current of the quiescent current bias circuit in quiescent current control circuit 32 that reduces to flow through; Described quiescent current equalizing circuit 32 is by reducing to flow through self quiescent current, to increase the quiescent current of the quiescent current bias circuit of flowing through in quiescent current control circuit 32.
By increasing or the quiescent current of the quiescent current equalizing circuit 32 that reduces to flow through, can reduce or increase the quiescent current of the quiescent current bias circuit of flowing through in quiescent current control circuit 33, thereby the quiescent current of the circuit of output terminal 34 of flowing through and the mismatch of the quiescent current of the described quiescent current bias circuit of flowing through that the variation by the drain-source voltage of circuit of output terminal 34 causes have been offset, and then the quiescent current of the circuit of output terminal 34 that makes to flow through keeps constant, that is: in circuit design, flow through the variation of quiescent current of circuit of output terminal 34 in the scope allow changing, reduced the correlation of circuit of output terminal quiescent current and supply voltage.
Described quiescent current control circuit 33, as shown in Figure 4, when practical application, may further include: the first quiescent current bias circuit 331, the second quiescent current bias circuit 332 and floating empty voltage offset electric circuit 333, the first quiescent current bias circuit 331 and the second quiescent current bias circuit 332 form quiescent current bias circuit; Wherein, the first quiescent current bias circuit 331 can comprise: a PMOS P1, the 2nd PMOS P2, the 6th NMOS N6, the first reference current source I
0, and the first reference voltage source V
0, the second quiescent current bias circuit 332 can comprise: a NMOS N1, the 2nd NMOS N2, the 6th PMOSP6, the second reference current source I
1and the second reference voltage source V
1, floating empty voltage offset electric circuit 333 can comprise: the 3rd PMOS P3, the 3rd NMOS N3, the 3rd reference current source I
2and the 4th reference current source I
3; Wherein, the first quiescent current bias circuit 331 and the second quiescent current bias circuit 332, be configured to the quiescent current of circuit of output terminal 34 to produce biasing, and the quiescent current of the circuit of output terminal that makes to flow through is self the mirror image of quiescent current of flowing through; Floating empty voltage offset electric circuit 333, is configured to the voltage of circuit of output terminal 34 to produce biasing.
Described quiescent current equalizing circuit 32, as shown in Figure 4, can comprise: the balanced electronic circuit 321 of the first quiescent current and the balanced electronic circuit 322 of the second quiescent current; The balanced electronic circuit 321 of described the first quiescent current comprises: the 5th PMOS P5, the balanced electronic circuit 322 of described two quiescent currents comprises: the 5th NMOS N5.Here, when practical application, in the circuit of design, described quiescent current equalizing circuit 32 can only comprise the balanced electronic circuit 321 of the first quiescent current, or, can only comprise the balanced electronic circuit 322 of the second quiescent current, or, the balanced electronic circuit 321 of the first quiescent current and the balanced electronic circuit 322 of the second quiescent current can be comprised simultaneously.
As shown in Figure 4, described circuit of output terminal 34 can comprise: the 4th PMOS P4 and the 4th NMOS N4.
The annexation of each parts of the output-stage circuit shown in Fig. 4 is:
In the first quiescent current bias circuit 331, the grid of the one PMOS P1 and drain electrode are all connected with the grid of the 5th PMOS P5 and the source electrode of the 2nd PMOS P2 in the balanced electronic circuit 321 of the first quiescent current, the source electrode of the one PMOS P1 connects power supply 31, the grid of the 2nd PMOS P2 and drain electrode all with float the grid of the 3rd PMOS P3 in empty voltage offset electric circuit 333, the drain electrode of the 6th NMOS N6 is connected, the grid of the 6th NMOS N6 connects the first reference voltage source V
0one end, drain electrode and the first reference current source I of the source electrode of the 6th NMOS N6 and the 5th PMOS P5 in the balanced electronic circuit 321 of the first quiescent current
0one end connect, the first reference current source I
0the other end connect earth point VSS, the first reference voltage source V
0the other end connect earth point VSS;
In the second quiescent current bias circuit 332, the grid of the one NMOS N1 and drain electrode are all connected with the grid of the 5th NMOS N5 and the source electrode of the 2nd NMOS N2 in the balanced electronic circuit 322 of the second quiescent current, the source electrode of the one NMOS N1 connects earth point VSS, the grid of the 2nd NMOS N2 and drain electrode all with float the grid of the 3rd NMOS P3 in empty voltage offset electric circuit 333, the drain electrode of the 6th PMOS P6 is connected, the grid of the 6th PMOS P6 connects the second reference voltage source V
1one end, drain electrode and the second reference current source I of the source electrode of the 6th PMOS P6 and the 5th NMOS N5 in the balanced electronic circuit 322 of the second quiescent current
1one end connect, the second reference current source I
1the other end connect power supply 31, the second reference voltage source V
0the other end connect power supply 31;
In floating empty voltage offset electric circuit 333, the source electrode of the 3rd PMOS P3 and the 3rd reference current source I
2one end, the drain electrode of the 3rd NMOS N3 and the formed tie point of grid of the 4th PMOS P4 in circuit of output terminal 34 be connected, the drain electrode of the 3rd NMOS N3 and the 4th reference current source I
3one end, the source electrode of the 3rd NMOS N3 and the formed tie point of grid of the 4th NMOS N4 be connected, the 3rd reference current source I
2the other end connect power supply 31, the four reference current source I
3the other end connect earth point VSS;
In circuit of output terminal 34, the source electrode of the 4th PMOS P4 connects the drain electrode that connects the 4th NMOS N4 for the drain electrode of power supply 31, the four PMOS P4, and the source electrode of the 4th NMOS N4 connects earth point VSS;
In the balanced electronic circuit 321 of the first quiescent current, the source electrode of the 5th PMOS P5 connects power supply 31;
In the balanced electronic circuit 322 of the second quiescent current, the source electrode of the 5th NMOS N5 connects earth point VSS.
When the voltage of power supply 31 raises, the operation principle of the balanced electronic circuit 321 of described the first quiescent current is:
When the voltage of power supply 31 raises, by
and
substantially remain unchanged, so, V
dsP5increase, cause the quiescent current of the 5th PMOS P5 that flows through to increase; And,
and the 5th PMOS P5 and a PMOS P1 are current mirrors, therefore, when the voltage of power supply 31 raises, I
p5increase make I
p5?
in ratio increase, thereby the quiescent current of the PMOS P1 that makes to flow through reduces, the quiescent current of the first quiescent current bias circuit 331 of flowing through reduces with the rising of the voltage of power supply 31.
As shown in Figure 4, due to V
dsP1=V
gsP1, and V
dsP4but relevant with the voltage of power supply 31 power supplys, so, there is mismatch in make the to flow through quiescent current of a PMOS P1 and the quiescent current of the 4th PMOS P4 that flows through, therefore, by the 5th PMOS be used for offset shown in the impact of mismatch, thereby make the electric current of the 4th PMOS P4 keep constant.
Wherein, V
gsP5the gate source voltage that represents the 5th PMOS P5,
represent the first reference voltage source V
0voltage, V
gsN6the gate source voltage that represents the 6th NMOS N6, V
vCCthe voltage that represents power supply 31, V
gsP1the gate source voltage that represents a PMOS P1, V
gsP5the gate source voltage that represents the 5th PMOS P5,
represent the first reference current source I
0electric current, I
p5represent the to flow through quiescent current of the 5th PMOS P5, I
p1represent the to flow through quiescent current of a PMOS P1, the quiescent current of the first quiescent current bias circuit 331 of flowing through, V
dsP1the drain-source voltage that represents a PMOS P1, V
dsP4the drain-source voltage that represents the 4th PMOS P4.
When the voltage drop of power supply 31, the operation principle of the balanced operation principle of electronic circuit 321 of described the first quiescent current during with the rising of the voltage of power supply 31 is contrary, repeats no more here.
The operation principle of the balanced electronic circuit 322 of the second quiescent current is identical with the operation principle of the balanced electronic circuit 321 of described the first quiescent current, repeats no more here.
Based on above-mentioned class ab ammplifier, the utility model also provides a kind of electronic equipment, this electronic equipment comprises: mainboard, shell and class ab ammplifier, described class ab ammplifier comprises output-stage circuit, as shown in Figure 3, described output-stage circuit comprises: power supply 31, quiescent current equalizing circuit 32, quiescent current control circuit 33 and circuit of output terminal 34; Wherein,
Power supply 31, is configured to as quiescent current control circuit 33 and circuit of output terminal 34 power supplies;
Quiescent current equalizing circuit 32, when the voltage that is configured to detect power supply 31 changes, reduces or increases the quiescent current of the quiescent current bias circuit of flowing through in quiescent current control circuit 32, and the quiescent current of the circuit of output terminal 34 that makes to flow through keeps constant;
Quiescent current control circuit 33, is configured to the quiescent current of control output end circuit 34, and realizes the working method of AB class.
Here, the voltage that power supply 31 detected changes and refers to: the voltage that power supply 31 current times detected is not identical with upper one voltage constantly; Wherein, when practical application, the described voltage that power supply 31 current times detected and upper one voltage is constantly identical referring to not: in circuit design, outside allowing the scope changing, that is: outside error range, the voltage that power supply 31 current times detected is not identical with the voltage in a upper moment.
Accordingly, when practical application, described in make the to flow through quiescent current of circuit of output terminal 34 keep constant referring to: when practical application, in circuit design, the variation of the quiescent current of the circuit of output terminal 34 of flowing through is in allowing the scope changing.
When the described voltage that power supply 31 detected changes, reduce or increase the quiescent current of the quiescent current bias circuit of flowing through in quiescent current control circuit 32, it is constant that the quiescent current of the circuit of output terminal 34 that makes to flow through keeps, and is specially:
When the voltage that power supply 31 detected raises, the quiescent current of the quiescent current bias circuit in quiescent current control circuit 32 that reduces to flow through, the quiescent current of the circuit of output terminal 34 that makes to flow through keeps constant; While the lower voltage of power supply 31 being detected, increase the quiescent current of the quiescent current bias circuit in quiescent current control circuit 32 of flowing through, the quiescent current of the circuit of output terminal 34 that makes to flow through keeps constant.
Wherein, by the quiescent current of the quiescent current bias circuit in quiescent current control circuit 33 that reduces to flow through, can offset the quiescent current of the circuit of output terminal 34 of flowing through and the mismatch of the quiescent current of the described quiescent current bias circuit of flowing through that the variation by the drain-source voltage of circuit of output terminal 34 causes, thereby it is constant that the quiescent current of the circuit of output terminal 34 that makes to flow through keeps, the correlation of quiescent current and power supply 31 voltages of the circuit of output terminal 34 that reduced to flow through.
The working method of the described AB of realization class refers to: when static state, the quiescent current with the less circuit of output terminal of flowing through is less; When dynamic, can export larger electric current to load, and there is higher delivery efficiency, less intermodulation distortion.
Described quiescent current equalizing circuit 32 reduces or increases the quiescent current of the quiescent current bias circuit of flowing through in quiescent current control circuit 32, the quiescent current of circuit of output terminal 34 of making to flow through keeps constant, be specially: self the quiescent current of increasing or reduce to flow through, the quiescent current of the circuit of output terminal 34 that makes to flow through keeps constant.
Here, described quiescent current equalizing circuit 32 is by flow through self quiescent current of increase, with the quiescent current of the quiescent current bias circuit in quiescent current control circuit 32 that reduces to flow through; Described quiescent current equalizing circuit 32 is by reducing to flow through self quiescent current, to increase the quiescent current of the quiescent current bias circuit of flowing through in quiescent current control circuit 32.
By increasing or the quiescent current of the quiescent current equalizing circuit 32 that reduces to flow through, can reduce or increase the quiescent current of the quiescent current bias circuit of flowing through in quiescent current control circuit 33, thereby the quiescent current of the circuit of output terminal 34 of flowing through and the mismatch of the quiescent current of the described quiescent current bias circuit of flowing through that the variation by the drain-source voltage of circuit of output terminal 34 causes have been offset, and then the quiescent current of the circuit of output terminal 34 that makes to flow through keeps constant, that is: in circuit design, flow through the variation of quiescent current of circuit of output terminal 34 in the scope allow changing, reduced the correlation of circuit of output terminal quiescent current and supply voltage.
Described quiescent current control circuit 33, as shown in Figure 4, when practical application, may further include: the first quiescent current bias circuit 331, the second quiescent current bias circuit 332 and floating empty voltage offset electric circuit 333, the first quiescent current bias circuit 331 and the second quiescent current bias circuit 332 form quiescent current bias circuit; Wherein, the first quiescent current bias circuit 331 can comprise: a PMOS P1, the 2nd PMOS P2, the 6th NMOS N6, the first reference current source I
0, and the first reference voltage source V
0, the second quiescent current bias circuit 332 can comprise: a NMOS N1, the 2nd NMOS N2, the 6th PMOS P6, the second reference current source I
1and the second reference voltage source V
1, floating empty voltage offset electric circuit 333 can comprise: the 3rd PMOS P3, the 3rd NMOS N3, the 3rd reference current source I
2and the 4th reference current source I
3; Wherein, the first quiescent current bias circuit 331 and the second quiescent current bias circuit 332, be configured to the quiescent current of circuit of output terminal 34 to produce biasing, and the quiescent current of the circuit of output terminal that makes to flow through is self the mirror image of quiescent current of flowing through; Floating empty voltage offset electric circuit 333, is configured to the voltage of circuit of output terminal 34 to produce biasing.
Described quiescent current equalizing circuit 32, as shown in Figure 4, can comprise: the balanced electronic circuit 321 of the first quiescent current and the balanced electronic circuit 322 of the second quiescent current; The balanced electronic circuit 321 of described the first quiescent current comprises: the 5th PMOS P5, the balanced electronic circuit 322 of described two quiescent currents comprises: the 5th NMOS N5.Here, when practical application, in the circuit of design, described quiescent current equalizing circuit 32 can only comprise the balanced electronic circuit 321 of the first quiescent current, or, can only comprise the balanced electronic circuit 322 of the second quiescent current, or, the balanced electronic circuit 321 of the first quiescent current and the balanced electronic circuit 322 of the second quiescent current can be comprised simultaneously.
As shown in Figure 4, described circuit of output terminal 34 can comprise: the 4th PMOS P4 and the 4th NMOS N4.
The annexation of each parts of the output-stage circuit shown in Fig. 4 is:
In the first quiescent current bias circuit 331, the grid of the one PMOS P1 and drain electrode are all connected with the grid of the 5th PMOS P5 and the source electrode of the 2nd PMOS P2 in the balanced electronic circuit 321 of the first quiescent current, the source electrode of the one PMOS P1 connects power supply 31, the grid of the 2nd PMOS P2 and drain electrode all with float the grid of the 3rd PMOS P3 in empty voltage offset electric circuit 333, the drain electrode of the 6th NMOS N6 is connected, the grid of the 6th NMOS N6 connects the first reference voltage source V
0one end, drain electrode and the first reference current source I of the source electrode of the 6th NMOS N6 and the 5th PMOS P5 in the balanced electronic circuit 321 of the first quiescent current
0one end connect, the first reference current source I
0the other end connect earth point VSS, the first reference voltage source V
0the other end connect earth point VSS;
In the second quiescent current bias circuit 332, the grid of the one NMOS N1 and drain electrode are all connected with the grid of the 5th NMOS N5 and the source electrode of the 2nd NMOS N2 in the balanced electronic circuit 322 of the second quiescent current, the source electrode of the one NMOS N1 connects earth point VSS, the grid of the 2nd NMOS N2 and drain electrode all with float the grid of the 3rd NMOS P3 in empty voltage offset electric circuit 333, the drain electrode of the 6th PMOS P6 is connected, the grid of the 6th PMOS P6 connects the second reference voltage source V
1one end, drain electrode and the second reference current source I of the source electrode of the 6th PMOS P6 and the 5th NMOS N5 in the balanced electronic circuit 322 of the second quiescent current
1one end connect, the second reference current source I
1the other end connect power supply 31, the second reference voltage source V
0the other end connect power supply 31;
In floating empty voltage offset electric circuit 333, the source electrode of the 3rd PMOS P3 and the 3rd reference current source I
2one end, the drain electrode of the 3rd NMOS N3 and the formed tie point of grid of the 4th PMOS P4 in circuit of output terminal 34 be connected, the drain electrode of the 3rd NMOS N3 and the 4th reference current source I
3one end, the source electrode of the 3rd NMOS N3 and the formed tie point of grid of the 4th NMOS N4 be connected, the 3rd reference current source I
2the other end connect power supply 31, the four reference current source I
3the other end connect earth point VSS;
In circuit of output terminal 34, the source electrode of the 4th PMOS P4 connects the drain electrode that connects the 4th NMOS N4 for the drain electrode of power supply 31, the four PMOS P4, and the source electrode of the 4th NMOS N4 connects earth point VSS;
In the balanced electronic circuit 321 of the first quiescent current, the source electrode of the 5th PMOS P5 connects power supply 31;
In the balanced electronic circuit 322 of the second quiescent current, the source electrode of the 5th NMOS N5 connects earth point VSS.
When the voltage of power supply 31 raises, the operation principle of the balanced electronic circuit 321 of described the first quiescent current is:
When the voltage of power supply 31 raises, due to
and
substantially remain unchanged, so, V
dsP5increase, cause the quiescent current of the 5th PMOS P5 that flows through to increase; And,
and the 5th PMOS P5 and a PMOS P1 are current mirrors, therefore, when the voltage of power supply 31 raises, I
p5increase make I
p5?
in ratio increase, thereby the quiescent current of the PMOS P1 that makes to flow through reduces, the quiescent current of the first quiescent current bias circuit 331 of flowing through reduces with the rising of the voltage of power supply 31.
As shown in Figure 4, due to V
dsP1=V
gsP1, and V
dsP4but relevant with the voltage of power supply 31 power supplys, so, there is mismatch in make the to flow through quiescent current of a PMOS P1 and the quiescent current of the 4th PMOS P4 that flows through, therefore, by the 5th PMOS be used for offset shown in the impact of mismatch, thereby make the electric current of the 4th PMOS P4 keep constant.
Wherein, V
dsP5the drain-source voltage that represents the 5th PMOS P5,
represent the first reference voltage source V
0voltage, V
gsN6the gate source voltage that represents the 6th NMOS N6, V
vCCthe voltage that represents power supply 31, V
gsP1the gate source voltage that represents a PMOS P1, V
gsP5the gate source voltage that represents the 5th PMOS P5,
represent the first reference current source I
0electric current, I
p5represent the to flow through quiescent current of the 5th PMOS P5, I
p1represent the to flow through quiescent current of a PMOS P1, the quiescent current of the first quiescent current bias circuit 331 of flowing through, V
dsP1the drain-source voltage that represents a PMOS P1, V
dsP4the drain-source voltage that represents the 4th PMOS P4.
When the voltage drop of power supply 31, the operation principle of the balanced operation principle of electronic circuit 321 of described the first quiescent current during with the rising of the voltage of power supply 31 is contrary, repeats no more here.
The operation principle of the balanced electronic circuit 322 of the second quiescent current is identical with the operation principle of the balanced electronic circuit 321 of described the firstth quiescent current, repeats no more here.
Here, described electronic equipment can be mobile phone, ipad, notebook computer etc.
The simulation result figure of Fig. 5 for adopting technical solutions of the utility model to obtain, simulation result shows: adopt the technical solution of the utility model, voltage at power supply rises to the process of 5.5V from 2.5V, the quiescent current of circuit of output terminal of flowing through changes between 315uA to 324uA, and rate of change is 3%.
Simultaneously, in order to illustrate better, adopt the technical solution of the utility model, the quiescent current of circuit of output terminal of flowing through does not change with the variation of power supply voltage, adopt the technical solution of the utility model to make six integrated circuit (IC that are numbered 1,2,3,4,5,6, Integrated Circuit), and the quiescent current of the circuit of output terminal of the IC that flows through is tested, probe temperature is 25 ℃, concrete outcome is as shown in table 1.
Table 1
As can be seen from Table 1, for each IC, voltage at power supply rises to the process of 5.5V from 2.7V, flow through the variation of quiescent current of circuit of output terminal of IC only for several uA, illustrate that test result has good repeatability, and after employing the technical solution of the utility model, the quiescent current of the circuit of output terminal of the IC that flows through changes with the variation of power supply voltage hardly.
The above, be only preferred embodiment of the present utility model, is not intended to limit protection range of the present utility model.
Claims (12)
1. an output-stage circuit, comprise: power supply, quiescent current control circuit and circuit of output terminal, it is characterized in that, described output-stage circuit also comprises: when the voltage that described power supply detected changes, reduce or increase the quiescent current of the quiescent current bias circuit of flowing through in described quiescent current control circuit, the quiescent current of the described circuit of output terminal that makes to flow through keeps constant quiescent current equalizing circuit.
2. output-stage circuit according to claim 1, it is characterized in that, described quiescent current equalizing circuit reduces or increases the quiescent current of the quiescent current bias circuit of flowing through in described quiescent current control circuit, the quiescent current of described circuit of output terminal of making to flow through keeps constant, for self the quiescent current of increasing or reduce to flow through, the quiescent current of the described circuit of output terminal that makes to flow through keeps constant.
3. output-stage circuit according to claim 1, is characterized in that, described quiescent current control circuit comprises: the first quiescent current bias circuit, the second quiescent current bias circuit and floating empty voltage offset electric circuit;
Described quiescent current equalizing circuit comprises: the balanced electronic circuit of the first quiescent current and/or the balanced electronic circuit of the second quiescent current;
Described the first quiescent current bias circuit comprises: a PMOS, the 2nd PMOS, the 6th NMOS, the first reference current source and the first reference voltage source; Described the second quiescent current bias circuit comprises: a NMOS, the 2nd NMOS, the 6th PMOS, the second reference current source and the second reference voltage source; Described floating empty voltage offset electric circuit comprises: the 3rd PMOS, the 3rd NMOS, the 3rd reference current source and the 4th reference current source;
Described circuit of output terminal comprises: the 4th PMOS and the 4th NMOS;
The balanced electronic circuit of described the first quiescent current comprises the 5th PMOS, and the balanced electronic circuit of described the second quiescent current comprises the 5th NMOS.
4. output-stage circuit according to claim 3, is characterized in that,
In described the first quiescent current bias circuit, the grid of a described PMOS and drain electrode are all connected with the grid of described the 5th PMOS and the source electrode of described the 2nd PMOS in the balanced electronic circuit of described the first quiescent current, and the source electrode of a described PMOS connects described power supply; The grid of described the 2nd PMOS is all connected with the drain electrode of described the 6th NMOS and the grid of described the 3rd PMOS in described floating empty voltage offset electric circuit with drain electrode, the grid of described the 6th NMOS connects one end of described the first reference voltage source, the source electrode of described the 6th NMOS connects one end of described the first reference current source and the drain electrode of described the 5th PMOS in the balanced electronic circuit of described the first quiescent current, the other end of described the first reference current source connects earth point, and the other end of described the first reference voltage source connects earth point;
In described the second quiescent current bias circuit, the grid of a described NMOS and drain electrode are all connected with the grid of described the 5th NMOS and the source electrode of described the 2nd NMOS in the balanced electronic circuit of described the second quiescent current, and the source electrode of a described NMOS connects described earth point; The grid of described the 2nd NMOS is all connected with the drain electrode of described the 6th PMOS and the grid of described the 3rd NMOS in described floating empty voltage offset electric circuit with drain electrode, the grid of described the 6th PMOS connects one end of described the second reference voltage source, the source electrode of described the 6th PMOS connects one end of described the second reference current source and the drain electrode of described the 5th NMOS in the balanced electronic circuit of described the second quiescent current, the other end of described the second reference current source connects described power supply, and the other end of described the second reference voltage source connects described power supply;
In described floating empty voltage offset electric circuit, one end of the source electrode of described the 3rd PMOS and described the 3rd reference current source, the formed tie point of grid of described the 4th PMOS in the drain electrode of described the 3rd NMOS and described circuit of output terminal is connected, one end of the drain electrode of described the 3rd PMOS and described the 4th reference current source, the formed tie point of grid of described the 4th NMOS in the source electrode of described the 3rd NMOS and described circuit of output terminal is connected, the other end of described the 3rd reference current source connects described power supply, the other end of described the 4th reference current source connects described earth point,
In described circuit of output terminal, the source electrode of described the 4th PMOS connects for described power supply, and the drain electrode of described the 4th PMOS connects the drain electrode of described the 4th NMOS, and the source electrode of described the 4th NMOS connects described earth point;
In the balanced electronic circuit of described the first quiescent current, the source electrode of described the 5th PMOS connects described power supply;
In the balanced electronic circuit of described the second quiescent current, the source electrode of described the 5th NMOS connects described earth point.
5. a class ab ammplifier, comprising: output-stage circuit; Described output-stage circuit comprises power supply, quiescent current control circuit and circuit of output terminal, it is characterized in that, described output-stage circuit also comprises: when the voltage that described power supply detected changes, reduce or increase the quiescent current of the quiescent current bias circuit of flowing through in described quiescent current control circuit, the quiescent current of the described circuit of output terminal that makes to flow through keeps constant quiescent current equalizing circuit.
6. class ab ammplifier according to claim 5, it is characterized in that, described quiescent current equalizing circuit reduces or increases the quiescent current of the quiescent current bias circuit of flowing through in described quiescent current control circuit, the quiescent current of described circuit of output terminal of making to flow through keeps constant, for self the quiescent current of increasing or reduce to flow through, the quiescent current of the described circuit of output terminal that makes to flow through keeps constant.
7. class ab ammplifier according to claim 5, is characterized in that, described quiescent current control circuit comprises: the first quiescent current bias circuit, the second quiescent current bias circuit and floating empty voltage offset electric circuit;
Described quiescent current equalizing circuit comprises: the balanced electronic circuit of the first quiescent current and/or the balanced electronic circuit of the second quiescent current;
Described the first quiescent current bias circuit comprises: a PMOS, the 2nd PMOS, the 6th NMOS, the first reference current source and the first reference voltage source; Described the second quiescent current bias circuit comprises: a NMOS, the 2nd NMOS, the 6th PMOS, the second reference current source and the second reference voltage source; Described floating empty voltage offset electric circuit comprises: the 3rd PMOS, the 3rd NMOS, the 3rd reference current source and the 4th reference current source;
Described circuit of output terminal comprises: the 4th PMOS and the 4th NMOS;
The balanced electronic circuit of described the first quiescent current comprises the 5th PMOS, and the balanced electronic circuit of described the second quiescent current comprises the 5th NMOS.
8. class ab ammplifier according to claim 7, is characterized in that,
In described the first quiescent current bias circuit, the grid of a described PMOS and drain electrode are all connected with the grid of described the 5th PMOS and the source electrode of described the 2nd PMOS in the balanced electronic circuit of described the first quiescent current, and the source electrode of a described PMOS connects described power supply; The grid of described the 2nd PMOS is all connected with the drain electrode of described the 6th NMOS and the grid of described the 3rd PMOS in described floating empty voltage offset electric circuit with drain electrode, the grid of described the 6th NMOS connects one end of described the first reference voltage source, the source electrode of described the 6th NMOS connects one end of described the first reference current source and the drain electrode of described the 5th PMOS in the balanced electronic circuit of described the first quiescent current, the other end of described the first reference current source connects earth point, and the other end of described the first reference voltage source connects earth point;
In described the second quiescent current bias circuit, the grid of a described NMOS and drain electrode are all connected with the grid of described the 5th NMOS and the source electrode of described the 2nd NMOS in the balanced electronic circuit of described the second quiescent current, and the source electrode of a described NMOS connects described earth point; The grid of described the 2nd NMOS is all connected with the drain electrode of described the 6th PMOS and the grid of described the 3rd NMOS in described floating empty voltage offset electric circuit with drain electrode, the grid of described the 6th PMOS connects one end of described the second reference voltage source, the source electrode of described the 6th PMOS connects one end of described the second reference current source and the drain electrode of described the 5th NMOS in the balanced electronic circuit of described the second quiescent current, the other end of described the second reference current source connects described power supply, and the other end of described the second reference voltage source connects described power supply;
In described floating empty voltage offset electric circuit, one end of the source electrode of described the 3rd PMOS and described the 3rd reference current source, the formed tie point of grid of described the 4th PMOS in the drain electrode of described the 3rd NMOS and described circuit of output terminal is connected, one end of the drain electrode of described the 3rd PMOS and described the 4th reference current source, the formed tie point of grid of described the 4th NMOS in the source electrode of described the 3rd NMOS and described circuit of output terminal is connected, the other end of described the 3rd reference current source connects described power supply, the other end of described the 4th reference current source connects described earth point,
In described circuit of output terminal, the source electrode of described the 4th PMOS connects for described power supply, and the drain electrode of described the 4th PMOS connects the drain electrode of described the 4th NMOS, and the source electrode of described the 4th NMOS connects described earth point;
In the balanced electronic circuit of described the first quiescent current, the source electrode of described the 5th PMOS connects described power supply;
In the balanced electronic circuit of described the second quiescent current, the source electrode of described the 5th NMOS connects described earth point.
9. an electronic equipment, comprising: mainboard, shell and class ab ammplifier, and described class ab ammplifier comprises: output-stage circuit; Described output-stage circuit comprises power supply, quiescent current control circuit and circuit of output terminal, it is characterized in that, described output-stage circuit also comprises: when the voltage that described power supply detected changes, reduce the to flow through quiescent current of the quiescent current bias circuit in described quiescent current control circuit, the quiescent current of the described circuit of output terminal that makes to flow through keeps constant quiescent current equalizing circuit.
10. electronic equipment according to claim 9, it is characterized in that, described quiescent current equalizing circuit reduces or increases the quiescent current of the quiescent current bias circuit of flowing through in described quiescent current control circuit, the quiescent current of described circuit of output terminal of making to flow through keeps constant, for self the quiescent current of increasing or reduce to flow through, the quiescent current of the described circuit of output terminal that makes to flow through keeps constant.
11. electronic equipments according to claim 9, is characterized in that, described quiescent current control circuit comprises: the first quiescent current bias circuit, the second quiescent current bias circuit and floating empty voltage offset electric circuit;
Described quiescent current equalizing circuit comprises: the balanced electronic circuit of the first quiescent current and/or the balanced electronic circuit of the second quiescent current;
Described the first quiescent current bias circuit comprises: a PMOS, the 2nd PMOS, the 6th NMOS, the first reference current source and the first reference voltage source; Described the second quiescent current bias circuit comprises: a NMOS, the 2nd NMOS, the 6th PMOS, the second reference current source and the second reference voltage source; Described floating empty voltage offset electric circuit comprises: the 3rd PMOS, the 3rd NMOS, the 3rd reference current source and the 4th reference current source;
Described circuit of output terminal comprises: the 4th PMOS and the 4th NMOS;
The balanced electronic circuit of described the first quiescent current comprises the 5th PMOS, and the balanced electronic circuit of described the second quiescent current comprises the 5th NMOS.
12. electronic equipments according to claim 11, is characterized in that,
In described the first quiescent current bias circuit, the grid of a described PMOS and drain electrode are all connected with the grid of described the 5th PMOS and the source electrode of described the 2nd PMOS in the balanced electronic circuit of described the first quiescent current, and the source electrode of a described PMOS connects described power supply; The grid of described the 2nd PMOS is all connected with the drain electrode of described the 6th NMOS and the grid of described the 3rd PMOS in described floating empty voltage offset electric circuit with drain electrode, the grid of described the 6th NMOS connects one end of described the first reference voltage source, the source electrode of described the 6th NMOS connects one end of described the first reference current source and the drain electrode of described the 5th PMOS in the balanced electronic circuit of described the first quiescent current, the other end of described the first reference current source connects earth point, and the other end of described the first reference voltage source connects earth point;
In described the second quiescent current bias circuit, the grid of a described NMOS and drain electrode are all connected with the grid of described the 5th NMOS and the source electrode of described the 2nd NMOS in the balanced electronic circuit of described the second quiescent current, and the source electrode of a described NMOS connects described earth point; The grid of described the 2nd NMOS is all connected with the drain electrode of described the 6th PMOS and the grid of described the 3rd NMOS in described floating empty voltage offset electric circuit with drain electrode, the grid of described the 6th PMOS connects one end of described the second reference voltage source, the source electrode of described the 6th PMOS connects one end of described the second reference current source and the drain electrode of described the 5th NMOS in the balanced electronic circuit of described the second quiescent current, the other end of described the second reference current source connects described power supply, and the other end of described the second reference voltage source connects described power supply;
In described floating empty voltage offset electric circuit, one end of the source electrode of described the 3rd PMOS and described the 3rd reference current source, the formed tie point of grid of described the 4th PMOS in the drain electrode of described the 3rd NMOS and described circuit of output terminal is connected, one end of the drain electrode of described the 3rd PMOS and described the 4th reference current source, the formed tie point of grid of described the 4th NMOS in the source electrode of described the 3rd NMOS and described circuit of output terminal is connected, the other end of described the 3rd reference current source connects described power supply, the other end of described the 4th reference current source connects described earth point,
In described circuit of output terminal, the source electrode of described the 4th PMOS connects for described power supply, and the drain electrode of described the 4th PMOS connects the drain electrode of described the 4th NMOS, and the source electrode of described the 4th NMOS connects described earth point;
In the balanced electronic circuit of described the first quiescent current, the source electrode of described the 5th PMOS connects described power supply;
In the balanced electronic circuit of described the second quiescent current, the source electrode of described the 5th NMOS connects described earth point.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320390535.5U CN203491978U (en) | 2013-06-27 | 2013-06-27 | Output stage circuit, class AB amplifier and electronic device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320390535.5U CN203491978U (en) | 2013-06-27 | 2013-06-27 | Output stage circuit, class AB amplifier and electronic device |
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|---|---|
| CN203491978U true CN203491978U (en) | 2014-03-19 |
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|---|---|---|---|
| CN201320390535.5U Expired - Lifetime CN203491978U (en) | 2013-06-27 | 2013-06-27 | Output stage circuit, class AB amplifier and electronic device |
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| Country | Link |
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| CN (1) | CN203491978U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104253589A (en) * | 2013-06-27 | 2014-12-31 | 快捷半导体(苏州)有限公司 | Static current balance method, output stage circuit, AB type amplifier and electronic equipment |
| CN104333337A (en) * | 2014-11-10 | 2015-02-04 | 锐迪科微电子科技（上海）有限公司 | Quiescent current control circuit of AB-type operational amplifier |
| CN107888150A (en) * | 2017-11-28 | 2018-04-06 | 维沃移动通信有限公司 | A kind of power amplification circuit of audio signal, method and terminal device |
| CN113014209A (en) * | 2021-02-23 | 2021-06-22 | 成都西瓴科技有限公司 | Floating bias dynamic amplification circuit based on stable bandwidth circuit |
-
2013
- 2013-06-27 CN CN201320390535.5U patent/CN203491978U/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104253589A (en) * | 2013-06-27 | 2014-12-31 | 快捷半导体(苏州)有限公司 | Static current balance method, output stage circuit, AB type amplifier and electronic equipment |
| CN104253589B (en) * | 2013-06-27 | 2017-08-22 | 快捷半导体(苏州)有限公司 | Quiescent current equalization methods, output-stage circuit, class ab ammplifier and electronic equipment |
| CN104333337A (en) * | 2014-11-10 | 2015-02-04 | 锐迪科微电子科技（上海）有限公司 | Quiescent current control circuit of AB-type operational amplifier |
| CN104333337B (en) * | 2014-11-10 | 2017-08-25 | 锐迪科微电子科技（上海）有限公司 | The quiescent current control circuit of AB class operational amplifiers |
| CN107888150A (en) * | 2017-11-28 | 2018-04-06 | 维沃移动通信有限公司 | A kind of power amplification circuit of audio signal, method and terminal device |
| CN107888150B (en) * | 2017-11-28 | 2020-06-30 | 维沃移动通信有限公司 | Power amplification circuit and method for audio signal and terminal equipment |
| CN113014209A (en) * | 2021-02-23 | 2021-06-22 | 成都西瓴科技有限公司 | Floating bias dynamic amplification circuit based on stable bandwidth circuit |
| CN113014209B (en) * | 2021-02-23 | 2023-09-19 | 成都西瓴科技有限公司 | Floating bias dynamic amplifying circuit based on stable bandwidth circuit |
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