KR20140030552A - Reference voltage generator - Google Patents

Reference voltage generator Download PDF

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Publication number
KR20140030552A
KR20140030552A KR1020120096767A KR20120096767A KR20140030552A KR 20140030552 A KR20140030552 A KR 20140030552A KR 1020120096767 A KR1020120096767 A KR 1020120096767A KR 20120096767 A KR20120096767 A KR 20120096767A KR 20140030552 A KR20140030552 A KR 20140030552A
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South Korea
Prior art keywords
voltage
drain
reference voltage
nmos transistor
voltage generator
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KR1020120096767A
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Korean (ko)
Inventor
최영경
곽승욱
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에스케이하이닉스 주식회사
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Priority to KR1020120096767A priority Critical patent/KR20140030552A/en
Publication of KR20140030552A publication Critical patent/KR20140030552A/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G11C5/146—Substrate bias generators

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

According to the present invention, a reference voltage generator for generating a reference voltage which is insensitive to orbital fluctuations includes a first voltage generation part for independently generating a first voltage according to temperature change, a second voltage generation part for independently generating a second voltage according to temperature change, a compensation part for correcting the level of the second voltage in response to the first voltage outputted from the first voltage generation part, and an output part outputting the reference voltage in response to the second voltage.

Description

Reference voltage generator

The present invention relates to a device for generating a reference voltage, and more particularly to a stable reference voltage generation technology insensitive to changes in process conditions.

The voltage generator according to the prior art, in particular the circuit for generating a reference voltage may be configured in various forms.

As one of circuits for generating a reference voltage, a Widlar type reference voltage generation circuit is used.

1A is a diagram illustrating a conventional Widler type reference voltage generation circuit.

Referring to FIG. 1A, a conventional Widler type reference voltage generation circuit includes a driving voltage generation unit 10, a pull-up driving unit 20, and a loading unit 30. Here, the 'weedler method' refers to a circuit including a general widler circuit, and the general widler circuit will be described again.

The driving voltage generation unit 10 outputs a driving voltage VR_P having a level corresponding to the voltage level of the supply voltage terminal VDD. The driving voltage generator 10 includes a constant current source 11, first and second NMOS transistors MN1 and MN2, and a temperature compensator 12, and is independent of temperature change with little voltage fluctuation caused by temperature change. Generates the driving voltage VR_P.

Referring to FIG. 1A, the driving voltage generation unit 10 includes a general Weirdler circuit, which includes a constant current source 11 for generating a constant current, first and second NMOS transistors MN1 and MN2 having gates connected to each other, and And a temperature compensator 12.

The constant current source 11 includes a first PMOS transistor MP1 having a gate and a drain connected in common, and a second PMOS transistor MP2 having a source connected to a supply voltage terminal VDD, and a second PMOS transistor MP2 having a gate. Is connected to the gate of the first PMOS transistor MP1, and the first PMOS transistor MP1 connects the source to the supply voltage terminal VDD.

The correction current source 11 supplies a constant current to the drain of the first PMOS transistor MP1 and the drain of the second PMOS transistor MP2. The first PMOS transistor MP1 supplies the drain to the drain of the first NMOS transistor MN1. The second PMOS transistor MP2 connects the drain to the drain of the second NMOS transistor MN2. The second NMOS transistor MN2 having the gate and the drain connected to each other connects the source to the ground terminal VSS, and the first NMOS transistor MN1 having the drain connected to the driving voltage VR_P connects the source to the temperature compensation unit 12. The other end of the temperature compensation unit 12 is connected to the ground terminal (VSS).

The temperature compensator 12 includes a resistance for temperature compensation, and the resistance for temperature compensation may be provided as an active resistance (R0). The active resistance R0 is connected between the first NMOS transistor MN1 and the ground voltage VSS and compensates for the driving voltage VR_P that varies with temperature.

The temperature compensator 12 compensates for the temperature by the characteristics of the active resistance R0 and the first NMOS transistor MN1. As shown in FIG. 1C, in the case of the active resistor R0, the resistance is proportional to the temperature, and in the case of the transistor, the resistance is inversely proportional to the temperature, and thus, the active resistor R0 having the zero temperature coefficient insensitive to temperature changes. And the transistor MN1 may produce a temperature compensation effect. Therefore, the driving voltage VR_P independent of the temperature change can be generated.

For reference, in order to implement the same function of the general Widler circuit, the configuration of the transistor and the active resistor R0 may be changed as necessary. PMOS transistors and NMOS transistors can be replaced with each other, and various transistors can be used as needed. In addition, the active resistor R0 of the Widler circuit is required for the temperature compensation effect, and is required to obtain a temperature compensation effect together with the transistor MN2 connected to the active resistor R0, and thus has a constant resistance value and a low temperature. It may be replaced by a configuration in which the resistance value increases proportionally.

The pull-up driving unit 20 drives a constant current to the reference voltage output terminal N0 regardless of a change in the voltage level of the supply voltage terminal VDD. That is, in order to compensate for the change in the reference voltage VREF with the slope in accordance with the change in the voltage level of the supply voltage terminal VDD, the amount of current is adjusted in response to the driving voltage VR_P.

The pull-up driving unit 20 includes a third PMOS transistor MP_d connected to a driving voltage VR_P through a gate and a source connected to a supply voltage terminal VDD. The pull-up driving unit 20 includes a driving voltage VR_P and a supply voltage terminal VDD. The pull-up driving is performed to the reference voltage output terminal N0 which is the drain of the third PMOS transistor MP_d with the amount of current corresponding to the voltage difference.

The loading unit 30 is connected between the reference voltage output terminal N0 and the ground voltage terminal VSS and generates a reference voltage VREF at the reference voltage output terminal N0 having a voltage level corresponding to its resistance value. If the pull-up driving unit 20 is interpreted as having a constant resistance value, the voltage level of the reference voltage VREF formed at the reference voltage output terminal NO is determined according to the resistance value of the loading unit 30.

Since the loading unit 30 includes a diode-connected transistor (MN_d) between the pull-up driving unit 20 and the ground terminal VSS, the loading unit 30 may have a voltage difference due to a resistance value of the loading unit 30. The voltage level of the threshold voltage of the diode is output to the reference voltage VREF.

FIG. 1B is a graph illustrating changes in voltage levels of internal signals according to changes in process conditions in a conventional Widler type reference voltage generator.

Referring to FIGS. 1A and 1B, the resistance value of the third PMOS transistor MP_d changes according to the voltage of the driving voltage VR_P input to the gate of the third PMOS transistor MP_d. The voltage level of the reference voltage VREF changes under the influence of the driving voltage VR_P. That is, when the voltage level of the driving voltage VR_P is lowered due to the variation of the process conditions, the resistance of the third PMOS transistor MP_d decreases and the threshold voltage of the diode-connected transistor MN_d increases, thereby reducing the reference voltage VREF. In contrast, when the voltage level rises and the voltage level of the driving voltage VR_P rises due to the variation of the process conditions, the voltage level of the reference voltage VREF decreases while the resistance of the third PMOS transistor MP_d increases.

As described above, since the voltage level of the driving voltage VR_P varies depending on the resistance values of the transistors MP1 and MN1 and the active resistor R0, the transistor and the active resistor ( Due to variations in the resistance values of R0), there is a problem in that the voltage level of the target reference voltage VREF designed under normal process conditions varies.

An embodiment of the present invention is to provide a reference voltage generator that can reduce the variation of the reference voltage according to the variation of the process conditions.

The reference voltage generator according to the present invention includes a first voltage generator for generating a first voltage independent of temperature change, a second voltage generator for generating a second voltage independent of temperature change, and a first voltage generator. And a compensator for compensating the level of the second voltage in response to the first voltage output from the comparator, and an output for outputting a reference voltage in response to the second voltage.

The reference voltage generator according to the present invention can generate a reference voltage having a constant magnitude insensitive to variations in process conditions, thereby improving reliability.

1A is a diagram illustrating a conventional Widlar type reference voltage generator.
FIG. 1B is a graph illustrating changes in voltage levels of internal signals according to changes in process conditions in a conventional Widlar type reference voltage generator.
1C is a graph illustrating a change in resistance values of a transistor and an active resistor according to temperature change.
2 is a circuit diagram illustrating a Widler type reference voltage generator according to an exemplary embodiment of the present invention.
3 is a simulation graph comparing a Widlar type reference voltage generator according to an embodiment of the present invention and an output signal of the prior art according to a change in resistance value of a temperature compensation resistor.
FIG. 4 is a simulation graph comparing a Widlar type reference voltage generator according to an exemplary embodiment of the present invention and a conventional output signal according to transistor skew variation. FIG.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2 is a circuit diagram illustrating a Widlar type reference voltage generator according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the Widler type reference voltage generator according to an embodiment of the present invention includes a first voltage generator 110, a second voltage generator 130, a compensator 120, and an output unit 200. ).

The first voltage generator 110 is configured to generate the first voltage VR_P1 having a level corresponding to the voltage level of the supply voltage terminal VDD.

The first voltage generator 110 includes first and second PMOS transistors MP11 and MP12 having their respective sources connected to the supply voltage terminal VDD in common, and first and second NMOS transistors MN11 having their respective gates connected to each other in common. , MN12), and one end of the temperature compensation resistor R1 connected to the ground terminal VSS.

In the first voltage generator 110, a first PMOS transistor MP11 having a gate and a drain connected thereto connects a gate to a gate of the second PMOS transistor MP12, and a second NMOS transistor MN12 having a gate and a drain connected thereto. Connects the drain to the drain of the second PMOS transistor MP12, the second NMOS transistor MN12 connects the source to the ground terminal VSS, and the first NMOS transistor MN11 connects the source to the temperature compensation resistor R1. ), And the first NMOS transistor MN11 connects the drain with the drain of the first PMOS transistor MP11. Here, the drain of the first NMOS transistor MN11 outputs the first voltage VR_P1.

Referring to the operation, the first voltage generator 110 feeds back feedback of the first and second PMOS transistors MP11 and MP12 that operate as current mirrors on the first and second NMOS transistors MN11 and MN12. Constant current is supplied to the first PMOS transistor MP11, the first NMOS transistor MN11, and the temperature compensation resistor R1, and thus, the first PMOS transistor MP11, the first NMOS transistor MN11, and The first voltage VR_P1 is generated based on each resistance value of the temperature compensation resistor R1. Here, the first temperature compensation resistor R1 may be provided as an active resistance and has a resistance value corresponding to a zero temperature coefficient insensitive to temperature change, and thus a compensation voltage independent of temperature change. (VR_P) is generated.

The compensator 120 adjusts the amount of current flowing in the dynamic voltage generation unit 130 in response to the first voltage VR_P1 of the first voltage generation unit 110 to vary according to the change of the process conditions. Compensate for the second voltage VR_P2.

The compensator 120 includes a third NMOS transistor MN23. The third NMOS transistor MN23 connects a gate to the first voltage VR_P1 of the first voltage generator 110, thereby providing a first voltage (MN23). Corresponding to VR_P1, the amount of current flowing through both the drain and the source of the third NMOS transistor MN23 is adjusted. That is, since the drain and the source of the third NMOS transistor MN23 are connected in parallel to the current flowing inside the second voltage generator 130, the compensator 120 corresponds to the first voltage VR_P1. 2 Adjusts the amount of current flowing in the voltage generation unit 130.

The second voltage generator 130 is configured to generate the second voltage VR_P2 having a current level corresponding to the compensator 120 and a voltage level corresponding to the voltage level of the supply voltage terminal VDD.

The second voltage generator 130 may include third and fourth PMOS transistors MP33 and MP34 having respective sources connected to the supply voltage terminal VDD, fourth and fifth NMOS transistors MN34 and MN35 having common gates connected thereto, And a temperature compensation resistor R2 having one end connected to the ground terminal VSS. Most preferably, the second voltage generator 130 has a device configuration substantially the same as that of the first voltage generator 110.

The connection state of the components of the second voltage generation unit 130 is almost the same as that of the first voltage generation unit 110, and since the difference is only in the connection state with the compensation unit 120, the same description will be omitted. . Both ends of the drain and the source of the third NMOS transistor MN23 of the compensator 120 are connected to both ends of the drain and the source of the fourth NMOS transistor MN34 of the second voltage generator 130, that is, the fourth NMOS. The amount of current flowing through the fourth NMOS transistor MN34 is adjusted in parallel with the current flowing through the transistor MN34 in response to the first voltage VR_P1. The amount of current flowing through the fourth NMOS transistor MN34 is adjusted. This is the same as adjusting the level of the voltage of the drain of the fourth NMOS transistor MN34.

The second voltage generator 130 supplies the fourth and fifth NMOS transistors MN34 and MN35 through feedback of the third and fourth PMOS transistors MP33 and MP34 that operate as current mirrors. Since a constant current from the voltage terminal VDD is supplied to the third NMOS transistor MN23, the fourth NMOS transistor MN34, and the second temperature compensation resistor R2 connected in parallel through the third PMOS transistor MP33. The second voltage VR_P2 is generated corresponding to the resistance values of the three PMOS transistors MP33, the third and fourth NMOS transistors MN23 and MN34 connected in parallel, and the second temperature compensation resistor R2. Here, since the resistance value of the third NMOS transistor MN23 corresponds to the current regulation amount according to the compensator 120, that is, it corresponds to the voltage level of the first voltage VR_P1 connected to the gate of the third NMOS transistor MN23. do. In other words, the resistance value between the drain and the both ends of the third and fourth NMOS transistors MN23 and MN34 connected in parallel varies with the voltage level of the first voltage VR_P1.

The output unit 200 includes a pull-up driving unit 210 and the loading unit 220.

The pull-up driver 210 is configured to pull-up the reference voltage output terminal NO with a current amount corresponding to the voltage difference between the second voltage VR_P2 and the supply voltage terminal VDD. At this time, the pull-up driving unit 210 drives a constant current to the reference voltage output terminal N0 regardless of the change of the supply voltage terminal VDD. In other words, the current amount corresponding to the second voltage VR_P2 is adjusted to compensate for the change in the reference voltage VREF according to the change in the supply voltage terminal VDD.

The pull-up driving unit 210 includes a fifth PMOS transistor MP_d. The fifth PMOS transistor MP_d connecting the supply voltage terminal VDD to the source connects a gate to the second voltage VR_P2 and connects a drain. Connect to the reference voltage output terminal (N0).

The loading unit 220 is connected between the reference voltage output terminal N0 and the ground terminal VSS, and configures a reference voltage VREF having a level corresponding to its resistance value at the reference voltage output terminal N0. . That is, when the pull-up driving unit 210 is interpreted as having a constant resistance value, the voltage level of the reference voltage VREF formed at the reference voltage output terminal NO is determined according to the resistance value of the loading unit 30.

The loading unit 220 includes a sixth NMOS transistor MN_d connected to a gate and a drain. The sixth NMOS transistor MN_d connects a drain to a reference voltage output terminal N0 and a source to a battery terminal VSS. Connect. Here, the loading unit 30 is the sixth NMOS transistor (MN_d) is composed of a diode-connected transistor (Diode-connected transistor), the voltage of the diode threshold voltage due to the voltage difference by the resistance value of the loading unit 30 The level is output to the reference voltage VREF.

Hereinafter, referring to FIGS. 1B and 2, an operation of compensating when a process condition changes in a Widler type reference voltage generator according to an exemplary embodiment of the present invention will be described.

For the effective description, in the first voltage generator 110 and the second voltage generator 130, the first voltage VR_P1 and the second when the process conditions change assuming that the compensation unit 120 is not present. The change in the voltage VR_P2 will first be described, and then the operation of compensating when the compensator 120 is present will be described in detail.

Since it is assumed that the compensator 120 is not present, referring to FIG. 1B, the first voltage generator 110 and the second voltage generator 130 have the same components, so that the first voltage VR_P1 and the second voltage ( VR_P2) outputs the same voltage level. The first voltage VR_P1 is generated by the resistance values of the first PMOS transistor MP11, the first NMOS transistor MN11, and the first temperature compensation resistor R1, and the second voltage VR_P2 is generated by the third voltage. The second voltage VR_P2 is generated by the resistance values of the PMOS transistor MP33, the fourth NMOS transistor MN34, and the second temperature compensation resistor R2. Accordingly, the resistance values of the first and fourth NMOS transistors MN11 and MN34, the first and second temperature compensation resistors R1 and R2, and the first and third PMOS transistors MP11 and MP33 may be changed due to variations in process conditions. In the case of fluctuation, the first voltage VR_P1 and the second voltage VR_P2 fluctuate.

More specifically, if the process conditions change to deviate from the normal process conditions, the resistance values of the first and fourth NMOS transistors MN11 and MN34 and the first and second temperature compensation resistors R1 and R2 become high. When the resistance values of the PMOS transistors MP11 and MP33 are lowered, the voltage levels of the first voltage VR_P1 and the second voltage VR_P2 become higher than the normal process conditions.

When the voltage levels of the first voltage VR_P1 and the second voltage VR_P2 become higher than the normal process conditions, the compensation unit 120 is described to compensate for the operation of the gate of the third NMOS transistor MN23. Since the voltage level of the first voltage VR_P1 connected to the voltage is increased, the current flowing to the third NMOS transistor MN23 increases, resulting in a decrease in the value of the second voltage VR_P2. Therefore, a compensation is made in which the voltage level of the reference voltage VREF is higher than the voltage level obtained by using the prior art, and comes out close to the voltage level of the target reference voltage VREF designed under normal process conditions.

In other cases, if the process conditions change to deviate from the normal process conditions, the resistance values of the first and fourth NMOS transistors MN11 and MN34 and the first and second temperature compensation resistors R1 and R2 are lowered. When the resistance values of the 3 PMOS transistors MP11 and MP33 are increased, the voltage levels of the first voltage VR_P1 and the second voltage VR_P2 are lower than the normal process conditions.

When the voltage levels of the first voltage VR_P1 and the second voltage VR_P2 are lower than the normal process conditions, the compensating unit 120 is described to compensate for the operation of the third NMOS transistor MN23. Since the voltage level of the first voltage VR_P1 connected to the gate is lowered, the current flowing to the third NMOS transistor MN23 decreases, resulting in a higher value of the second voltage VR_P2. Therefore, the voltage level of the reference voltage VREF is lower than that of the conventional technique, and the compensation is made to be close to the voltage level of the target reference voltage VREF designed under the normal process conditions.

In addition, assuming that there is no compensation unit 120 described above, the first voltage of the first voltage generation unit 110 and the second voltage of the second voltage generation unit 130 have the same voltage level regardless of process change. Outputs According to the present invention, since the output voltages of the first voltage generator 110 and the second voltage generator 130 output the same voltage level regardless of the process change, the compensation operation by the compensator 120 effectively occurs. Therefore, most preferably, the device configuration of the first voltage generation unit 110 and the device configuration of the second voltage generation unit 130 may be the same, but according to another embodiment, the first voltage generation unit 110 and the first configuration may be the same. If only the condition that the first voltage and the second voltage of the second voltage generator 130 are output at the same voltage level is satisfied, the device configuration of the first voltage generator 110 and the device configuration of the second voltage generator 130 are satisfied. Can be different.

3 is a simulation graph comparing a Widler type reference voltage generator according to an exemplary embodiment of the present invention and an output signal of the prior art according to a change in resistance value of a temperature compensation resistor.

As shown in the simulation graph of FIG. 3, in the range in which the resistance value of the target temperature compensation resistor designed in the normal process condition decreases by 1/2 times or doubles due to the variation of the process conditions, in the prior art at 0.629V It has a variation up to 0.450V. In comparison, the output signal of the Widler type reference voltage generator according to the exemplary embodiment of the present invention has a variation of 0.597V to 0.454V. Therefore, compared with the prior art, the reference voltage generator according to the present invention operates insensitive to the change in the resistance value of the temperature compensation resistor according to the process change.

4 is a simulation graph comparing a Widler type reference voltage generator according to an exemplary embodiment of the present invention and a conventional output signal according to transistor skew variation.

As shown in the simulation graph of FIG. 4, while the skew fluctuations occur in F (Fast) and S (Slow), respectively, as the process changes, the NMOS transistor and the PMOS transistor are based on the normal process condition TT (Typical, Typical). This is a simulation result of the fluctuation of the output signal. In the variation of the output signal of the prior art, it varies from the minimum value of 0.507V to the maximum value of 0.588V, and the difference is 0.081V. In comparison, the output signal of the Widler type reference voltage generator according to the embodiment of the present invention varies from the minimum value of 0.541V to the maximum value of 0.6V, and the difference value is 0.059V. Therefore, compared with the prior art, the reference voltage generator according to the present invention operates insensitive to skew variations of transistors due to process changes.

As described above, specific description has been given according to an embodiment of the present invention. The above-described embodiment has been described as the first voltage generator 110 and the second voltage generator 130 including the Widler circuit. However, according to another exemplary embodiment, the first voltage generator 110 and the second voltage generator are described. The voltage generator 130 may include a bandgap voltage generation circuit that outputs a voltage independent of temperature change.

For reference, although the part is not directly related to the technical spirit of the present invention, an embodiment including an additional configuration may be illustrated in order to describe the present invention in more detail. Also, the configuration of the active high or active low for indicating the activation state of the signal and the circuit may vary according to the embodiment. In addition, the configuration of the transistor may be changed as necessary to implement the same function. That is, the configurations of the PMOS transistor and the NMOS transistor may be replaced with each other, and may be implemented using various transistors as needed. The detailed explanation according to the modification of the embodiment is too many cases, and the change thereof can be inferred easily by any ordinary expert, so the enumeration thereof will be omitted.

Thus, those skilled in the art will appreciate that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. .

110: first voltage generation unit
120: compensation
130: second voltage generator
200: output unit
210: pull-up drive unit
220: loading unit

Claims (7)

A first widdler circuit for generating a first voltage independent of temperature change;
A second widler circuit for generating a second voltage independent of temperature change;
A compensator for compensating for the level of the second voltage in response to the first voltage output from the first widdler circuit; And
An output unit for outputting a reference voltage in response to the second voltage
Reference voltage generator characterized in that it comprises a.
The method of claim 1,
The first widdler circuit and the second widdler circuit have substantially the same device configuration,
The second widler circuit
The first PMOS transistor having a source connected to the supply voltage terminal, a drain connected to a drain of a first NMOS transistor, and a gate and a drain connected to each other;
A second PMOS transistor having a source connected to the supply voltage terminal, a drain connected to the drain of the second NMOS transistor, and a gate connected to the gate of the first PMOS transistor;
The first NMOS transistor having a source connected to one end of a resistor, a gate connected to a second NMOS transistor, and generating the second voltage as a drain;
The second NMOS transistor having a source connected to a ground terminal and a gate and a drain connected to each other; And
The resistor whose other end is connected to the ground terminal
Reference voltage generator characterized in that the
3. The method of claim 2,
The compensation unit
A third NMOS transistor having a gate connected to the first voltage, a drain connected to a drain of the first NMOS transistor, and a source connected to the first NMOS transistor
Reference voltage generator characterized in that it comprises a
The method according to any one of claims 1 to 3,
The output
A third PMOS transistor having a gate connected to the second voltage, a source connected to the supply voltage terminal, and a drain outputting the reference voltage; And
A diode-connected NMOS transistor having a drain connected to the drain of the third PMOS transistor, a source connected to the ground terminal, and a gate and a drain connected to each other.
Reference voltage generator characterized in that it comprises a A first bandgap voltage generator circuit for generating a first voltage independent of temperature change;
A second bandgap voltage generator circuit for generating a second voltage independent of temperature change;
A compensator for compensating for the level of the second voltage in response to the first voltage output from the first bandgap voltage generator; And
An output unit for outputting a reference voltage in response to the second voltage
Reference voltage generator characterized in that it comprises a
The method of claim 5,
And the first band cap voltage generator circuit and the second band gap voltage generator circuit have substantially the same device configuration.
The method of claim 5 or 6,
The output
A PMOS transistor having a gate connected to the second voltage, a source connected to the supply voltage terminal, and a drain outputting the reference voltage; And
Diode-connected NMOS transistor with a drain connected to the drain of the PMOS transistor, a source connected to the ground terminal, and a gate and a drain connected to each other.
Reference voltage generator characterized in that it comprises a
KR1020120096767A 2012-08-31 2012-08-31 Reference voltage generator KR20140030552A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108398978A (en) * 2018-03-02 2018-08-14 湖南大学 A kind of voltage reference circuit with anti-process corner variation and Width funtion tracking range
CN114690824A (en) * 2020-12-25 2022-07-01 圣邦微电子（北京）股份有限公司 Temperature compensation voltage regulator
CN115113676A (en) * 2021-03-18 2022-09-27 纮康科技股份有限公司 Reference circuit with temperature compensation function

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108398978A (en) * 2018-03-02 2018-08-14 湖南大学 A kind of voltage reference circuit with anti-process corner variation and Width funtion tracking range
CN114690824A (en) * 2020-12-25 2022-07-01 圣邦微电子（北京）股份有限公司 Temperature compensation voltage regulator
CN114690824B (en) * 2020-12-25 2024-01-30 圣邦微电子（北京）股份有限公司 Temperature compensation voltage regulator
CN115113676A (en) * 2021-03-18 2022-09-27 纮康科技股份有限公司 Reference circuit with temperature compensation function
CN115113676B (en) * 2021-03-18 2024-03-01 纮康科技股份有限公司 Reference circuit with temperature compensation function

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