CN104111682B - Low-power consumption, low-temperature coefficient reference source circuit - Google Patents

Abstract

Low-power consumption provided by the invention, low-temperature coefficient reference source circuit, relate to field of analog integrated circuit.This circuit, comprising: start-up circuit, the current generating circuit be directly proportional to temperature, reference voltage generating circuit and Substrate bias circuit; Wherein, the described current generating circuit be directly proportional to temperature for generation of the electric current of positive temperature coefficient (PTC), in circuit, each branch road provides required electric current; Described reference voltage generating circuit is for generation of temperature independent reference voltage; Described Substrate bias circuit, for generation of Substrate bias voltage, carries out temperature compensation to described reference voltage generating circuit.Circuit of the present invention, solving existing reference source circuit is all based on band-gap reference, needs the supply voltage that high, can not meet the problem of the demand of low-power consumption, realize having good temperature characterisitic under the prerequisite meeting low-power consumption.

Description

Low-power consumption, low-temperature coefficient reference source circuit

Technical field

The present invention relates to field of analog integrated circuit, refer to low-power consumption, low-temperature coefficient reference source circuit especially.

Background technology

Reference voltage source circuit is an indispensable unit module in integrated circuit (IC) design, is widely used in various Analogous Integrated Electronic Circuits, hybrid digital-analog integrated circuit and digital integrated circuit.Universal along with various portable mobile communication and counting yield, low supply voltage and low-power consumption be one of main subject matter becoming Analog Circuit Design.

Traditional reference source circuit is all based on band-gap reference, utilize standard CMOS (ComplementaryMetalOxideSemiconductorFET, complementary metal oxide semiconductor field effect transistor) vertical BJT pipe in technique, obtain one and be similar to the irrelevant voltage source of temperature, output voltage is generally 1.25V, this means can not meet the demand of low-power consumption by the supply voltage that needs one are higher.Therefore, current technical scheme is not well positioned to meet performance requirement in circuit structure, power consumption and temperature coefficient etc., and the reference voltage source particularly realizing a low-temperature coefficient under the requirement of low-power consumption also exists very large difficulty.

Summary of the invention

The object of this invention is to provide low-power consumption, low-temperature coefficient reference source circuit, realize, under the prerequisite meeting low-power consumption, there is good temperature characterisitic.

For achieving the above object, embodiments of the invention provide a kind of low-power consumption, low-temperature coefficient reference source circuit, comprising:

Start-up circuit, the current generating circuit be directly proportional to temperature, reference voltage generating circuit and Substrate bias circuit; Wherein,

The described current generating circuit be directly proportional to temperature for generation of the electric current of positive temperature coefficient (PTC), in circuit, each branch road provides required electric current;

Described reference voltage generating circuit is for generation of temperature independent reference voltage;

Described Substrate bias circuit, for generation of Substrate bias voltage, carries out temperature compensation to described reference voltage generating circuit.

Wherein, the described current generating circuit be directly proportional to temperature comprises:

First nmos pass transistor MN1, the second nmos pass transistor MN2, the 3rd nmos pass transistor MN3, the 4th nmos pass transistor MN4, the first PMOS transistor MP1, the second PMOS transistor MP2 and the 3rd PMOS transistor MP3, wherein,

The Substrate ground GND of the source electrode of described first nmos pass transistor MN1, the substrate of described first nmos pass transistor MN1, the source electrode of described 3rd nmos pass transistor MN3, the substrate of described 3rd nmos pass transistor MN3, the source electrode of described 4th nmos pass transistor MN4 and described 4th nmos pass transistor MN4;

The grid of described first nmos pass transistor MN1 connects the grid of described second nmos pass transistor MN2, the grid of described first nmos pass transistor MN1 and the drain electrode short circuit of described first nmos pass transistor MN1;

The source electrode of described second nmos pass transistor MN2 connects the drain electrode of described 4th nmos pass transistor MN4, the source electrode of described second nmos pass transistor MN2 and the substrate short circuit of described second nmos pass transistor MN2;

The grid of described 3rd nmos pass transistor MN3 connects the grid of described 4th nmos pass transistor MN4, the grid of described 3rd nmos pass transistor MN3 and the drain electrode short circuit of described 3rd nmos pass transistor MN3;

The substrate of the substrate of the source electrode of described first PMOS transistor MP1, the substrate of described first PMOS transistor MP1, the source electrode of described second PMOS transistor MP2, described second PMOS transistor MP2, the source electrode of described 3rd PMOS transistor MP3 and described 3rd PMOS transistor MP3 meets supply voltage VDD;

The drain electrode of described first PMOS transistor MP1 connects the drain electrode of described 3rd nmos pass transistor MN3, and the grid of described first PMOS transistor MP1 connects the grid of described 3rd PMOS transistor MP3;

The drain electrode of described second PMOS transistor MP2 connects the drain electrode of described first nmos pass transistor MN1, and the grid of described second PMOS transistor MP2 connects the grid of described 3rd PMOS transistor MP3;

The drain electrode of described 3rd PMOS transistor MP3 connects the drain electrode of described second nmos pass transistor MN2, the grid of described 3rd PMOS transistor MP3 and the drain electrode short circuit of described 3rd PMOS transistor MP3;

After electric current I 2 mirror image of described 4th nmos pass transistor MN4, in circuit, each branch road provides required electric current.

Wherein, described start-up circuit comprises:

5th nmos pass transistor MS0, the 6th nmos pass transistor MS1, the 7th nmos pass transistor MS2, the 4th PMOS transistor MS3 and the first PMOS transistor electric capacity MS4, wherein,

The Substrate ground GND of the substrate of described 5th nmos pass transistor MS0, the source electrode of described 6th nmos pass transistor MS1, the substrate of described 6th nmos pass transistor MS1, the source electrode of described 7th nmos pass transistor MS2 and described 7th nmos pass transistor MS2;

The grid of described 5th nmos pass transistor MS0 connects the drain electrode of described 6th nmos pass transistor MS1 and the grid of described first PMOS transistor electric capacity MS4, and the source electrode of described 5th nmos pass transistor MS0 connects the control end of drain electrode as described start-up circuit of described 3rd nmos pass transistor MN3;

The grid of described 6th nmos pass transistor MS1 connects the grid of described 7th nmos pass transistor MS2;

The grid of described 7th nmos pass transistor MS2 and the drain electrode short circuit of described 7th nmos pass transistor MS2;

The substrate of the source electrode of the source electrode of described 4th PMOS transistor MS3, the substrate of described 4th PMOS transistor MS3, described first PMOS transistor electric capacity MS4, the drain electrode of described first PMOS transistor electric capacity MS4 and described first PMOS transistor electric capacity MS4 meets supply voltage VDD;

The drain electrode of described 4th PMOS transistor MS3 connects the drain electrode of described 7th nmos pass transistor MS2, and the grid of described 4th PMOS transistor MS3 connects the drain electrode of described 5th nmos pass transistor MS0 and the grid of described first PMOS transistor MP1 another output terminal as the start-up circuit of described reference source.

Wherein, described reference voltage generating circuit comprises:

8th nmos pass transistor MN5, the 9th nmos pass transistor MN6 and the 5th PMOS transistor MP4, wherein

The grid of described 8th nmos pass transistor MN5 and the drain electrode short circuit of described 8th nmos pass transistor MN5, the source electrode of described 8th nmos pass transistor MN5 connects the drain electrode of described 9th nmos pass transistor MN6, and as the output terminal of described reference source circuit;

The source electrode of described 9th nmos pass transistor MN6, the Substrate ground GND of described 9th nmos pass transistor MN6, the grid of described 9th nmos pass transistor MN6 connects the grid of described 8th nmos pass transistor MN5;

The source electrode of described 5th PMOS transistor MP4, the substrate of described 5th PMOS transistor MP4 meet supply voltage VDD, the grid of described 5th PMOS transistor MP4 connects the grid of described 3rd PMOS transistor MP3, and the drain electrode of described 5th PMOS transistor MP4 connects the drain electrode of described 8th nmos pass transistor MN5.

Wherein, described Substrate bias circuit comprises:

Tenth nmos pass transistor MN7 and the 6th PMOS transistor MP5, wherein,

The source electrode of described tenth nmos pass transistor MN7 and Substrate ground GND;

The grid of described tenth nmos pass transistor MN7 and drain electrode short circuit also connect the substrate of described 8th nmos pass transistor MN5;

Source class and the substrate of described 6th PMOS transistor MP5 meet supply voltage VDD;

The grid of described 6th PMOS transistor MP5 connects the grid of described 5th PMOS transistor MP4, and the drain electrode of described 6th PMOS transistor MP5 connects the drain electrode of described tenth nmos pass transistor MN7;

The grid of described tenth nmos pass transistor MN7 provides bias voltage for the substrate of described 8th nmos pass transistor MN5.

Wherein, described second PMOS transistor MP2 is identical with the breadth length ratio of described 6th PMOS transistor MP5;

Described 3rd PMOS transistor MP3 is identical with the breadth length ratio of described 5th PMOS transistor MP4, and is four times of the breadth length ratio of described second PMOS transistor MP2 and described 6th PMOS transistor MP5;

The breadth length ratio of described first PMOS transistor MP1 is the octuple of the breadth length ratio of described second PMOS transistor MP2 and described 6th PMOS transistor MP5.

The beneficial effect of technique scheme of the present invention is as follows:

The low-power consumption of the embodiment of the present invention, low-temperature coefficient reference source circuit, have good temperature characterisitic under the prerequisite meeting low-power consumption.

Accompanying drawing explanation

Fig. 1 is embodiment of the present invention low-power consumption, low-temperature coefficient reference source circuit schematic diagram.

Embodiment

For making the technical problem to be solved in the present invention, technical scheme and advantage clearly, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.

The present invention is directed to existing reference source circuit is all based on band-gap reference, need the supply voltage that high, the problem of the demand of low-power consumption can not be met, provide a kind of low-power consumption, low-temperature coefficient reference source circuit, realize, under the prerequisite meeting low-power consumption, there is good temperature characterisitic.

As shown in Figure 1, the low-power consumption of the embodiment of the present invention, low-temperature coefficient reference source circuit, comprising:

Start-up circuit, the current generating circuit be directly proportional to temperature, reference voltage generating circuit and Substrate bias circuit; Wherein,

The described current generating circuit be directly proportional to temperature for generation of the electric current of positive temperature coefficient (PTC), in circuit, each branch road provides required electric current;

Described reference voltage generating circuit is for generation of temperature independent reference voltage;

Described Substrate bias circuit, for generation of Substrate bias voltage, carries out temperature compensation to described reference voltage generating circuit.

Further, the described current generating circuit be directly proportional to temperature comprises: the first nmos pass transistor MN1, second nmos pass transistor MN2, 3rd nmos pass transistor MN3, 4th nmos pass transistor MN4, first PMOS transistor MP1, second PMOS transistor MP2 and the 3rd PMOS transistor MP3, wherein, the source electrode of described first nmos pass transistor MN1, the substrate of described first nmos pass transistor MN1, the source electrode of described 3rd nmos pass transistor MN3, the substrate of described 3rd nmos pass transistor MN3, the source electrode of described 4th nmos pass transistor MN4 and the Substrate ground GND of described 4th nmos pass transistor MN4, the grid of described first nmos pass transistor MN1 connects the grid of described second nmos pass transistor MN2, the grid of described first nmos pass transistor MN1 and the drain electrode short circuit of described first nmos pass transistor MN1, the source electrode of described second nmos pass transistor MN2 connects the drain electrode of described 4th nmos pass transistor MN4, the source electrode of described second nmos pass transistor MN2 and the substrate short circuit of described second nmos pass transistor MN2, the grid of described 3rd nmos pass transistor MN3 connects the grid of described 4th nmos pass transistor MN4, the grid of described 3rd nmos pass transistor MN3 and the drain electrode short circuit of described 3rd nmos pass transistor MN3, the substrate of the substrate of the source electrode of described first PMOS transistor MP1, the substrate of described first PMOS transistor MP1, the source electrode of described second PMOS transistor MP2, described second PMOS transistor MP2, the source electrode of described 3rd PMOS transistor MP3 and described 3rd PMOS transistor MP3 meets supply voltage VDD, the drain electrode of described first PMOS transistor MP1 connects the drain electrode of described 3rd nmos pass transistor MN3, and the grid of described first PMOS transistor MP1 connects the grid of described 3rd PMOS transistor MP3, the drain electrode of described second PMOS transistor MP2 connects the drain electrode of described first nmos pass transistor MN1, and the grid of described second PMOS transistor MP2 connects the grid of described 3rd PMOS transistor MP3, the drain electrode of described 3rd PMOS transistor MP3 connects the drain electrode of described second nmos pass transistor MN2, the grid of described 3rd PMOS transistor MP3 and the drain electrode short circuit of described 3rd PMOS transistor MP3, after electric current I 2 mirror image of described 4th nmos pass transistor MN4, in circuit, each branch road provides required electric current.

Further, described start-up circuit comprises: the 5th nmos pass transistor MS0, the 6th nmos pass transistor MS1, the 7th nmos pass transistor MS2, the 4th PMOS transistor MS3 and the first PMOS transistor electric capacity MS4, wherein, the Substrate ground GND of the substrate of described 5th nmos pass transistor MS0, the source electrode of described 6th nmos pass transistor MS1, the substrate of described 6th nmos pass transistor MS1, the source electrode of described 7th nmos pass transistor MS2 and described 7th nmos pass transistor MS2; The grid of described 5th nmos pass transistor MS0 connects the drain electrode of described 6th nmos pass transistor MS1 and the grid of described first PMOS transistor electric capacity MS4, and the source electrode of described 5th nmos pass transistor MS0 connects the control end of drain electrode as described start-up circuit of described 3rd nmos pass transistor MN3; The grid of described 6th nmos pass transistor MS1 connects the grid of described 7th nmos pass transistor MS2; The grid of described 7th nmos pass transistor MS2 and the drain electrode short circuit of described 7th nmos pass transistor MS2; The substrate of the source electrode of the source electrode of described 4th PMOS transistor MS3, the substrate of described 4th PMOS transistor MS3, described first PMOS transistor electric capacity MS4, the drain electrode of described first PMOS transistor electric capacity MS4 and described first PMOS transistor electric capacity MS4 meets supply voltage VDD; The drain electrode of described 4th PMOS transistor MS3 connects the drain electrode of described 7th nmos pass transistor MS2, and the grid of described 4th PMOS transistor MS3 connects the drain electrode of described 5th nmos pass transistor MS0 and the grid of described first PMOS transistor MP1 another output terminal as the start-up circuit of described reference source.

Further, described reference voltage generating circuit comprises: the 8th nmos pass transistor MN5, the 9th nmos pass transistor MN6 and the 5th PMOS transistor MP4, wherein, the grid of described 8th nmos pass transistor MN5 and the drain electrode short circuit of described 8th nmos pass transistor MN5, the source electrode of described 8th nmos pass transistor MN5 connects the drain electrode of described 9th nmos pass transistor MN6, and as the output terminal of described reference source circuit; The source electrode of described 9th nmos pass transistor MN6, the Substrate ground GND of described 9th nmos pass transistor MN6, the grid of described 9th nmos pass transistor MN6 connects the grid of described 8th nmos pass transistor MN5; The source electrode of described 5th PMOS transistor MP4, the substrate of described 5th PMOS transistor MP4 meet supply voltage VDD, the grid of described 5th PMOS transistor MP4 connects the grid of described 3rd PMOS transistor MP3, and the drain electrode of described 5th PMOS transistor MP4 connects the drain electrode of described 8th nmos pass transistor MN5.

Further, described Substrate bias circuit comprises: the tenth nmos pass transistor MN7 and the 6th PMOS transistor MP5, wherein, and the source electrode of described tenth nmos pass transistor MN7 and Substrate ground GND; The grid of described tenth nmos pass transistor MN7 and drain electrode short circuit also connect the substrate of described 8th nmos pass transistor MN5; Source class and the substrate of described 6th PMOS transistor MP5 meet supply voltage VDD; The grid of described 6th PMOS transistor MP5 connects the grid of described 5th PMOS transistor MP4, and the drain electrode of described 6th PMOS transistor MP5 connects the drain electrode of described tenth nmos pass transistor MN7; The grid of described tenth nmos pass transistor MN7 provides bias voltage for the substrate of described 8th nmos pass transistor MN5.

Further, described second PMOS transistor MP2 is identical with the breadth length ratio of described 6th PMOS transistor MP5; Described 3rd PMOS transistor MP3 is identical with the breadth length ratio of described 5th PMOS transistor MP4, and is four times of the breadth length ratio of described second PMOS transistor MP2 and described 6th PMOS transistor MP5; The breadth length ratio of described first PMOS transistor MP1 is the octuple of the breadth length ratio of described second PMOS transistor MP2 and described 6th PMOS transistor MP5.

In the above-described embodiments, as shown in Figure 1,3rd nmos pass transistor MN3 is operated in saturation region, 4th nmos pass transistor MN4 is operated in dark linear zone, all the other transistors are all operated in sub-threshold region, and the reference source of the embodiment of the present invention realizes the voltage Δ V of a positive temperature coefficient (PTC) on the one hand by current generating circuit _gS', wherein Δ V _gS' the difference of the gate source voltage of the 9th nmos pass transistor MN6 and the 8th nmos pass transistor MN5 when being Substrate ground as the 8th nmos pass transistor MN5, produces the voltage V of a negative temperature coefficient on the other hand by Substrate bias circuit _{gS, N7}, wherein V _{gS, N7}be the gate source voltage of the tenth nmos pass transistor MN7, mutually superposed the low-power reference source circuit realizing a low-temperature coefficient by the voltage of Positive and Negative Coefficient Temperature.

When nmos pass transistor is operated in saturation region, the drain-source current of nmos pass transistor is:

$I_D=\frac{1}{2}{\mathrm{\μ}}_n{C}_{\mathrm{ox}}K{(V_{\mathrm{CS}}-V_{\mathrm{TH}})}^2$ Formula (1)

Wherein, I _dinjection Current, μ _nthe mobility of channel carrier, C _oxbe unit area gate oxide capacitance, K is the breadth length ratio of transistor, V _gSgate source voltage, V _tHit is the threshold voltage of transistor.As can be seen from formula (1), for a given leakage current, the gate source voltage of transistor can be expressed as:

$V_{\mathrm{GS}}=V_{\mathrm{TH}}+\sqrt{\frac{{2I}_D}{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}K}}$ Formula (2)

When nmos pass transistor is operated in dark linear zone, the drain-source current of nmos pass transistor is:

I _d=μ _nc _oxk (V _gS-V _tH) V _dSformula (3)

Wherein, V _dSit is the drain-source voltage of transistor.As can be seen from formula (3), drain current I _dv _dSlinear function, this linear function can be expressed as with a linear resistance:

$R_{\mathrm{on}}=\frac{1}{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}K(V_{\mathrm{GS}}-V_{\mathrm{TH}})}$ Formula (4)

Wherein, R _onfor the conducting resistance of transistor.

When nmos pass transistor is operated in sub-threshold region, the drain-source current of nmos pass transistor is:

$I_D=(n-1){\mathrm{\μ}}_n{C}_{\mathrm{ox}}{{\mathrm{KV}}_T}^2\exp \left(\frac{V_{\mathrm{GS}}-V_{\mathrm{TH}}}{n{T}_T}\right)$ Formula (5)

Wherein, n is slope factor, V _tbe thermal voltage, size equals kT/q.As can be seen from formula (5), for a given leakage current, the gate source voltage of transistor can be expressed as:

$V_{\mathrm{GS}}=V_{\mathrm{TH}}+n{V}_T\ln \left(\frac{I_D}{(n-1){\mathrm{\μ}}_n{C}_{\mathrm{ox}}{{\mathrm{KV}}_T}^2}\right)$ Formula (6)

In formula (2) and formula (6), the threshold voltage of transistor can be expressed as:

$V_{\mathrm{TH}}=V_{\mathrm{TH}0}+\mathrm{\γ}(\sqrt{{2\mathrm{\φ}}_f+V_{\mathrm{sb}}}-\sqrt{{2\mathrm{\φ}}_f})$ Formula (7)

Wherein, V _tH0be transistor source and substrate short circuit time threshold voltage, γ is body-effect coefficient, φ _ffermi potential, V _sbit is the difference of nmos pass transistor source electrode and underlayer voltage.

In the present embodiment, first nmos pass transistor MN1, the second nmos pass transistor MN2, the 8th nmos pass transistor MN5 and the 9th nmos pass transistor MN6 are operated in sub-threshold region, 3rd nmos pass transistor MN3 is operated in saturation region, 4th nmos pass transistor MN4 is operated in dark linear zone, and the 4th nmos pass transistor MN4 drain terminal is to the voltage V on ground ₀can be expressed as:

V ₀=V _{gS, N1}-V _{gS, N2}formula (8)

Formula (6) is substituted in formula (8), can obtain:

$V_0=n{V}_T\ln \frac{K_{N2}}{a{K}_{N1}}$ Formula (9) wherein, a=I ₂i ₁.

4th nmos pass transistor MN4 drain terminal is to the voltage V on ground ₀can also be expressed as:

V ₀=I ₂r _{on, N4}formula (10)

Formula (4) and formula (9) are substituted into formula (10) and abbreviation obtains:

$I_1=\frac{2\mathrm{bn}{\mathrm{\μ}}_n{C}_{\mathrm{ox}}{K_{N4}}^2}{a^2{K}_{N3}}\·{\left(\ln \frac{K_{N2}}{a{K}_{N1}}\right)}^2\·{V_T}^2$ Formula (11) wherein, b=I ₃i ₁.

Output reference voltage can be expressed as:

V _ref＝V _GS,N6-V _GS,N5

$=\mathrm{\γ}(\sqrt{{2\mathrm{\φ}}_f}-\sqrt{{2\mathrm{\φ}}_f+V_{\mathrm{ref}}-V_{\mathrm{GS},N7}})+{\mathrm{nV}}_T\ln \frac{K_{N5}}{K_{N6}}$ Formula (12)

Formula (6) is substituted into formula (12) and abbreviation, and when obtaining, output reference voltage is:

$V_{\mathrm{ref}}=\frac{\mathrm{\γ}(\mathrm{\γ}+2\sqrt{{2\mathrm{\φ}}_f})}{2}+n{V}_T\ln \frac{K_{N5}}{K_{N6}}$

$-\mathrm{\γ}\sqrt{\mathrm{\γ}(\frac{\mathrm{\γ}}{4}+\sqrt{{2\mathrm{\φ}}_f})+{2\mathrm{\φ}}_f+{\mathrm{nV}}_T\ln \frac{K_{N5}}{K_{N6}}-V_{\mathrm{TH},N7-{\mathrm{nV}}_T\ln }[\frac{{{2\mathrm{bcK}}_{N4}}^2}{a^2{K}_{N3}{K}_{N7}}\·\frac{n}{n-1}\·{\left(\ln \frac{K_{N2}}{{\mathrm{aK}}_{N1}}\right)}^2]}$

Wherein, V _tpositive temperature coefficient, and V _{tH, N7}it is negative temperature coefficient.

Can find out that threshold voltage is positioned at radical sign from formula (13), so the second-order temperature coefficient of threshold voltage be can not ignore, the threshold voltage of the tenth nmos pass transistor MN7 be carried out Two-order approximation:

V _{tH, N7}=V _{tH, N7}(T ₀)+α (T-T ₀)+β (T-T ₀) ²formula (14)

Wherein V _{tH, N7}(T ₀) be T ₀threshold voltage at temperature, α, β are respectively single order and the second-order temperature coefficient of threshold voltage.

Formula (14) is substituted into formula (13) formula abbreviation obtain:

$V_{\mathrm{ref}}=A+B(T-T_0)-\mathrm{\γ}\sqrt{C+D(T-T_0)-\mathrm{\α}(T-T_0)-\mathrm{\β}{(T-T_0)}^2}$ Formula (15)

Wherein $A=\frac{\mathrm{\γ}(\mathrm{\γ}+2\sqrt{2{\mathrm{\φ}}_f})}{2},B=n\·\frac{k}{q}\ln \frac{K_{N5}}{K_{N6}},C=\mathrm{\γ}\·(\frac{\mathrm{\γ}}{4}+\sqrt{{2\mathrm{\φ}}_f})+{2\mathrm{\φ}}_f-V_{\mathrm{TH},N7}\left(T_0\right),$

$D=n\·\frac{k}{q}\·\left\{\begin{array}{c}\ln \frac{K_{N5}}{K_{N6}}-\ln \left[\begin{array}{c}\frac{{{2\mathrm{bcK}}_{N4}}^2}{{a^{2}K}_{N3}{K}_{N7}}\·\end{array}\frac{n}{n-1}\·{\left(\ln \frac{K_{N2}}{{\mathrm{aK}}_{N1}}\right)}^2\right]\end{array}\right\}.$

Want the reference voltage source realizing zero-temperature coefficient, then must meet:

$\frac{\∂V_{\mathrm{ref}}}{\∂}=0$ Formula (16)

Formula (15) is substituted into formula (16) abbreviation and obtains two zero points, namely

$T_1=\frac{4(D-\mathrm{\α})({\mathrm{\β\γ}}^2+B^2)+\sqrt{\mathrm{\Δ}}}{8({\mathrm{\β}}^2{\mathrm{\γ}}^2+{\mathrm{\β\γ}}^2)}+T_0,T_2=\frac{4(D-\mathrm{\α})({\mathrm{\β\γ}}^2+{\mathrm{\β}}^2)-\sqrt{\mathrm{\Δ}}}{8({\mathrm{\β}}^2{\mathrm{\γ}}^2+{\mathrm{\β\γ}}^2)}+T_0$ Formula (17)

Wherein, $\mathrm{\Δ}=16{(D-\mathrm{\α})}^2{({\mathrm{\β\γ}}^2+B^2)}^2-16({\mathrm{\β}}^2{\mathrm{\γ}}^2+{\mathrm{\β\γ}}^2)[{\mathrm{\γ}}^2{(D-\mathrm{\α})}^2-{4B}^{2}C]{.}^{}$ Can find out, when meeting Δ > 0, there are two different zero points in this reference source, achieves second order compensation, thus obtain the output reference voltage V of a low-temperature coefficient _ref.

Because the 6th PMOS transistor is used to provide Substrate bias electric current in the embodiment of the present invention, in order to reduce system power dissipation, it is identical with the breadth length ratio of the second PMOS transistor MP2 that the 6th PMOS transistor MP5 is set; Because the 3rd nmos pass transistor MN3 is operated in saturation region, 4th nmos pass transistor MN4 is operated in dark linear zone, consider system power dissipation and circuit area, arrange the octuple that the first PMOS transistor MP1 is the breadth length ratio of the second PMOS transistor MP2, the 3rd PMOS transistor MP3 is four times of the breadth length ratio of the second PMOS transistor MP2; In benchmark output circuit, the 8th nmos pass transistor MN5 and the 9th nmos pass transistor MN6 is operated in sub-threshold region, consider the size of system power dissipation and output reference voltage, arrange four times that the 5th PMOS transistor MP4 is the breadth length ratio of the second PMOS transistor MP2.

Low-power reference source circuit provided by the invention is owing to achieving second order compensation, so have good temperature characterisitic, and in reference source circuit, 3rd nmos pass transistor MN3 is operated in saturation region, 4th nmos pass transistor MN4 is operated in dark linear zone, all the other transistors are all operated in sub-threshold region, so the supply voltage needed for this reference source circuit is very low, finally achieves and have good temperature characterisitic under the prerequisite meeting low-power consumption.

The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (5)

1. low-power consumption, a low-temperature coefficient reference source circuit, is characterized in that, comprising:

Start-up circuit, the current generating circuit be directly proportional to temperature, reference voltage generating circuit and Substrate bias circuit; Wherein,

The described current generating circuit be directly proportional to temperature for generation of the electric current of positive temperature coefficient (PTC), in circuit, each branch road provides required electric current;

Described reference voltage generating circuit is for generation of temperature independent reference voltage;

Described Substrate bias circuit, for generation of Substrate bias voltage, carries out temperature compensation to described reference voltage generating circuit; Wherein, the described current generating circuit be directly proportional to temperature comprises:

First nmos pass transistor (MN1), the second nmos pass transistor (MN2), the 3rd nmos pass transistor (MN3), the 4th nmos pass transistor (MN4), the first PMOS transistor (MP1), the second PMOS transistor (MP2) and the 3rd PMOS transistor (MP3), wherein

The source electrode of the source electrode of described first nmos pass transistor (MN1), the substrate of described first nmos pass transistor (MN1), described 3rd nmos pass transistor (MN3), the substrate of described 3rd nmos pass transistor (MN3), the source electrode of described 4th nmos pass transistor (MN4) and the Substrate ground (GND) of described 4th nmos pass transistor (MN4);

The grid of described first nmos pass transistor (MN1) connects the grid of described second nmos pass transistor (MN2), the described grid of the first nmos pass transistor (MN1) and the drain electrode short circuit of described first nmos pass transistor (MN1);

The source electrode of described second nmos pass transistor (MN2) connects the drain electrode of described 4th nmos pass transistor (MN4), the source electrode of described second nmos pass transistor (MN2) and the substrate short circuit of described second nmos pass transistor (MN2);

The grid of described 3rd nmos pass transistor (MN3) connects the grid of described 4th nmos pass transistor (MN4), the grid of described 3rd nmos pass transistor (MN3) and the drain electrode short circuit of described 3rd nmos pass transistor (MN3);

The source electrode of the source electrode of the source electrode of described first PMOS transistor (MP1), the substrate of described first PMOS transistor (MP1), described second PMOS transistor (MP2), the substrate of described second PMOS transistor (MP2), described 3rd PMOS transistor (MP3) and the substrate of described 3rd PMOS transistor (MP3) connect supply voltage (VDD);

The drain electrode of described first PMOS transistor (MP1) connects the drain electrode of described 3rd nmos pass transistor (MN3), and the grid of described first PMOS transistor (MP1) connects the grid of described 3rd PMOS transistor (MP3);

The drain electrode of described second PMOS transistor (MP2) connects the drain electrode of described first nmos pass transistor (MN1), and the grid of described second PMOS transistor (MP2) connects the grid of described 3rd PMOS transistor (MP3);

The drain electrode of described 3rd PMOS transistor (MP3) connects the drain electrode of described second nmos pass transistor (MN2), the grid of described 3rd PMOS transistor (MP3) and the drain electrode short circuit of described 3rd PMOS transistor (MP3);

After electric current (I2) mirror image of described 4th nmos pass transistor (MN4), in circuit, each branch road provides required electric current.

2. low-power consumption according to claim 1, low-temperature coefficient reference source circuit, is characterized in that, described start-up circuit comprises:

5th nmos pass transistor (MS0), the 6th nmos pass transistor (MS1), the 7th nmos pass transistor (MS2), the 4th PMOS transistor (MS3) and the first PMOS transistor electric capacity (MS4), wherein,

The Substrate ground (GND) of the substrate of described 5th nmos pass transistor (MS0), the source electrode of described 6th nmos pass transistor (MS1), the substrate of described 6th nmos pass transistor (MS1), the source electrode of described 7th nmos pass transistor (MS2) and described 7th nmos pass transistor (MS2);

The grid of described 5th nmos pass transistor (MS0) connects the drain electrode of described 6th nmos pass transistor (MS1) and the grid of described first PMOS transistor electric capacity (MS4), and the source electrode of described 5th nmos pass transistor (MS0) connects the control end of drain electrode as the start-up circuit of described reference source of described 3rd nmos pass transistor (MN3);

The grid of described 6th nmos pass transistor (MS1) connects the grid of described 7th nmos pass transistor (MS2);

The grid of described 7th nmos pass transistor (MS2) and the drain electrode short circuit of described 7th nmos pass transistor (MS2);

The substrate of the source electrode of described 4th PMOS transistor (MS3), the substrate of described 4th PMOS transistor (MS3), the source electrode of described first PMOS transistor electric capacity (MS4), the drain electrode of described first PMOS transistor electric capacity (MS4) and described first PMOS transistor electric capacity (MS4) connects supply voltage (VDD);

The drain electrode of described 4th PMOS transistor (MS3) connects the drain electrode of described 7th nmos pass transistor (MS2), and the grid of described 4th PMOS transistor (MS3) connects the described drain electrode of the 5th nmos pass transistor (MS0) and the grid of described first PMOS transistor (MP1) another output terminal as the start-up circuit of described reference source.

3. low-power consumption according to claim 1, low-temperature coefficient reference source circuit, is characterized in that, described reference voltage generating circuit comprises:

8th nmos pass transistor (MN5), the 9th nmos pass transistor (MN6) and the 5th PMOS transistor (MP4), wherein,

The grid of described 8th nmos pass transistor (MN5) and the drain electrode short circuit of described 8th nmos pass transistor (MN5), the source electrode of described 8th nmos pass transistor (MN5) connects the drain electrode of described 9th nmos pass transistor (MN6), and as the output terminal of described reference source circuit;

The source electrode of described 9th nmos pass transistor (MN6), the Substrate ground (GND) of described 9th nmos pass transistor (MN6), the grid of described 9th nmos pass transistor (MN6) connects the grid of described 8th nmos pass transistor (MN5);

The source electrode of described 5th PMOS transistor (MP4), the substrate of described 5th PMOS transistor (MP4) connect supply voltage (VDD), the grid of described 5th PMOS transistor (MP4) connects the grid of described 3rd PMOS transistor (MP3), and the drain electrode of described 5th PMOS transistor (MP4) connects the drain electrode of described 8th nmos pass transistor (MN5).

4. low-power consumption according to claim 3, low-temperature coefficient reference source circuit, is characterized in that, described Substrate bias circuit comprises:

Tenth nmos pass transistor (MN7) and the 6th PMOS transistor (MP5), wherein,

The source electrode of described tenth nmos pass transistor (MN7) and Substrate ground (GND);

The grid of described tenth nmos pass transistor (MN7) and drain electrode short circuit also connect the substrate of described 8th nmos pass transistor (MN5);

Source electrode and the substrate of described 6th PMOS transistor (MP5) connect supply voltage (VDD);

The grid of described 6th PMOS transistor (MP5) connects the grid of described 5th PMOS transistor (MP4), and the drain electrode of described 6th PMOS transistor (MP5) connects the drain electrode of described tenth nmos pass transistor (MN7);

The grid of described tenth nmos pass transistor (MN7) is that the substrate of described 8th nmos pass transistor (MN5) provides bias voltage.

5. low-power consumption according to claim 4, low-temperature coefficient reference source circuit, is characterized in that, described second PMOS transistor (MP2) is identical with the breadth length ratio of described 6th PMOS transistor (MP5);

Described 3rd PMOS transistor (MP3) is identical with the breadth length ratio of described 5th PMOS transistor (MP4), and is four times of the breadth length ratio of described second PMOS transistor (MP2) and described 6th PMOS transistor (MP5);

The breadth length ratio of described first PMOS transistor (MP1) is the octuple of the breadth length ratio of described second PMOS transistor (MP2) and described 6th PMOS transistor (MP5).