CN107851614A - 垂直功率器件内的表面器件 - Google Patents
垂直功率器件内的表面器件 Download PDFInfo
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- CN107851614A CN107851614A CN201680024714.3A CN201680024714A CN107851614A CN 107851614 A CN107851614 A CN 107851614A CN 201680024714 A CN201680024714 A CN 201680024714A CN 107851614 A CN107851614 A CN 107851614A
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Abstract
一种半导体器件包括垂直功率器件,诸如超级结MOSFET、IGBT、二极管等,以及表面器件,所述表面器件包括沿半导体器件的顶部表面有电活性的一个或多个横向器件。
Description
技术领域
本公开一般地涉及在垂直功率器件管芯内集成和嵌入许多类型的表面器件(例如NMOS、PMOS等)的方法。特别地,本公开详述用于通过设计能够托管各种表面器件的最顶部表面掺杂区同时将功率器件导电区设计成能够维持指定击穿电压或者通过将功率器件和所述各种表面器件设计成与完全电气隔离的绝缘体上硅架构兼容来在垂直功率器件内集成和嵌入表面器件的方法和设计。
背景技术
用以降低***成本、提供更大功能性以及实现更高水平的精度和效率的需要正在朝向更高水平的集成持续地推动半导体。许多应用将从一个或多个垂直功率器件与包括传感器的逻辑、模拟和混合信号电路在单个管芯内的集成受益。益处包括由于集成所致的降低的产品成本,更高功能性的实现,改进的组件匹配和由于共享衬底所致的改进的热匹配。
诸如超级结MOSFET、IGBT和二极管之类的垂直功率器件使用在许多功率应用中,一个示例是开关模式电源中的MOSFET。这些应用中的许多要求外部电路以允许控制电路(例如微处理器)以最优的方式与这些功率器件对接。例如,许多应用要求分离的栅极驱动器IC以在控制电路与功率器件之间对接以便为功率器件提供其要求以最优地开关的栅极电压。为了降低***成本,提供更大的功能性,以及实现更大的精度和效率,将有利的是能够在功率器件管芯内嵌入各种类型的控制电路。本公开提供一种在垂直器件管芯内集成和嵌入许多类型的表面器件(例如NMOS、PMOS等)的方法。
附图说明
图1是依照本公开的包括垂直功率器件和混合信号表面器件的器件的框图。
图2A是依照本公开的包括在体硅上的外延部中的与混合信号器件组合的垂直功率超级结MOSFET(SJMOSFET)的半导体器件的截面视图。
图2B是SJMOSFET的部分的截面视图。
图2C是表面器件的截面视图。
图2D是器件的中等电压区的截面视图。
图2E是MV NMOS区中的晶体管的截面视图。
图2F是MV PMOS区中的晶体管的截面视图。
图2G是器件的低电压区的截面视图。
图2H是LV NMOS区中的晶体管的截面视图。
图2I是LV PMOS区中的晶体管的截面视图。
图3A是依照本公开的包括在体硅上的外延部中的与混合信号器件组合的垂直IGBT的半导体器件的截面视图。
图3B更加详细地示出IGBT的部分的截面视图。
图3C是表面器件的截面视图。
图4A是依照本公开的包括在体硅上的外延部中的与混合信号器件组合的垂直功率二极管的半导体器件的截面视图。
图4B更加详细地示出二极管的部分的截面视图。
图5是依照本公开的包括使用绝缘体上硅(SOI)技术形成的垂直功率器件和混合信号表面器件的半导体器件的框图。
图6A是包括垂直SJMOSFET和表面器件的器件的截面视图,所述垂直SJMOSFET和表面器件使用绝缘体上硅技术在体硅上的外延部中形成并且通过绝缘体分离。
图6B是SJMOSFET的部分的截面视图。
图6C是MV NMOS区的截面。
图6D是MV PMOS区的截面。
图6E是LV NMOS区的截面。
图6F是LV PMOS区的截面。
图7A是包括使用绝缘体上硅技术的IGBT的部分和表面器件的器件的截面视图。
图7B是垂直IGBT的截面视图。
图8A是包括使用绝缘体上硅技术的二极管和表面器件的器件的截面视图。
图8B更加详细地示出二极管的部分的截面视图。
图9是包括具有混合信号表面器件的垂直功率器件的器件的三维视图。
具体实施方式
虽然以下详细地讨论本公开的各种实施例的制作和使用,但是应当领会的是,本公开提供可以在多种多样的具体情境中具体化的许多适用的发明的概念。本文所讨论的具体实施例仅仅说明制作和使用本发明的具体方式并且不限制本发明的范围。
诸如MOSFET、IGBT和二极管之类的垂直功率器件是其中器件内部的电流流动的主要方向是垂直的(即从顶部向底部或底部向顶部或二者)的半导体构成物。此外,诸如超级结MOSFET之类的垂直超级结器件采用交替的n型和p型区之间的电荷平衡来实现相比于在没有电荷平衡的情况下将是可能的更低的导通电阻(RON)和更高的击穿电压(BV)。IGBT和二极管的构造不例行地采用电荷平衡架构,而是在从功率效率的立足点触发有利时可以这样做。
与垂直功率器件形成对照,用于构造逻辑电路、模拟电路、混合信号电路和存储器电路的半导体器件元件(在此统称为“电路元件”)主要是顶部表面器件。这些器件采用顶部表面的几微米内的横向电流流动(例如具有顶部表面源极、栅极和漏极端子的NMOS晶体管)、顶部表面上方的横向电流流动(多晶硅或薄膜晶体管)或在表面处收集的仅在表面的几微米(通常5um或更小)内的垂直电流流动(电流垂直流动,然后横向流动,然后回到垂直流动以便在表面处被收集)并且不从顶部表面流动到底部表面或者从底部表面流动到顶部表面(例如具有顶部表面发射极、基极和集电极端子的NPN双极型晶体管)。这类顶部表面器件构成物还包括顶部表面电容元件,和顶部表面上方电容和电感元件,以及电荷俘获非易失性存储器元件,比如EPROM、EEPROM和闪存EEPROM。
优选的实施例包括在体硅上的外延部中实现的垂直电流流动功率MOSFET、IGBT或二极管,其具有能够托管各种表面类型电路元件的顶部表面掺杂区。顶部表面掺杂区被设计成使得其足够深以包含更小和更大净掺杂水平的嵌入式阱,具有相同掺杂类型和相反掺杂类型二者,并且同时将底层功率器件漂移区(具有或没有超级结电荷平衡区)设计为足够高以仍支持垂直功率器件的必需的击穿电压。该顶部表面掺杂区将称为MV-P阱(中等电压p型阱)。由于该MV-P阱区位于垂直器件的表面并且电气连接到功率器件的低侧电压,并且由于向垂直构造的背侧施加功率器件的高侧电压并且该高侧电压从垂直器件的底部向顶部下降,因此MV-P阱区在零伏特电位处被有效地偏置。MV-P阱区可以因而被绘制成跨越功率器件漂移区(在超级结MOSFET的情况下包括交替的p型和n型超级结柱)并且可以充当用于相反掺杂类型阱的掺杂阱宿主(host)使得导电类型器件(变化的电压能力的横向、表面NMOS和PMOS)和双极型晶体管二者可以嵌入在MV-P阱区内。
可以使用体硅衬底上的外延部来实现垂直功率器件与逻辑、模拟、非易失性存储器和混合信号电路(表面器件)的集成,如在优选实施例中描述的那样,但是它还可以使用SOI(绝缘体上硅)衬底来实现。使用SOI衬底的可替换的实施例是垂直电流流动功率MOSFET、IGBT或二极管,其通过绝缘物填充的沟槽与相邻的表面类型电路区或甚至附加的垂直电流流动功率MOSFET、IGBT或二极管区横向隔离,所述绝缘物填充的沟槽跨越功率器件漂移区、横切SOI的底部绝缘体并且为每一个器件区提供完全电介质隔离。对每一个垂直功率器件的高电压端子的接入通过高电压端子区内的任何处置晶片(如果被利用的话)和SOI绝缘体的背侧图案化和蚀刻来获得。对于MOSFET,在每一个漏极区之上图案化和蚀刻任何处置晶片(如果被利用的话)以及SOI绝缘体,并且沉积、图案化和蚀刻背侧金属化物以保留在每一个MOSFET漏极区之上。对于IGBT,图案化和蚀刻任何处置晶片(如果被利用的话)以及SOI绝缘体,执行和退火p+注入并且沉积、图案化和蚀刻背侧金属以保留在IGBT集电极区中的每一个中。对于二极管,在每一个阴极区之上图案化和蚀刻任何处置晶片(如果被利用的话)以及SOI绝缘体,并且沉积、图案化和蚀刻背侧金属化物以保留在每一个二极管阴极区之上。
以下描述超级结MOSFET与邻近的经介电隔离的表面器件区的详细示例SOI工艺实现方式。开始的SOI可以具有任何类型,例如,利用分离技术的晶片接合(使用氢注入,比如Smart CutTM或其他分离技术),或氧注入技术比如通过氧注入进行的分离(SIMOX)。如今,SOI的大部分实现方式使用绝缘体的顶部上的相对薄的硅(若干微米),因此用于集成功率器件的实现方式通常用于经完全介电隔离的横向高电压器件(例如横向扩散MOS(LDMOS))或用于具有与漏极(MOSFET)、集电极(IGBT)或阴极(二极管)的顶侧接触的垂直功率器件,并且不用于具有与漏极(MOSFET)、集电极(IGBT)或阴极(二极管)的背侧接触的垂直功率器件。
用于在使用晶片接合技术构造的SOI晶片上构建垂直超级结MOSFET的示例工艺流将为如下:
1)以具有低n型掺杂(小于1E16原子/cm3)的体Si晶片开始。
2)在通过使用晶片接合技术来使用该起始体Si晶片构造SOI基底晶片之前,利用N+砷掺杂(剂量等于或大于2E15原子/cm²)注入起始Si晶片,其稍后将形成超级结MOSFET的重掺杂漏极。
3)在重掺杂的N+晶片表面上生长SiO2并且以所选晶片接合SOI制造技术的正常形式完成SOI基底晶片的构造。
4)对于多外延沉积超级结实现方式,通过沉积多个外延层并且向每一个外延层中执行一个或多个经掩蔽的p型注入而将超级结p型柱构建到SOI晶片的顶侧上。
5)对于沟槽超级结实现方式,在一次沉积中向SOI晶片的顶侧上沉积完整厚度的超级结外延,蚀刻沟槽,并且通过例如利用选择性p型外延重新填充沟槽或者利用p型掺杂剂注入侧壁并且利用SiO2或SiO2和多晶硅的组合重新填充沟槽等等来形成超级结。
6)在多外延和沟槽超级结实现方式二者中,蚀刻深沟槽(不同于沟槽超级结实现方式中的超级结沟槽),其向下延伸到底部SOI隔离氧化物并且在利用氧化物蚀刻后填充这些沟槽以介电隔离(一个或多个)超级结功率器件与CMOS、双极型、非易失性存储器和其他混合信号区域(即,表面器件区域)。
7)在完成正侧处理之后:
a)研磨掉背侧处置晶片的所有或部分的厚度。随后的处理要求处置薄晶片(10密尔或更小)的能力。
b)仅在超级结区域之上,在背侧上图案化和蚀刻背侧处置晶片厚度的其余部分(如果有的话)和隔离氧化物,以便暴露背侧重掺杂的N+漏极硅。
c)沉积(一个或多个)背侧金属以便与背侧漏极硅电气接触。
d)为了形成多个介电隔离的垂直超级结MOSFET,图案化背侧金属化物以分离每一个独立漏极连接。可能必要的是在对背侧处置晶片的图案化和蚀刻与对SOI隔离氧化物的图案化和蚀刻之间沉积绝缘层,使得随后的背侧金属沉积不与处置晶片接触,这可能使背侧金属蚀刻的末端指示是困难的。此外,为了封装具有背侧上的多个隔离的垂直超级结MOSFET漏极的配置,封装管芯叶片将需要具有多个连接区段。
8)对于如以上描述的SOI配置,CMOS、双极型、非易失性存储器和其他混合信号区域(即表面器件区域)可以均与(一个或多个)垂直功率器件区域并且与彼此介电隔离,其中的某些实施例在图5至8B中示出和描述。
参照图1,器件102包括垂直功率器件104和混合信号表面器件108。
垂直功率器件104被形成为体硅116上的外延硅110的部分并且连接到金属126和金属118。垂直功率器件104包括形成单个高功率器件的并联连接的半导体器件,诸如SJMOSFET、IGBT、硅结二极管、肖特基二极管或复合器件。金属126与金属118之间的器件102的高度充分高以支持垂直功率器件104的给定击穿电压。垂直功率器件104的最顶部部分形成器件102的最顶部掺杂区的部分。垂直功率器件104具有背侧连接,其不将高电压端子路由回到顶部表面,并且替代地,将高电压端子带出在背表面上,诸如通过金属118。背侧端子是主要的高电压电流运载端子,诸如漏极(MOS)、集电极(IGBT)或阴极(二极管)。背侧端子不是寄生端子,比如寄生电容或寄生结,其在器件的主要功能中不被牵涉到。
表面器件108是混合信号器件,其包括形成在外延硅110的顶部表面中或顶部表面上的一个或多个模拟器件和数字器件,所述外延硅110形成在体硅116上。表面器件108包括中等电压(MV)区120和低电压(LV)区122。可替换的实施例使用一个或多个MV区、一个或多个LV区、或者一个或多个MV区和LV区的组合。形成表面器件108的电子电路沿器件102的顶部表面有电活性,使得来自表面器件108的电流不流动到器件102的底部或背侧表面上的金属118。表面器件108,连同垂直功率器件104的最顶部部分,形成器件102的最顶部掺杂区。形成表面器件108的器件是横向器件,因为它们沿器件102的顶部表面处的横向轴有电活性,或者是垂直器件(诸如NPN晶体管),其主要电气活动被限制在表面器件区内。
在某些实施例中,形成表面器件108的电子电路用于控制垂直功率器件104。在某些实施例中,表面器件108包括一个或多个横向NMOS、横向PMOS、LDMOS、垂直NPN、垂直PNP、横向NPN和横向PNP晶体管。在某些实施例中,表面器件108的电路形成一个或多个EPROM(可擦除可编程只读存储器)或EEPROM(电可擦除可编程只读存储器)非易失性存储器元件。在某些实施例中,表面器件108包括一个或多个电容、电感和电阻元件。可替换的实施例可以具有形成在表面器件108中的任何数目或类型的电气组件,诸如晶体管、电阻器、电容器等等,以形成任何数目的数字或模拟组件,诸如模拟到数字转换器、数字到模拟转换器、逻辑门、存储器、处理器、状态机、EPROM、EEPROM、逻辑门等。
MV区120包括NMOS区142和PMOS区144内部的一个或多个晶体管。在附加的实施例中,NMOS区142与PMOS区144之间的某些晶体管彼此问候以便形成从简单的逻辑门和存储器到复杂的状态机和处理器的CMOS逻辑电路。
LV区122包括NMOS区168和PMOS区169内部的一个或多个晶体管。LV区122使用比MV区120中的晶体管更低的电压和更小的晶体管尺寸。
金属126包括一个或多个金属层。最顶部金属层是厚的(大约2-5微米[μm]厚)以便运载用于垂直功率器件104的电流。
对于连接表面器件108的金属126的部分,金属126可以包括一个或多个较薄的下部金属层,大约0.3-1.0μm厚并且最靠近于硅,以用于在MV区120和LV区122中的密集布线。这些较薄的层然后用作为最顶部金属层的厚功率器件金属层结束。在垂直功率器件104上方的金属126的较薄的层被堆叠并且包括过孔以从厚的最顶部金属层一直到较薄的金属层并且最终向下至垂直功率器件104输送电流。
由于体硅116上的外延硅110的部分不运载表面器件108下方的电流,因此外延硅110的该部分将具有比形成垂直功率器件104的外延硅110的部分更低的温度。在某些实施例中,表面器件108的区在策略上被放置或散置在垂直器件区域周围或垂直器件区域内,以便耗散来自垂直功率器件104的热量并且降低器件102的总体温度。
参照图2A,示出半导体器件202的截面视图,所述半导体器件202包括在体硅上的外延部中或外延部上的与混合信号器件组合的垂直功率超级结MOSFET(SJMOSFET)。器件202是图1的器件102的实施例。
器件202包括第一SJMOSFET部分204、第二SJMOSFET部分206和表面器件208,其全部形成在体硅216上的外延硅210中或外延硅210上。
第一SJMOSFET部分204和第二SJMOSFET部分206与彼此电气连接。可以包括附加的SJMOSFET部分以增加形成在器件202上的SJMOSFET的功率处置容量。
外延硅210包括形成在N型外延层214中的P型硅柱212。P型硅柱212和N型外延层214被掺杂到从大约4-6乘以10的15次幂(中等E15)cm-3至大约1-3乘以10的16次幂(低E16)cm-3。N+层216是与晶片的背侧上的金属层218接触的体硅层。
在某些实施例中,P型柱212通过执行到设置在n+体衬底上的一个或多个n型外延硅沉积中的每一个中的经掩蔽的p型注入来构造。在某些实施例中,P型柱212通过向设置在n+体衬底上的n型外延区中蚀刻沟槽,利用P型注入来注入沟槽侧壁并且利用未经掺杂的外延硅或利用二氧化硅重新填充沟槽来构造。在某些实施例中,P型柱212通过向设置在n+体衬底上的n型外延区中蚀刻沟槽,在沟槽中生长衬垫二氧化硅,利用P型注入来注入沟槽侧壁并且利用经掺杂的或未经掺杂的多晶硅重新填充沟槽来构造。
在某些实施例中,由于经垂直蚀刻的绝缘沟槽的添加,对于器件202的SJMOSFET而言不需要高电压终止区,所述经垂直蚀刻的绝缘沟槽利用具有充分低的内部电荷的沟槽绝缘材料来提供充分的电气隔离以便不扰动邻近超级结柱的电荷平衡。在某些实施例中,经垂直蚀刻的绝缘沟槽基本上平分P型柱宽度以便维持电荷平衡。
在某些实施例中,经垂直蚀刻的绝缘沟槽基本上平分N型柱宽度以便维持电荷平衡。对于使用体硅上的外延部技术的设计,添加经垂直蚀刻的绝缘沟槽,比如存在于SOI技术中的那些,以减小由使用在体块上外延技术中的高电压终止区消耗的面积。经垂直蚀刻的绝缘沟槽横向电气隔离表面器件的区与功率器件的区,同时仍旧依赖于结/漂移隔离来提供垂直电气隔离,因为在体块上外延部设计中不存在底部绝缘体。
在某些实施例中,表面器件208包括中等电压(MV)区220和低电压(LV)区222。作为示例,表面器件208包括四个晶体管。可替换的实施例可以包括仅一个MV区、仅一个LV区、或其组合,并且具有任何数目或类型的电气组件,诸如晶体管、电阻器、电容器等等,以形成任何数目的数字或模拟组件,诸如模拟到数字转换器、数字到模拟转换器、逻辑门、存储器、处理器、状态机、EPROM、EEPROM、逻辑门等等。
钝化层224涂敷器件202的顶部表面以使器件202较少受环境因素影响。钝化层224利用氧化物、氮化物、聚酰亚胺等等中的一个或多个来形成。
图2B更加详细地示出SJMOSFET部分204的截面。
金属226将SJMOSFET部分204的源极互连到其他SJMOSFET部分(诸如SJMOSFET部分206)的源极。在可替换的实施例中,可以使用多级金属拓扑。多级金属拓扑可以将铝(Al)用于所有层,或者可以将Al用于最底部金属层,其与用于最顶部金属层的铜(Cu)组合,只要最顶部层足够厚(大约2-5微米[μm]厚)以处置器件202的SJMOSFET的高功率要求。对于MV区220和LV区222中的金属层,金属层226可以具有一个或多个较薄的下部金属层,大约0.3-1.0μm厚并且最靠近于硅,以用于在MV区220和LV区222中的密集布线。这些较薄的层然后用作为最顶部金属层的厚功率器件金属层结束。对于具有较薄的金属层的器件202的SJMOSFET部分,下部金属层和下部过孔层的堆叠将从最顶部金属层向硅内的SJMOSFET输送电流。
过孔228利用钨(W)插头制作,所述钨(W)插头具有接触底部和用阻挡层诸如钛(Ti)、氮化钛(TiN)或其组合镶衬的侧壁。
层间电介质(ILD)230是由多晶硅制成的栅极238和金属226之间的电介质材料层。功率器件,诸如器件202的SJMOSFET,典型地包括多个SiO2(氧化物)层,最靠近表面具有不带电的、未经掺杂的氧化物层(非等离子体增强沉积),其随后是经掺杂(例如PSG(磷硅酸盐玻璃))和等离子体沉积的氧化物(例如PETEOS(等离子体增强正硅酸乙酯))。
场氧化物232是用于功率器件的层场氧化物,其通常是厚厚沉积(在表面上)的氧化物(即不是硅的局部氧化(LOCOS))并且被湿法蚀刻以给它非常接近于45°的倾斜以便维持平滑变化的电场。这对于功率器件是重要的,因为它从核心区(其中电场多半是垂直的)过渡到终止区(其中电场是水平和垂直的组合,多半是水平的)。
栅极氧化物234将栅极238与n柱和p主体236分离。
P主体掺杂236形成SJMOSFET部分204的沟道区,其还可以称为VDMOS(垂直扩散金属氧化物半导体)器件。P主体236包括N+和P基础掺杂区,其未被示出。
栅极238包括多晶硅并且施加于栅极238的电压控制在器件202的SJMOSFET的源极和漏极之间传递的电流的量。
图2C是表面器件208的截面视图。表面器件208包括中等电压(MV)区220和低电压(LV)区222。中等电压区220和低电压区222均包括两个范例MOSFET器件。在可替换的实施例中,表面器件208包括附加的晶体管和组件以执行模拟信号处理和数字信号处理中的一个或多个。在一个可替换的实施例中,表面器件208包括附加的晶体管以形成用于控制SJMOSFET器件202的通/断状态的状态机。表面器件208包括形成在外延硅210的顶部处的中等电压P型阱(MV P阱)240。MV P阱240被掺杂到大约低至中等E16 cm-3的浓度,其下限由N型外延层214的浓度限制,使得MV P阱240的掺杂浓度大于N型外延层214的本底掺杂浓度。
图2D是器件202的中等电压区220的截面视图。中等电压区220包括中等电压N型金属氧化物半导体(MV NMOS)区242和中等电压P型金属氧化物半导体(MV PMOS)区244。
MV NMOS区242包括形成在MV P阱240中的晶体管246。
MV PMOS区244包括形成在MV N阱250中的晶体管248。MV N阱250形成在MV P阱240内部并且被掺杂到中等E16 cm-3中的浓度,其具有由MV P阱240的掺杂浓度限制的下限,使得MV N阱250的掺杂浓度大于MV P阱240的本底掺杂浓度。
图2E是MV NMOS区242中的晶体管246的截面视图。晶体管246包括栅极252、源极254和漏极256。栅极252由多晶硅制成,其基于施加于栅极252的电压而控制源极253与漏极254之间的电流。栅极氧化物层255将栅极252与外延硅210分离。源极253包括形成在外延硅210的顶部处MV P阱240内部的N+区256和N++区257。漏极254包括形成在外延硅210的顶部处MV P阱240内部的N+区258和N++区259。对于大约7-9乘以10的19次幂(高E19)至中等E20cm-3的浓度,N++区257和259的剂量为大约3-7 E15 cm-2。N+区256和258分别围绕N++区257和259,以分级出横向场并且使晶体管246能够操作在中等电压电平下。对于从中等E17至高E18 cm-3的浓度,N+区256和258的剂量是从高E13至高E14 cm-2。
图2F是MV PMOS区244中的晶体管248的截面视图。晶体管248包括栅极260、源极261和漏极262。栅极260由多晶硅制成,其基于施加于栅极260的电压控制源极261与漏极262之间的电流。栅极氧化物层263分离栅极260与外延硅210。源极261包括形成在外延硅210的顶部处MV N阱250内部的P+区264和P++区265。漏极262包括形成在外延硅210的顶部处MV N阱250内部的P+区266和P++区267。对于中等E19至中等E20 cm-3中的浓度,P++区265和267的剂量为大约1-5 E15 cm-2。P+区264和266分别围绕P++区265和267以分级出横向场并且使晶体管248能够操作在中等电压电平下。对于从中等E17至高E18 cm-3的浓度,P+区264和266的剂量是从高E13至高E14 cm-2。
图2G是器件202的低电压区222的截面视图。低电压区222包括低电压N型金属氧化物半导体(LV NMOS)区268和低电压P型金属氧化物半导体(LV PMOS)区269。
LV NMOS区268包括形成在LV P阱272中的晶体管270。LV P阱272形成在MV P阱240内部并且具有从大约中等E16至中等E17 cm-3的掺杂浓度。
LV PMOS区269包括形成在LV N阱273中的晶体管271。LV N阱273形成在MV P阱240内部并且具有从大约高E16至中等E17 cm-3的掺杂浓度,其下限由MV P阱240的掺杂浓度限制,使得LV N阱273的掺杂浓度大于MV P阱240的本底掺杂浓度。
图2H是LV NMOS区268中的晶体管270的截面视图。晶体管270包括栅极274、源极275和漏极276。栅极274由多晶硅制成,其基于施加于栅极274的电压而控制源极275与漏极276之间的电流。栅极氧化物层277分离栅极274与外延硅210。源极275包括形成在外延硅210的顶部处LV P阱272内部的N++区278,所述LV P阱272形成在MV P阱240内部。漏极276包括形成在外延硅210的顶部处LV P阱272内部的N++区279。对于从高E19至中等E20 cm-3的浓度,N++区278和279的剂量为大约3-7 E15 cm-2。
图2I是LV PMOS区269中的晶体管271的截面视图。晶体管271包括栅极280、源极281和漏极282。栅极280由多晶硅制成,其基于施加于栅极280的电压控制源极281与漏极282之间的电流。栅极氧化物层283分离栅极280与外延硅210。源极281包括形成在外延硅210的顶部处LV N阱273内部的P++区285。漏极282包括形成在外延硅210的顶部处LV N阱273内部的P++区284。对于中等E19至中等E20 cm-3的浓度,P++区284和285的剂量为大约1-5E15 cm-2。
图2J是具有垂直功率器件的器件的截面视图,所述垂直功率器件包括与SJMOSFET部分204平行的超级结IGBT(SJIGBT)部分207。与SJMOSFET平行地提供SJIGBT形成复合超级结IGBT和MOSFET高电压器件。用于SJIGBT部分207和SJMOSFET部分204的栅极总线可以被分离以便单独地控制SJIGBT部分207和SJMOSFET部分204的通-断时序。SJIGBT部分207和SJMOSFET部分204的相对通-断时序的优化导致具有与IGBT的优秀电流处置能力组合的MOSFET的优秀开关速度的复合器件。在某些实施例中,嵌入式混合信号电路控制SJIGBT部分207和SJMOSFET部分204的相对通-断时序以优化复合器件的开关速度和电流处置能力。
参照图3A,所示出的是包括在体硅上的外延部中的与混合信号器件组合的垂直IGBT的半导体器件302的截面视图。器件302是图1的器件102的实施例。
第一IGBT部分304和第二IGBT部分306与彼此电气连接。可以包括附加的IGBT部分以增加形成在器件302上的IGBT的功率处置容量。
外延硅310包括N型外延层314,其被掺杂到从大约4-6乘以10的15次幂(中等E15)cm-3至大约1-3乘以10的16次幂(低E16)cm-3的浓度。体硅N+层316和金属层318形成在晶片的背侧上。
表面器件308包括中等电压(MV)区320和低电压(LV)区322。表面器件308包括四个晶体管。可替换的实施例可以包括仅一个MV区、仅一个LV区或其组合,并且具有任何数目或类型的电气组件,诸如晶体管、电阻器、电容器等等,以形成任何数目的数字或模拟组件,诸如模拟到数字转换器、数字到模拟转换器、逻辑门、存储器、处理器、状态机等等。
钝化层324涂敷器件302的顶部表面以使器件302较少受环境因素影响。钝化层324利用氧化物、氮化物、聚酰亚胺等等中的一个或多个形成。
图3B更加详细地示出IGBT部分304的截面。
金属326将IGBT部分304的发射极互连到其他IGBT部分(诸如IGBT部分306)的发射极。在可替换的实施例中,可以使用多级金属拓扑。多级金属拓扑可以将铝(Al)用于所有层,或者可以将Al用于最底部金属层,其与用于最顶部金属层的铜(Cu)组合,只要最顶部层足够厚(大约2-5微米[μm]厚)以处置器件302的IGBT的高功率要求。MV区320中的MV NMOS晶体管346的源极通过金属326连接到器件302的IGBT的发射极。
过孔328利用钨(W)插头制作,所述钨(W)插头具有接触底部和用阻挡层诸如钛(Ti)、氮化钛(TiN)或其组合镶衬的侧壁。
层间电介质(ILD)330是由多晶硅制成的栅极和金属326之间的电介质材料层。功率器件,诸如器件302的IGBT,典型地包括多个SiO2(氧化物)层,最靠近表面具有不带电的、未经掺杂的氧化物层(非等离子体增强沉积),其随后是经掺杂(例如PSG)和等离子体沉积的氧化物(例如PETEOS)。
场氧化物332是用于功率器件的层场氧化物,其通常是厚沉积(在表面上)的氧化物(即不是硅的局部氧化(LOCOS))并且被湿法蚀刻以给它非常接近于45°的倾斜以便维持平滑变化的电场。这对于功率器件是重要的,因为它从核心区(其中电场多半是垂直的)过渡到终止区(其中电场是水平和垂直的组合,多半是水平的)。
栅极氧化物334将栅极338与晶片的外延硅310中的N型外延层314分离。
朝向IGBT部分306中的外延硅310的顶部表面形成P主体掺杂336,其具有在低E16cm-3至低E18 cm-3的范围中的掺杂。N++层331形成在P主体336内。
栅极338包括多晶硅并且施加于栅极338的电压控制在器件302的IGBT的发射极和集电极之间传递的电流的量。为了附图中的清楚性,未示出栅极接触件和控制。
P+层339与N+层316形成P-N结以形成第一IGBT部分304的集电极。
图3C是表面器件308的截面视图。表面器件308包括中等电压(MV)区320和低电压(LV)区322。中等电压区320和低电压区322均包括两个范例MOSFET器件。在可替换的实施例中,表面器件308包括附加的晶体管和组件以执行模拟信号处理和数字信号处理中的一个或多个。在一个可替换的实施例中,表面器件308包括附加的晶体管以形成用于控制器件302的IGBT的通/断状态的状态机。表面器件308包括形成在外延硅310的顶部处的中等电压P型阱(MV P阱)340。MV P阱340被掺杂到大约低到中等E16 cm-3的浓度,其下限由N型外延层314的浓度限制,使得MV P阱340的掺杂浓度大于N型外延层314的本底掺杂浓度。
金属326形成为ILD 330的顶部上的单个不连续的层。在可替换的实施例中,MV区320和LV区322中的金属层、金属层326可以具有一个或多个“薄的”下部金属层,大约0.3-1.0μm厚并且最接近于硅,以用于在MV区320和LV区322中的密集布线。这些薄层然后用作为最顶部金属层的厚功率器件金属层结束。对于具有薄金属层的器件302的IGBT部分,下部金属层和下部过孔层的堆叠将从最顶部金属层向硅内的IGBT输送电流。
中等电压区320包括中等电压N型金属氧化物半导体(MV NMOS)区342和中等电压P型金属氧化物半导体(MV PMOS)区344。MV NMOS区342包括形成在MV P阱340中的晶体管346。MV PMOS区344包括形成在MV N阱350中的晶体管348。
MV N阱350形成在MV P阱340内部并且被掺杂到中等E16 cm-3中的浓度,其具有由MV P阱340的掺杂浓度限制的下限,使得MV N阱350的掺杂浓度大于MV P阱340的本底掺杂浓度。
MV NMOS区342中的晶体管346和MV PMOS区344中的晶体管348在形式和功能方面分别与图2E的晶体管246和图2F的晶体管238类似。
低电压区322包括低电压N型金属氧化物半导体(LV NMOS)区368和低电压P型金属氧化物半导体(LV PMOS)区369。LV NMOS区368包括形成在LV P阱372中的晶体管370。LV P阱372形成在MV P阱340内部并且具有从大约中等E16至中等E17 cm-3的掺杂浓度。
LV PMOS区369包括形成在LV N阱373中的晶体管371。LV N阱373形成在MV P阱340内部并且具有从大约高E16至中等E17 cm-3的掺杂浓度,其下限由MV P阱340的掺杂浓度限制,使得LV N阱373的掺杂浓度大于MV P阱340的本底掺杂浓度。
LV NMOS区368中的晶体管370和LV PMOS区369中的晶体管371在形式和功能方面分别与图2H的晶体管270和图2I的晶体管271类似。
参照图4A,示出半导体器件402的截面视图,半导体器件402包括在体硅上的外延部中或外延部上的与混合信号器件组合的垂直功率二极管。器件402是图1的器件102的实施例。
第一二极管部分404和第二二极管部分406与彼此电气连接。可以包括附加的二极管部分以增加形成在器件402上的二极管的功率处置容量。
外延硅410包括N型外延层414,所述N型外延层414被掺杂到从大约4-6乘以10的15次幂(中等E15)cm-3至大约1-3乘以10的16次幂(低E16)cm-3的浓度。N+层416是与晶片的背侧上的金属层418接触的体硅层。
表面器件408包括中等电压(MV)区420和低电压(LV)区422。表面器件408包括四个晶体管。可替换的实施例可以包括仅一个MV区、仅一个LV区或其组合,并且具有任何数目或类型的电气组件,诸如晶体管、电阻器、电容器等等,以形成任何数目的数字或模拟组件,诸如模拟到数字转换器、数字到模拟转换器、逻辑门、存储器、处理器、状态机等等。
钝化层424涂敷器件402的顶部表面以使器件402较少受环境因素影响。钝化层424利用氧化物、氮化物、聚酰亚胺等等中的一个或多个来形成。
MV区420包括MV NMOS晶体管446和MV PMOS晶体管448。MV区420及其相应的晶体管在形式和功能方面与图2C的MV区220和图3C的MV区320类似。
LV区422包括LV NMOS晶体管470和LV PMOS晶体管471。LV区422及其相应的晶体管在形式和功能方面与图2C的LV区222和图3C的LV区322类似。
图4B更加详细地示出二极管部分404的截面。
金属426将二极管部分404的阳极互连到其他二极管部分(诸如二极管部分406)的阳极。在可替换的实施例中,铝(Al)或铜(Cu)使用在多级金属拓扑中,其具有厚的Al层以处置器件402的二极管的高功率要求。在多级金属拓扑中,全部使用Al,或者靠近硅使用Al其在上部层中变成Cu。金属的最顶部层是厚的(大约2-5微米(μm)厚)以运载用于器件402的电流。MV区420中的MV NMOS晶体管446的源极通过金属426连接到器件402的二极管的发射极。
过孔428利用钨(W)插头制作,所述钨(W)插头具有接触底部和用阻挡层诸如钛(Ti)、氮化钛(TiN)或其组合镶衬的侧壁。
层间电介质(ILD)430是将金属426与器件402的电活性部分分离的电介质材料层。功率器件,诸如器件402的二极管,典型地包括多个SiO2(氧化物)层,最靠近表面具有不带电的、未经掺杂的氧化物层(非等离子体增强沉积),其随后是经掺杂(例如PSG)和等离子体沉积的氧化物(例如PETEOS)。
场氧化物432是用于功率器件的层场氧化物,其是厚沉积(在表面上)的氧化物(即不是硅的局部氧化(LOCOS))并且被湿法蚀刻给它非常接近于45°的倾斜以便维持平滑变化的电场。这对于功率器件是重要的,因为它从核心区(其中电场多半是垂直的)过渡到终止区(其中电场是水平和垂直的组合,多半是水平的)。
P+层433朝向二极管部分404中的外延硅410的顶部表面形成并且通过过孔428连接到金属426,所述P+层433具有在高E18 cm-3至低E20 cm-3的范围中的掺杂。界面435是P+层433与N掺杂外延层414之间的界面,其形成P-N结以创建硅结二极管。界面437是过孔429与N掺杂的N型外延层414之间的界面,其形成金属-半导体结以创建用于肖特基二极管的肖特基势垒。在附加的实施例中,器件402的二极管仅包括硅结二极管,仅包括肖特基二极管或硅结二极管和肖特基二极管的任何组合。
图5是半导体器件502的框图,其包括使用绝缘体上硅(SOI)技术形成的垂直功率器件504和混合信号表面器件508。在一个实施例中,垂直功率器件504由表面器件508控制,垂直功率器件504和表面器件508形成在外延硅510上并且通过绝缘体586分离。
垂直功率器件504包括一个或多个功率器件,其子集并联连接在一起以形成一个或多个功率器件,诸如SJMOSFET、IGBT、硅结二极管、肖特基二极管等等。垂直功率器件504连接在金属526与金属518之间,所述金属526和金属518可以均包括一个或多个金属层。功率在晶片的顶部表面或正侧上的金属526与晶片的底部表面或背侧上的金属518之间流过垂直功率器件504。
表面器件508是包括模拟电路和数字电路中的一个或多个的混合信号器件。表面器件508包括一个或多个MOS区,诸如MV NMOS区542、MV PMOS区544、LV NMOS区568和LVPMOS区569。每一个区包括一个或多个电路,其包括一个或多个晶体管,并且不同电路通过金属526互连。可替换的实施例可以具有形成在表面器件508中的任何数目或类型的电气组件,诸如晶体管、电阻器、电容器等等,以形成任何数目的数字或模拟组件,诸如模拟到数字转换器、数字到模拟转换器、逻辑门、存储器、处理器、状态机、EPROM、EEPROM、逻辑门等。
MV NMOS区542和MV PMOS区544操作在中等电压电平下,而LV NMOS区568和LVPMOS区569操作在低电压电平下。每一个区可选地通过绝缘体586与彼此分离。
由于外延硅510的部分不运载表面器件508以下的电流,因此外延硅510的该部分将具有比形成垂直功率器件504的外延硅510更低的温度。在某些实施例中,表面器件508的区在策略上被放置或散置在垂直器件区域周围或垂直器件区域内以便耗散来自垂直功率器件504的热量并且降低器件502的总体温度。
图6A是包括垂直SJMOSFET和表面器件608的器件602的截面视图,所述垂直SJMOSFET和表面器件608形成在体硅616上的外延硅610上并且通过绝缘体686分离。器件602是图5的器件502的实施例。处置晶片690在处置和处理期间支撑器件602。第一SJMOSFET部分604包括形成在外延硅610中的P型柱612。表面器件608包括MV NMOS区642、MV PMOS区644、LV NMOS区668和LV PMOS区669,其均通过绝缘体686分离。MV NMOS区642、MV PMOS区644、LV NMOS区668和LV PMOS区669不包括外延硅610内的P型柱。MV NMOS区642、MV PMOS区644、LV NMOS区668和LV PMOS区669均包括单个阱,其具有对于具体化在每一个相应区中的器件的类型而言所需要的半导体掺杂类型和浓度。
图6B是第一SJMOSFET部分604的截面视图。第一SJMOSFET部分604包括钝化层624、金属626、ILD 630、栅极638、P主体掺杂636、栅极氧化物634、P型柱612、N型外延层614、N+层616、金属618,并且被绝缘体686围绕。第一SJMOSFET部分604的形式和功能类似于图2A和2B的第一SJMOSFET部分204的形式和功能。绝缘体686将第一SJMOSFET部分604与作为器件602的部分的其他电路隔离和绝缘。
图6C是MV NMOS区642的截面。MV NMOS区642形成在外延硅610中的晶片的顶部表面处。MV NMOS区642被绝缘体686围绕以隔离形成在MV NMOS区642上和MV NMOS区642内的电气电路。MV NMOS区642使用中等电压电平并且包括晶体管646。MV P阱640不包括其他半导体掺杂类型和浓度的阱。MV P阱640的可替换的实施例可以包括其他半导体掺杂类型和浓度的阱。
晶体管646包括通过氧化物655与形成在外延硅610中的MV NMOS区642分离的栅极652。晶体管646包括由N++层657和N+层656形成的源极653。晶体管646包括由N++层659和N+层658形成的漏极654。
图6D是MV PMOS区644的截面。MV PMOS区644形成在外延硅610中的晶片的顶部表面处。MV PMOS区644被绝缘体686围绕以隔离形成在MV PMOS区644上和MV PMOS区644内的电气电路。MV PMOS区644使用中等电压电平并且包括晶体管648。MV N阱650不包括其他半导体类型和浓度的阱。MV N阱650的可替换实施例使用形成在MV N阱650内的其他半导体掺杂类型和浓度的阱。
晶体管648包括通过氧化物663与形成在外延硅610中的MV PMOS区644分离的栅极660。晶体管648包括由P++层665和P+层664形成的源极661。晶体管648包括由P++层665和P+层664形成的漏极662。
晶体管646的漏极654和晶体管648的漏极662通过金属626连接。在一个实施例中,晶体管646的栅极652和晶体管648的栅极660电气连接以形成CMOS反相器的输入,其中晶体管646的漏极654和晶体管648的漏极662形成CMOS反相器的输出。
图6E是LV NMOS区668的截面。LV NMOS区668形成在外延硅610中的晶片的顶部表面处。LV NMOS区668被绝缘体686围绕以隔离形成在LV NMOS区668上和LV NMOS区668内的电气电路。LV NMOS区668使用低电压电平并且包括晶体管670。LV P阱672不包括其他半导体掺杂类型和浓度的阱。LV P阱672的可替换的实施例可以包括其他半导体掺杂类型和浓度的阱。
晶体管670包括通过氧化物677与形成在外延硅610中的LV NMOS区668分离的栅极674。晶体管670包括由N++层678形成的源极675。晶体管670包括由N++层679形成的漏极676。
图6F是LV PMOS区669的截面。LV PMOS区669形成在外延硅610中的晶片的顶部表面处。LV PMOS区669被绝缘体686围绕以隔离形成在LV PMOS区669上和LV PMOS区669内的电气电路。LV PMOS区669使用低电压电平并且包括晶体管671。LV N阱673不包括其他半导体掺杂类型和浓度的阱。LV N阱670的可替换的实施例使用形成在LV N阱670内的其他半导体掺杂类型和浓度的阱。
晶体管671包括通过氧化物683与形成在外延硅610中的LV PMOS区669分离的栅极680。晶体管671包括由P++层685形成的源极681。晶体管671包括由P++层684形成的漏极682。为了清楚起见,未示出中间金属层和到栅极的接触。
晶体管670的漏极676和晶体管671的漏极682通过金属626连接。在一个实施例中,晶体管670的栅极674和晶体管671的栅极680电气连接以形成CMOS反相器的输入,其中晶体管670的漏极676和晶体管671的漏极682形成CMOS反相器的输出。
图7A是包括第一IGBT部分704和表面器件708的器件702的截面视图。器件702是图5的器件502的实施例并且与图6A的器件602的不同之处在于,图7A的实施例中的垂直功率器件是垂直功率IGBT,而图6A的实施例中的垂直功率器件是垂直功率SJMOSFET。处置晶片790在处置和处理期间支撑器件702。
表面器件708在形式和功率方面与图6A的表面器件608类似,并且包括MV NMOS区742、MV PMOS区744、LV NMOS区768和LV PMOS区769。MV NMOS区742、MV PMOS区744、LV NMOS区768和LV PMOS区769中的每一个被绝缘体786围绕。MV NMOS区742、MV PMOS区744、LVNMOS区768和LV PMOS区769中的每一个包括形成在外延硅710的顶部上的晶体管。在可替换的实施例中,均包括任何数目的电气组件的任何数目的MOS区组合以形成表面器件708,其可以用于控制一个或多个垂直功率器件。
图7B是器件702的垂直IGBT的截面视图。器件702的垂直IGBT是包括栅极738的沟槽栅极IGBT。为了清楚器件,未示出中间金属层和到栅极的接触。
金属726将IGBT部分704的发射极互连到其他电子电路,包括表面器件708。在可替换的实施例中,可以使用多级金属拓扑。多级金属拓扑可以将铝(Al)用于所有层,或者可以将Al用于最底部金属层,其与用于最顶部金属层的铜(Cu)组合,只要最顶部层足够厚(大约2-5微米[μm]厚)以处置器件702的IGBT的高功率要求。MV NMOS区742中的晶体管的源极通过金属726连接到器件702的IGBT的发射极。
过孔728利用钨(W)插头制作,所述钨(W)插头具有接触底部和用阻挡层诸如钛(Ti)、氮化钛(TiN)或其组合镶衬的侧壁。
ILD 730是外延硅710的顶部与金属726之间的电介质材料层。功率器件,诸如器件702的IGBT,典型地包括多个SiO2(氧化物)层,最靠近表面具有不带电的、未经掺杂的氧化物层(非等离子体增强沉积),其随后是经掺杂(例如PSG)和等离子体沉积的氧化物(例如PETEOS)。
栅极氧化物734将栅极738与晶片的外延硅710中的N型外延层714分离。
朝向IGBT部分704中的外延硅710的顶部表面形成P主体掺杂736。N++层731形成在P主体736内。
栅极738包括多晶硅并且施加于栅极738的电压控制在器件702的IGBT的发射极和集电极之间传递的电流的量。为了附图中的清楚性,未示出栅极接触件和控制。
P+层739与N+层316形成P-N结以形成第一IGBT部分704的集电极。
图8A是包括第一二极管部分804和表面器件808的器件802的截面视图。器件802是图5的器件502的实施例,并且与图6A的器件602的不同之处在于,图8A的实施例中的垂直功率器件是垂直功率二极管,而图6A的实施例中的垂直功率器件是垂直功率SJMOSFET。器件802被示出没有处置晶片。
表面器件808在形式和功能方面与图6A的表面器件608类似,并且包括MV NMOS区842、MV PMOS区844、LV NMOS区868和LV PMOS区869。MV NMOS区842、MV PMOS区844、LV NMOS区868和LV PMOS区869中的每一个被绝缘体886围绕。MV NMOS区842、MV PMOS区844、LVNMOS区868和LV PMOS区869中的每一个包括形成在外延硅810的顶部上的晶体管。在可替换的实施例中,均包括任何数目的电气组件的任何数目的MOS区组合以形成表面器件808,其可以用于控制一个或多个垂直功率器件。
图8B更加详细地示出二极管部分804的截面。
金属826将二极管部分804的阳极互连到表面器件802。在可替换的实施例中,金属826将二极管部分804的阳极互连到其他二极管部分的阳极。在其他可替换的实施例中,可以使用多级金属拓扑。多级金属拓扑可以将铝(Al)用于所有层,或者可以将Al用于最底部金属层,其与用于最顶部金属层的铜(Cu)组合,只要最顶部层足够厚(大约2-5微米[μm]厚)以处置器件802的二极管的高功率要求。
过孔828利用钨(W)插头制作,所述钨(W)插头具有接触底部和用阻挡层诸如钛(Ti)、氮化钛(TiN)或其组合镶衬的侧壁。
ILD 830是将金属826与器件802的电活性部分分离的电介质材料层。功率器件,诸如器件802的二极管,典型地包括多个SiO2(氧化物)层,最靠近表面具有不带电的、未经掺杂的氧化物层(非等离子体增强沉积),其随后是经掺杂(例如PSG)和等离子体沉积的氧化物(例如PETEOS)。
P+层833朝向二极管部分804中的外延硅810的顶部表面形成并且通过过孔828连接到金属826。界面835是P+层833与N掺杂外延层814之间的界面,其形成P-N结以创建硅结二极管。界面837是过孔829与N掺杂的N型外延层414之间的界面,其形成金属-半导体结以创建用于肖特基二极管的肖特基势垒。在附加的实施例中,器件802的二极管仅包括硅结二极管,仅包括肖特基二极管或硅结二极管和肖特基二极管的任何组合。
图9是包括具有混合信号表面器件的垂直功率器件的器件902的三维视图。器件902是图5的器件502的实施例。
SJMOSFET 904形成在具有P型柱912的外延硅910中。SJMOSFET 904的形式和功能类似于在图2A和图2B中描述的SJMOSFET的形式和功能。SJMOSFET 904的栅极包括并联连接的若干栅极,其中的一些被截短以为MV区920让出位置。SJMOSFET 904的漏极通过N+层916形成在底部或背侧上,所述N+层916连接到金属层918。
表面器件908包括MV区920,其包括由MV NMOS晶体管946和MV PMOS晶体管948形成的CMOS反相器。晶体管946的栅极952和栅极960晶体管948并联连接以形成到CMOS反相器的输入。晶体管946的漏极954和晶体管948的漏极962连接在一起以形成CMOS反相器的输出。晶体管946的源极953连接到SJMOSFET 904的并联连接的源极。晶体管948的源极961连接到电压VDD。
MV NMOS晶体管946形成在MV P阱940的内部。MV PMOS晶体管948形成在MV N阱950的内部,所述MV N阱950形成在MV P阱940中。
在本公开中呈现的实施例意图提供本发明的可实现的示例,但是不意图限制本发明。例如,除了硅之外的其他材料可以用作基底半导体材料。可以如所要求的那样采用针对N型和P型区的各种掺杂水平范围以及使用P型体硅或外延层(而不是N型)并且使掺杂类型相反以形成问候的器件,如本领域技术人员所认识到的。可以采用各种类型和厚度的氧化物材料。可以采用用于高电压器件的各种类型的栅极结构,其包括平面栅极和沟槽栅极二者。任一实施例的任何特征、元件或益处可以与其他实施例的特征、元件和益处组合。
Claims (21)
1.一种半导体器件,包括:
垂直功率器件,其沿半导体器件的垂直轴有电活性并且其具有在半导体器件的背表面上的至少一个主要电气端子;以及
表面器件,其包括沿半导体器件的顶部表面有电活性的一个或多个横向器件。
2.权利要求1所述的半导体器件:
其中垂直功率器件形成超级结金属氧化物半导体场效应晶体管(SJMOSFET)。
3.权利要求1所述的半导体器件:
其中垂直功率器件由超级结金属氧化物半导体场效应晶体管(SJMOSFET)和绝缘栅双极型晶体管(IGBT)组成。
4.权利要求1所述的半导体器件:
其中垂直功率器件由超级结金属氧化物半导体场效应晶体管(SJMOSFET)、绝缘栅双极型晶体管(IGBT)和功率二极管组成。
5.权利要求2所述的半导体器件:
其中所述一个或多个横向器件包括以下中的一个或多个:N型MOS(NMOS)晶体管、P型MOS(PMOS)晶体管、横向漂移MOS(LDMOS)晶体管、NPN双极型结型晶体管(NPN)、PNP双极型结型晶体管(PNP)、浮栅MOS晶体管、二极管、电阻器、电容器、电感器和可熔元件;并且
其中表面器件配置成控制垂直功率器件。
6.权利要求2所述的半导体器件:
其中所述一个或多个横向器件互连以形成以下中的一个或多个:可擦除可编程只读存储器(EPROM)、电可擦除可编程只读存储器(EEPROM)、状态机、模拟到数字转换器、数字到模拟转换器、栅极驱动器、温度传感器、逻辑门、处理器和任何其他混合模拟-数字电路构成物;并且,
其中表面器件配置成控制垂直功率器件。
7.权利要求5所述的半导体器件:
其中表面器件包括中等电压区和低电压区;
其中中等电压区包括NMOS区和PMOS区;
其中低电压区包括NMOS区和PMOS区。
8.权利要求1所述的半导体器件,还包括:
半导体器件的顶侧上的金属层;
其中金属层将垂直功率器件互连到表面器件。
9.权利要求1所述的半导体器件:
其中表面器件的部分关于垂直功率器件的部分散置以耗散来自垂直功率器件的热量并且降低半导体器件的总体温度。
10.权利要求8所述的半导体器件,还包括:
分离垂直功率器件与表面器件的绝缘体;并且,
其中半导体器件形成为绝缘体上硅器件并且绝缘体是氧化硅和氧化铝中的一个。
11.一种半导体器件,包括:
垂直功率器件,其沿半导体器件的垂直轴有电活性并且形成具有在半导体器件的背表面上的集电极端子的绝缘栅双极型晶体管(IGBT);以及
表面器件,其包括沿半导体器件的顶部表面有电活性的一个或多个横向器件。
12.权利要求11所述的半导体器件:
其中所述一个或多个横向器件包括以下中的一个或多个:N型MOS(NMOS)晶体管、P型MOS(PMOS)晶体管、横向漂移MOS(LDMOS)晶体管、NPN双极型结型晶体管(NPN)、PNP双极型结型晶体管(PNP)、浮栅MOS晶体管、二极管、电阻器、电容器、电感器和可熔元件;并且
其中表面器件配置成控制垂直功率器件。
13.权利要求11所述的半导体器件:
其中所述一个或多个横向器件互连以形成以下中的一个或多个:可擦除可编程只读存储器(EPROM)、电可擦除可编程只读存储器(EEPROM)、状态机、模拟到数字转换器、数字到模拟转换器、栅极驱动器、温度传感器、逻辑门、处理器和任何其他混合模拟-数字电路构成物;并且,
其中表面器件配置成控制垂直功率器件。
14.权利要求11所述的半导体器件:
其中表面器件包括中等电压区和低电压区;
其中中等电压区包括NMOS区和PMOS区;
其中低电压区包括NMOS区和PMOS区。
15.权利要求11所述的半导体器件,还包括:
半导体器件的顶侧上的金属层;
其中金属层将垂直功率器件互连到表面器件。
16.权利要求11所述的半导体器件:
其中表面器件的部分关于垂直功率器件的部分散置以耗散来自垂直功率器件的热量并且降低半导体器件的总体温度。
17.权利要求11所述的半导体器件,还包括:
分离垂直功率器件与表面器件的绝缘体;并且,
其中半导体器件形成为绝缘体上硅器件并且绝缘体是氧化硅和氧化铝中的一个。
18.一种半导体器件,包括:
垂直功率器件,其沿半导体器件的垂直轴有电活性并且形成具有在半导体器件的背表面上的阴极端子的二极管;以及
表面器件,其包括沿半导体器件的顶部表面有电活性的一个或多个横向器件。
19.权利要求18所述的半导体器件:
其中所述一个或多个横向器件包括以下中的一个或多个:N型MOS(NMOS)晶体管、P型MOS(PMOS)晶体管、横向漂移MOS(LDMOS)晶体管、NPN双极型结型晶体管(NPN)、PNP双极型结型晶体管(PNP)、浮栅MOS晶体管、二极管、电阻器、电容器、电感器和可熔元件;
其中所述一个或多个横向器件互连以形成以下中的一个或多个:可擦除可编程只读存储器(EPROM)、电可擦除可编程只读存储器(EEPROM)、状态机、模拟到数字转换器、数字到模拟转换器、栅极驱动器、温度传感器、逻辑门、处理器和任何其他混合模拟-数字电路构成物;并且,
其中表面器件配置成控制垂直功率器件。
20.权利要求18所述的半导体器件:
其中表面器件包括中等电压区和低电压区;
其中中等电压区包括NMOS区和PMOS区;
其中低电压区包括NMOS区和PMOS区。
21.权利要求18所述的半导体器件,还包括:
分离垂直功率器件与表面器件的绝缘体;并且,
其中半导体器件形成为绝缘体上硅器件并且绝缘体是氧化硅和氧化铝中的一个。
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TWI826190B (zh) * | 2022-12-16 | 2023-12-11 | 力晶積成電子製造股份有限公司 | 高頻電晶體 |
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EP3262678A1 (en) | 2018-01-03 |
US20180012981A1 (en) | 2018-01-11 |
US9755058B2 (en) | 2017-09-05 |
US20160254373A1 (en) | 2016-09-01 |
KR20170121224A (ko) | 2017-11-01 |
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