CN107644604A

CN107644604A - Display device

Info

Publication number: CN107644604A
Application number: CN201610580827.3A
Authority: CN
Inventors: 简廷宪; 高宏成; 林松君; 詹建廷
Original assignee: Hannstar Display Corp
Current assignee: Hannstar Display Corp
Priority date: 2016-07-22
Filing date: 2016-07-22
Publication date: 2018-01-30
Anticipated expiration: 2036-07-22
Also published as: CN107644604B

Abstract

The invention discloses a kind of display device, and it has viewing area and neighboring area.There are multiple first grid polar curves and second gate line being staggered in viewing area.There are multiple first shift register circuits and multiple second shift register circuits in neighboring area.Each first shift register circuit according at least one clock signal to produce and provide the first scanning signal to corresponding first grid polar curve, and each second shift register circuit according at least one clock signal producing and provide the second scanning signal to corresponding second gate line.For the first shift register circuit and the second shift register circuit of peer, the high potential duration of the first scanning signal is identical with the high potential duration of the second scanning signal, and the first scanning signal differs 1/4 clock cycle with the second scanning signal.Display device of the present invention at least has high-res, narrow frame, high display quality and low manufacture cost and other advantages.

Description

Display device

Technical field

The present invention relates to a kind of display device, and more particularly to a kind of display device of bilateral turntable driving.

Background technology

With the continuous progress of electronic technology, existing miscellaneous portable type electronic product comes out, as intelligent mobile phone, GPS navigation machine etc..These portable type electronic products generally have display device, and the image of display device is shown need to pass through driving Circuit controls, and the setting of this drive circuit causes the increase of sized display.How to design one kind has high display quality And beneficial to lightening one of the display device, the target endeavoured by relevant industry technical staff of portable electronic product.

The content of the invention

The purpose of the present invention is to be to provide a kind of display device, and it at least has high-res, narrow frame, high display product Matter and low manufacture cost and other advantages.

According to the above-mentioned purpose of the present invention, propose a kind of display device, its have viewing area and neighboring area and comprising Multiple pixel cells, N bar first grid polar curves and N bars second gate line, the first drive circuit and the second drive circuit.These pixels Unit is arranged in viewing area and is arranged as multiple pixel columns and multiple pixel columns.These N bar first grid polar curves and these N bars Second gate line is staggered in viewing area, and wherein these pixel columns (row) are coupled to these first grid polar curves wherein One of and one of these second gate lines.First drive circuit is arranged in neighboring area, when it includes the 1st to the 4th Clock signal wire and the 1st grade are to the shift register circuit of N levels first.1st to the 4th clock cable respectively to provide the 1st to 4th clock signal, and these first shift register circuits are respectively at least clock in the 1st to the 4th clock signal Signal produces and provides the 1st grade to the scanning signal of N levels first to these first grid polar curves.Second drive circuit is arranged at periphery In region, it includes the 5th to the 8th clock cable and the 1st grade to the shift register circuit of N levels second.5th to the 8th clock Signal wire is respectively to provide the 5th to the 8th clock signal, and these second shift register circuits are respectively to according to the 5th to the 8th At least one clock signal in clock signal produces and provides the 1st grade to the scanning signal of N levels second to the second grid Line.The clock cycle length of 1st to the 8th clock signal is identical, and (j+4) clock signal in the 1st to the 8th clock signal with Jth clock signal in 1st to the 8th clock signal differs 1/4 clock cycle, and i-th in these first scanning signals The high potential duration of the first scanning signal of level and the high potential of the scanning signal of i-stage second in these second scanning signals Duration is identical, the scanning signal of i-stage first in these first scanning signals and the i-stage in these second scanning signals Second scanning signal differs 1/4 clock cycle, and wherein N is the positive integer more than or equal to 2, and j is more than or equal to 1 and is less than Or the positive integer equal to 4, and i is any positive integer in 1 to N.

It is non-rectangle according to one embodiment of the invention, being shaped as above-mentioned viewing area.

According to another embodiment of the present invention, the shift register circuit of i-stage first in first shift register circuit Or the shift register circuit of i-stage second in second shift register circuit includes precharge unit and output unit.Preliminary filling Electric unit couples first node and to by first node output control signal.Output unit is used to receive control signal To export in the scanning signal of i-stage first or second scanning signal in first scanning signal by section point The scanning signal of i levels second.

According to another embodiment of the present invention, the control signal of the above-mentioned shift register circuit of i-stage first is at the 1st time point Second current potential is changed into by the first current potential, the 3rd current potential is changed into by the second current potential at the 3rd time point, at the 5th time point by Three current potentials are changed into the 4th current potential, and are changed into first current potential by the 4th current potential at the 7th time point, wherein the 3rd current potential Potential value is more than the potential value of the second current potential and the potential value of the 4th current potential, and the electricity of the potential value of the second current potential and the 4th current potential Place value is all higher than the potential value of the first current potential.The control signal of the above-mentioned shift register circuit of i-stage second is at the 2nd time point by One current potential is changed into the second current potential, is changed into the 3rd current potential by the second current potential at the 4th time point, at the 6th time point by the 3rd electricity Position is changed into the 4th current potential, and is changed into the first current potential by the 4th current potential at the 8th time point.The of described 1st to the 8th time point (m+1) time point falls behind 1/4 clock cycle of m time points at the 1st to the 8th time point, and m is in 1,3,5 and 7 Any positive integer.

According to another embodiment of the present invention, the potential value phase of the potential value of above-mentioned second current potential and the 4th current potential Deng.

According to another embodiment of the present invention, the above-mentioned scanning signal of i-stage first is by low potential at above-mentioned 3rd time point Be converted to high potential and low potential is converted to by high potential at above-mentioned 5th time point, and the scanning signal of above-mentioned i-stage second is High potential is converted to by low potential at above-mentioned 4th time point and low potential is converted to by high potential at above-mentioned 6th time point.

According to another embodiment of the present invention, the time difference at above-mentioned 5th time point and above-mentioned 7th time point is at least 1/2 The individual clock cycle, and the time difference at above-mentioned 6th time point and above-mentioned 8th time point is at least 1/2 clock cycle.

According to another embodiment of the present invention, the time difference at above-mentioned 1st time point and above-mentioned 7th time point is at least 3/2 The individual clock cycle, and the time difference at above-mentioned 2nd time point and above-mentioned 8th time point is at least 3/2 clock cycle.

According to another embodiment of the present invention, above-mentioned first drive circuit is to be separately positioned on above-mentioned second drive circuit The opposite sides of viewing area.

According to another embodiment of the present invention, each pixel cell in these above-mentioned pixel cells includes at least one thin Film transistor, above-mentioned first drive circuit include multiple thin film transistor (TFT)s, and above-mentioned first respectively with above-mentioned second drive circuit The thin film transistor (TFT) of the thin film transistor (TFT) and these above-mentioned pixel cells of drive circuit and above-mentioned second drive circuit is to set jointly Put on substrate.

According to another embodiment of the present invention, the thin film transistor (TFT) of above-mentioned first drive circuit and above-mentioned second drive circuit Thin film transistor (TFT) with the pixel cell is amorphous silicon film transistor.

According to another embodiment of the present invention, high potential of above-mentioned 1st to the 8th clock signal within a clock cycle is held The continuous time is respectively 1/2 clock cycle, and (k+1) clock signal in above-mentioned 1st to the 4th clock signal is believed with kth clock Number 1/2 clock cycle of difference, and (k+5) clock signal in above-mentioned 5th to the 8th clock signal and (k+4) clock are believed Number difference 1/2 clock cycle, wherein k be more than or equal to 1 and less than or equal to 3 positive integer.

According to another embodiment of the present invention, above-mentioned 1st grade to the i-stage first in the scanning signal of N levels first scans Signal and the above-mentioned 1st grade of high potential duration to the scanning signal of i-stage second in the scanning signal of N levels second be respectively 1/2 clock cycle, and the height during the high potential of the scanning signal of above-mentioned i-stage first with the above-mentioned scanning signal of i-stage second It is 1/4 clock cycle that overlaps in sequential during current potential.

According to another embodiment of the present invention, above-mentioned precharge unit is believed to receive the first input signal and the second input Number, above-mentioned output unit receives the 4th input signal, the shift register circuit of i-stage first in above-mentioned first shift register circuit Or the shift register circuit of i-stage second in second shift register circuit is also single comprising the first drop-down unit and the second drop-down Member.First drop-down unit couples first node and to receive the 3rd input signal.Second drop-down unit couple section point and To receive the 5th input signal.The 4th input signal and the 5th input signal of the above-mentioned shift register circuit of i-stage first point Not Wei the 1st to the 4th clock signal two of which, and above-mentioned 3rd input signal be these first scanning signals in (i+ 2) scanning signal of level first or the first reset signal.The 4th input signal and the 5th of the above-mentioned shift register circuit of i-stage second Input signal is respectively the two of which of the 5th to the 8th clock signal, and above-mentioned 3rd input signal is these second scanning signals In the second scanning signal of (i+2) level or the second reset signal.

According to another embodiment of the present invention, n is the positive integer less than or equal to N and the multiple for being 4.When i is (n-3) When, the 4th input signal of the above-mentioned shift register circuit of i-stage first is the 1st clock signal, and the displacement of above-mentioned i-stage second is posted The 4th input signal for depositing circuit is the 5th clock signal.When i is (n-2), the of the above-mentioned shift register circuit of i-stage first Four input signals are the 2nd clock signal, and the 4th input signal of the shift register circuit of above-mentioned i-stage second is believed for the 6th clock Number.When i is (n-1), the 4th input signal of the above-mentioned shift register circuit of i-stage first is the 3rd clock signal, and above-mentioned 4th input signal of the shift register circuit of i levels second is the 7th clock signal.When i is n, the above-mentioned shift LD of i-stage first 4th input signal of circuit is the 4th clock signal, and the 4th input signal of the shift register circuit of above-mentioned i-stage second is the 8 clock signals.

According to another embodiment of the present invention, when i is 1, the first input letter of the above-mentioned shift register circuit of i-stage first Number be all the first commencing signal with the second input signal, and the first input signal of the shift register circuit of above-mentioned i-stage second and Second input signal is all the second commencing signal.When i is 2, the first input signal of the above-mentioned shift register circuit of i-stage first It is respectively the first scanning signal of (i-1) level and the first commencing signal in these first scanning signals with the second input signal, And the first input signal of the above-mentioned shift register circuit of i-stage second and the second input signal are respectively these second scanning signals In the second scanning signal of (i-1) level and the second commencing signal.When i is 3 to N any positive integer, above-mentioned i-stage first The first input signal and the second input signal of shift register circuit are respectively (i-1) level in these first scanning signals The first scanning signal of scan signal and (i-2) level, the first input signal and second of the shift register circuit of i-stage first Input signal is respectively the second scanning signal of (i-1) level and the scanning letter of (i-2) level second in these second scanning signals Number.

According to another embodiment of the present invention, above-mentioned precharge unit includes the first transistor and second transistor.First The first end of transistor and the 3rd end are receiving above-mentioned first input signal.The first end of second transistor and the 3rd end to Receive above-mentioned second input signal.Above-mentioned first drop-down unit includes third transistor.3rd end of third transistor is connecing Above-mentioned 3rd input signal is received, and the first end of the third transistor couples above-mentioned first node.Above-mentioned output unit includes the Four transistors and electric capacity.3rd end of the 4th transistor couples above-mentioned first node, and the first end of the 4th transistor is receiving Above-mentioned 4th input signal, and the second end of the 4th transistor couples above-mentioned section point.Electric capacity couples the of the 4th transistor Three ends and the second end.

Compared with prior art, the present invention has the advantages that：The display device of the present invention at least has high parsing Degree, narrow frame, high display quality and low manufacture cost and other advantages.

Brief description of the drawings

In order to more completely understand embodiment and its advantage, description below is done referring now to reference to accompanying drawing mode, wherein：

Fig. 1 is the schematic diagram of the display device according to the embodiment of the present invention；

Fig. 2A and Fig. 2 B are respectively the schematic diagram according to the pixel cell in Fig. 1 of some embodiments viewing area；

Fig. 3 is that the coupling relation of the element and gate line and data line in the pixel cell in Fig. 1 viewing area is shown It is intended to；

Fig. 4 is the schematic diagram of the display device according to another embodiment of the present invention；

Fig. 5 is the schematic diagram of the known display device with non-rectangle viewing area；

Fig. 6 is according to the first drive circuit of the embodiment of the present invention and the schematic diagram of the second drive circuit；

Fig. 7 A and Fig. 7 B are the block diagram of the shift register circuit according to some embodiments of the invention；

Fig. 8 A and Fig. 8 B are the equivalent circuit diagram of the shift register circuit according to some embodiments of the invention；

And

Fig. 9 A to Fig. 9 C are the timing diagram of Fig. 6 the first drive circuit and the second drive circuit in a picture frame cycle.

Embodiment

Embodiments of the invention are hashed out below.It is understood, however, that embodiment offer is many applicable general Read, it may be implemented in miscellaneous certain content.Discuss, embodiments of the disclosure only for explanation, is not limited to this The scope of invention.

Fig. 1 is the schematic diagram of the display device 100 according to the embodiment of the present invention.Display device 100 can for example be reversed Nematic (twisted nematic；TN) type, horizontal handoff (in-plane switching；IPS) type, fringe field switching (fringe-field switching；FFS) type or vertical orientation (vertical alignment；VA) type etc. is various types of Liquid crystal display panel, or Organic Light Emitting Diode (organic light emitting diode；OLED) display panel, but Not limited to this.Display device 100 has viewing area 110, and has multiple pixels in viewing area 110, its jointly to Display image.It is outer (i.e. positioned at peripheral region that source electrode drive circuit 122 and gate driving circuit 124A, 124B are located at viewing area 110 In domain 120) opposite sides.Source electrode drive circuit 122 drives source electrode view data is converted into source drive signal Dynamic signal is transmitted to the pixel in viewing area 110.Gate driving circuit 124A, 124B to produce gate drive signal, and Gate drive signal is transmitted to transmitting to the pixel in viewing area 110.Pixel in viewing area 110 is by source drive The driving of signal and gate drive signal and common display image.

Fig. 2A is the schematic diagram of the pixel cell in Fig. 1 viewing area 110.As shown in Figure 2 A, in viewing area 110 Multiple pixel cell P (1,1)~P (M, N) is provided with, these pixel cells P is arranged in N number of pixel column (row) R (1)~R (N) With M pixel column (column) C (1)~C (M).In addition, multiple first grid polar curve GA (1) are also provided with viewing area 110 ~GA (N), multiple second gate line GB (1)~GB (N) and multiple data line D (1)~D (L).Embodiment depicted in Fig. 2A is Using bigrid (dual gate) design, that is to say, that these pixel columns R (1)~R (N) each pixel column is corresponding to be coupled In a first grid polar curve and these second gate lines GB (1)~GB (N) in these first grid polar curves GA (1)~GA (N) One second gate line, wherein two adjacent pixel cells in same pixel column are respectively coupled to this corresponding pixel column First grid polar curve and second gate line, and these pixel columns C (1)~C (M) two adjacent pixel columns couple these data wires A data wire in D (1)~D (L).As shown in Figure 2 A, pixel column R (i) couples first grid polar curve GA (i) and second gate line GB (i), pixel column C (j-1), C (j) coupling data wire D (j/2), and pixel cell P (j-1, i), P in pixel column R (i) (j, i) is respectively coupled to first grid polar curve GA (i) and second gate line GB (i), and wherein i is the positive integer less than or equal to N, and j For the even number more than or equal to 2 and less than or equal to M.In other embodiments, as shown in Figure 2 B, the picture in pixel column R (i) Plain unit P (j-1, i), P (j, i) are respectively coupled to second gate line GB (i) and first grid polar curve GA (i).

Fig. 3 is in pixel cell P (1,1)~P (M, N) in the viewing area 110 according to some embodiments of the invention The coupling of element and first grid polar curve GA (1)~GA (N), second gate line GB (1)~GB (N) and data wire D (1)~D (L) Relation schematic diagram, its corresponding pixel cell arrangement mode to Fig. 2 B.Each pixel cell P (1,1)~P (M, N) includes film The transistor T and pixel electrode PE with this thin film transistor (TFT) T couplings, wherein thin film transistor (TFT) T grid G couple these first One second in a first grid polar curve or these second gate lines GB (1)~GB (N) in gate lines G A (1)~GA (N) Gate line, thin film transistor (TFT) T source S couple a data wire in these data wires D (1)~D (L), and thin film transistor (TFT) T Drain D coupling pixel electrode PE.As shown in figure 3, if j is odd number, the grid of the thin film transistor (TFT) T in pixel cell P (j, i) Pole G and source S are respectively coupled to second gate line GB (i) and data wire D ((j+1)/2)；If j is even number, pixel cell P (j, I) grid G and source S of the thin film transistor (TFT) T in is respectively coupled to first grid polar curve GA (i) and data wire D (j/2).With pixel list Exemplified by first P (1, N), the grid G and source S of the thin film transistor (TFT) T in pixel cell P (1, N) are respectively coupled to second gate line GB (N) and data wire D (1).Similarly, other correspondences are into the embodiment of Fig. 2A pixel cell arrangement mode, if j is strange Number, then the grid G of the thin film transistor (TFT) T in pixel cell P (j, i) and source S are respectively coupled to first grid polar curve GA (i) and data Line D ((j+1)/2)；If j is even number, the grid G and source S of the thin film transistor (TFT) T in pixel cell P (j, i) are respectively coupled to Second gate line GB (i) and data wire D (j/2).

Next Fig. 4 is refer to, Fig. 4 is the schematic diagram of the display device 200 according to another embodiment of the present invention.Such as Fig. 4 Shown, display device 200 has viewing area 210 and neighboring area 220, has multiple pixel cells in viewing area 210 P, source electrode drive circuit 222 are located at the bottom side of viewing area 210 outer (i.e. in neighboring area 220), and gate driving circuit 224A, 224B are respectively positioned at the left and right sides of viewing area 210 outer (i.e. in neighboring area 220).In viewing area 210 Pixel cell P is arranged as N rows pixel column and M row pixel columns, and gate lines G A (1)~GA (N) and GB (1)~GB (N) are electrical respectively Gate driving circuit 224A, 224B are connected to, data wire D (1)~D (L) is electrically connected to source electrode drive circuit 222, wherein L etc. In M/2.Fig. 4 and Fig. 1 difference is, Fig. 1 viewing area 110 is shaped as rectangle, and the shape of Fig. 4 viewing area 210 Shape is non-rectangle (or being abnormity).In the fig. 4 embodiment, the shape of viewing area 210 is circular, and in other embodiments In, the shape of non-rectangle viewing area can be ellipse, triangle, heart or other irregular shapes, but the present invention The shape of non-rectangle viewing area is not limited with above-mentioned.Pixel cell number in each pixel column and pixel column can be according to display The shape in region 210 and corresponding change.It is similar with Fig. 2A, Fig. 2 B and Fig. 3, the pixel cell configuration and use of Fig. 4 embodiments The design of bigrid (dual gate), its related description refer to Fig. 2A, Fig. 2 B and Fig. 3 explanation, repeated no more in this.

It should be noted that the present invention especially has two grid design applied to the display device of non-rectangle viewing area Advantage.Referring to the schematic diagram that Fig. 4 and Fig. 5, Fig. 5 are the known display device 300 with non-rectangle viewing area.Display Device 300 has viewing area 310 and neighboring area 320, has multiple pixel cell P, source drive in viewing area 310 Circuit 322 is located at the bottom side of viewing area 310 outer (i.e. in neighboring area 320), and gate driving circuit 324A, 324B divide Not Wei Yu viewing area 310 outer (i.e. in neighboring area 320) opposite sides.Pixel cell P rows in viewing area 310 N rows pixel column and M row pixel columns are classified as, gate lines G L (1)~GL (N) is electrically connected to gate driving circuit 324A, 324B, number Source electrode drive circuit 322 is electrically connected to according to line DL (1)~DL (M).Fig. 5 and Fig. 4 difference is Fig. 5 pixel cell, grid The coupling mode of polar curve and data wire is known, and each pixel column is respectively coupled to a gate line and one with each pixel column Data line (such as the first row pixel cell coupling gate lines G L (1), the second row pixel cell coupling gate lines G L (2) ... etc., And first row pixel cell coupling data wire DL (1), secondary series pixel cell coupling data wire DL (2) ... etc.), and Fig. 4 is to adopt With dual gate design, that is, adjacent pixel column shares a data line (such as first row pixel cell and secondary series pixel Unit coupling data wire D (1), the 3rd row pixel cell and the 4th row pixel cell coupling data wire D (2) ... etc.), and each picture Two gate lines of plain row coupling (such as the first row pixel cell coupling gate lines G A (1) and GB (1), the second row pixel cell coupling Meet gate lines G A (2) and GB (2) ... etc.), therefore to same pixel number of unit, same pixel number of lines and same pixel For the display device 200 and 300 of column number, the data wire number of Fig. 5 embodiments is the two of the data wire number of Fig. 4 embodiments Times, and the gate line number of Fig. 4 embodiments is twice of the gate line number of Fig. 5 embodiments.As shown in figure 5, because Fig. 5 is implemented The data wire number of example is twice of the data wire number of Fig. 4 embodiments, in order to which data wire DL (1)~DL (M) is extended into source Pole drive circuit 322 and source electrode drive circuit 322 is electrically connected with, the data wire DL (1) in neighboring area 320~DL (M) sections It need to be reduced away from (pitch) make it that Fig. 5 frame (border) area is identical with the frame area of Fig. 4 embodiments, that is, week The spacing (spacing) in data-line width (width) and/or adjacent data line in border area domain 320 needs to reduce, therefore can lead Data wire DL (1)~DL (M) easily open circuit or short circuits in neighboring area 320 is caused, reduces the yield of display device 300 and reliable Degree.

In addition, because the pitch of data wire is relevant with the ability of board with processing procedure and have its limiting value, therefore work as panel During resolution increase, the number of data wire increases therewith, and frame area need to be increased with accommodating more data line, or neighboring area Data wire in 320 need to use multiple layer metal processing procedure to reduce the pitch of data wire, therefore lead to not the need for reaching narrow frame Ask or manufacturing cost increases.Fig. 4 of the present invention embodiment is reviewed, the data wire number of Fig. 4 embodiments is only Fig. 5 embodiments The half of data wire number.Therefore, compared to the known display device with non-rectangle viewing area, the present invention can be with relatively low Manufacturing cost completes tool narrow frame advantage and the display device with non-rectangle viewing area.

Fig. 6 is the schematic diagram of the first drive circuit 400A and the second drive circuit 400B according to the embodiment of the present invention.The One drive circuit 400A and the second drive circuit 400B suitable for Fig. 1 display device 100, Fig. 4 display device 200 or its Its similar display device.Illustrate exemplified by being used in Fig. 1 display device 100 to be arranged at below.First drive circuit 400A It is respectively Fig. 1 gate driving circuit 124A, 124B with the second drive circuit 400B, wherein when the first drive circuit 400A is included Clock signal wire L1~L4, commencing signal line SL1, reset signal line RL1 and the 1st grade to the first shift register circuit of N levels 410A (1)~410A (N), and the second drive circuit 400B includes clock cable L5~L8, commencing signal line SL2, reset signal line RL2 and the 1st grade to N levels the second shift register circuit 410B (1)~410B (N), wherein N is the positive integer more than or equal to 6. In certain embodiments, N is 4 plural multiple.

Clock cable L1~L8 is providing clock signal C1~C8 to corresponding first shift register circuit 410A (1) ~410A (N) or the second shift register circuit 410B (1)~410B (N).For example, for the first shift register circuit 410A (1) for~410A (N), clock cable L1 and L3 are coupled to the 1st grade of first shift register circuit 410A (1), clock signal Line L2 and L4 are coupled to the 2nd grade of first shift register circuit 410A (2) ... clock cable L3 and L1 and are coupled to (N-1) level One shift register circuit 410A (N-1), and clock cable L4 and L2 are coupled to the first shift register circuit of (N-1) level 410A (N).Similarly, for the second shift register circuit 410B (1)~410B (N), clock cable L5 and L7 are coupled to the 1st The second shift register circuit 410B (1) of level, clock cable L6 and L8 are coupled to the 2nd grade of second shift register circuit 410B (2) ... clock cable L7 and L5 is coupled to (N-1) level the second shift register circuit 410B (N-1), and clock cable L8 And L6 is coupled to N levels the second shift register circuit 410B (N).

In addition, commencing signal line SL1 provides commencing signal STV1 to the 1st, 2, the first shift register circuit of 4~N levels 410A (1), 410A (2), 410A (4)~410A (N), commencing signal line SL2 provide commencing signal STV2 to the 1st, 2,4~N levels second Shift register circuit 410B (1), 410B (2), 410B (4)~410B (N), reset signal line RL1 provide reset signal RST1 extremely (N-1), N levels the first shift register circuit 410A (N-1), 410A (N), and reset signal line RL2 provides reset signal RST2 To (N-1), N levels the second shift register circuit 410B (N-1), 410B (N).

1st grade to N levels the first shift register circuit 410A (1)~410A (N) respectively producing the 1st grade to N levels First scanning signal SA (1)~SA (N) and the 1st grade of output is to N levels the first scanning signal SA (1)~SA (N) to first grid Line GA (1)~GA (N), and the 1st grade to N levels the second shift register circuit 410B (1)~410B (N) respectively producing the 1st Level to N levels the second scanning signal SB (1)~SB (N) and output the 1st grade to N levels the second scanning signal SB (1)~SB (N) extremely Second gate line GB (1)~GB (N).1st grade of first shift register circuit 410A (1) also exports the 1st grade of first scanning signal SA (1) it is also defeated to the 2nd, 3 grade of first shift register circuit 410A (2), 410A (3), the 2nd grade of first shift register circuit 410A (2) Go out the 2nd grade of first scanning signal SA (2) to the 3rd, 4 grade of first shift register circuit 410A (3), 410A (4), (N-1) level One shift register circuit 410A (N-1) also exports (N-1) level the first scanning signal SA (N-1) and moved to (N-3), N levels first Position register circuit 410A (N-3), 410A (N), N levels the first shift register circuit 410A (N) also export the scanning letter of N levels first Number SA (N) to (N-2) level the first shift register circuit 410A (N-2), and the shift register circuit 410A (i) of i-stage first is also Export the scanning signal SA (i) of i-stage first to (i-2), (i+1), (i+2) level the first shift register circuit 410A (i-2), 410A (i+1), 410A (i+2), wherein i are the positive integer more than or equal to 3 and less than or equal to (N-2).For example, the 3rd The first shift register circuit 410A (3) of level more exports 3rd level the first scanning signal SA (3) to the 1st, 4,5 grades of the first shift LD Circuit 410A (1), 410A (4), 410A (5).

Similarly, the 1st grade of second shift register circuit 410B (1) also export the 1st grade of second scanning signal SB (1) to the 2nd, 3 grade of second shift register circuit 410B (2), 410B (3), the 2nd grade of second shift register circuit 410B (2) also export the 2nd grade Two scanning signal SB (2) to the 3rd, 4 grade of second shift register circuit 410B (3), 410B (4), the second shift LD of (N-1) level Circuit 410B (N-1) also exports (N-1) level the second scanning signal SB (N-1) to (N-3), the shift register circuit of N levels second 410B (N-3), 410B (N), N levels the second shift register circuit 410B (N) also export N levels the second scanning signal SB (N) extremely (N-2) level the second shift register circuit 410B (N-2), and the shift register circuit 410B (i) of i-stage second also exports i-stage Second scanning signal SB (i) to (i-2), (i+1), (i+2) level the second shift register circuit 410B (i-2), 410B (i+1), 410B (i+2), wherein i are the positive integer more than or equal to 3 and less than or equal to (N-2).

Fig. 7 A are the block diagram of the shift register circuit 500A according to some embodiments of the invention.For example, displacement is posted Depositing circuit 500A block diagram can correspond to Fig. 6 the 1st~3 grade of first shift register circuit 410A (1)~410A (3) and the 1st Any shift register circuit in~3 grade of second shift register circuit 410B (1)~410B (3).Shift register circuit 500A bags Include precharge unit 510A, the first drop-down unit 520A, output unit 530A and the second drop-down unit 540A.Precharge unit 510A is receiving input signal IN1~IN2 and by the output control signal CTRL of nodes X 1.First drop-down unit 520A couplings are pre- Charhing unit 510A, it is receiving input signal IN3 and pull-down node X1 current potential.Output unit 530A coupling precharge is single First 510A, it is receiving control signal CTRL and input signal IN4 and export scanning signal OUT by nodes X 2.Second drop-down Unit 540A couples the first drop-down unit 520A and output unit 530A, and it believes to receive input signal IN5 and reset scanning Number OUT.

Next Fig. 7 B are referred to, Fig. 7 B are the square of the shift register circuit 500B according to some embodiments of the invention Figure.For example, shift register circuit 500B block diagram can be corresponded to Fig. 6 the first shift register circuit of 4~N levels 410A (4) any shift register circuit in~410A (N) and 4~N levels the second shift register circuit 410B (4)~410B (N). Shift register circuit 500B includes precharge unit 510B, the first drop-down unit 520B, the drop-down lists of output unit 530B and second First 540B.Fig. 7 B shift register circuit 500B and Fig. 7 A shift register circuit 500A difference are shift register circuit 500B the first drop-down unit 520B also receives input signal IN6 in addition to receiving input signal IN3.Remainder is posted with displacement It is similar to deposit circuit 500A, is repeated no more in this.

Fig. 8 A illustrate the equivalent circuit diagram of the shift register circuit 600A according to some embodiments of the invention.Shift LD electricity Road 600A is shift register circuit 500A one of which embodiment, and it can be the 1st~3 grade of the first shift register circuit Any shift LD electricity in 410A (1)~410A (3) and the 1st~3 grade of second shift register circuit 410B (1)~410B (3) Road.Shift register circuit 600A includes precharge unit 610A, the first drop-down unit 620A, the drop-downs of output unit 630A and second Unit 640A, it distinguishes corresponding displaced register circuit 500A precharge unit 510A, the first drop-down unit 520A, output unit 530A and the second drop-down unit 540A.

Precharge unit 610A includes transistor T1, T2.Transistor T1 first end be coupled to the 3rd end together with simultaneously And input signal IN1 is received, and transistor T1 the second end couple nodes X1.Transistor T2 the 3rd end and first end receive defeated Enter signal IN2, and transistor T2 the second end couple nodes X1.It should be noted that in this manual, the first end of transistor It is respectively then to drain with source electrode or respectively source electrode with draining with the second end, first end and second when it is according to transistor operation The voltage at end determines, and the 3rd end of transistor is the grid of transistor.

First drop-down unit 620A includes transistor T3.Transistor T3 the 3rd end receives input signal IN3, transistor T3 First end receive reference potential Vss, and transistor T3 the second end couple nodes X1.

Output unit 630A includes electric capacity Cx and transistor T4, T5.Electric capacity Cx first end and the second end are respectively coupled to save Point X1 and nodes X 2.Transistor T4 the 3rd end couple nodes X1, transistor T4 first end receive input signal IN4, and brilliant Body pipe T4 the second end couple nodes X2.Transistor T5 the 3rd end and the second end couple nodes X2, and the first of transistor T5 End receives input signal IN4.

Second drop-down unit 640A includes transistor T6.Transistor T3 the 3rd end receives input signal IN5, transistor T3 First end receive reference potential Vss, and transistor T3 the second end couple nodes X2.

If shift register circuit 600A is the 1st grade of first shift register circuit 410A (1), IN1~IN5 points of input signal Wei not commencing signal STV1, commencing signal STV1,3rd level the first scanning signal SA (3), clock signal C1 and clock signal C3. If shift register circuit 600A is the 2nd grade of first shift register circuit 410A (2), input signal IN1~IN5 is respectively the 1st The first scanning signal SA (1) of level, commencing signal STV1, the 4th grade of first scanning signal SA (4), clock signal C2 and clock signal C4.If shift register circuit 600A is 3rd level the first shift register circuit 410A (3), input signal IN1~IN5 is respectively 2nd grade of first scanning signal SA (2), the 1st grade of first scanning signal SA (1), the 5th grade of first scanning signal SA (5), clock signal C3 and clock signal C1.

Similarly, if shift register circuit 600A is the 1st grade of second shift register circuit 410B (1), input signal IN1 ~IN5 is respectively commencing signal STV2, commencing signal STV2,3rd level the second scanning signal SB (3), clock signal C5 and clock Signal C7.If shift register circuit 600A is the 2nd grade of second shift register circuit 410B (2), IN1~IN5 points of input signal Not Wei the 1st grade of second scanning signal SB (1), commencing signal STV2, the 4th grade of second scanning signal SB (4), clock signal C6 and when Clock signal C8.If shift register circuit 600A is 3rd level the second shift register circuit 410B (3), input signal IN1~IN5 Respectively the 2nd grade of second scanning signal SB (2), the 1st grade of second scanning signal SB (1), the 5th grade of second scanning signal SB (5), when Clock signal C7 and clock signal C5.

Fig. 8 B illustrate the equivalent circuit diagram of the shift register circuit 600B according to some embodiments of the invention.Shift LD electricity Road 600B is shift register circuit 500B one of which embodiment, and it can be the shift register circuit of 4~N levels first Any shift LD electricity in 410A (4)~410A (N) and 4~N levels the second shift register circuit 410B (4)~410B (N) Road.Shift register circuit 600B includes precharge unit 610B, the first drop-down unit 620B, the drop-downs of output unit 630B and second Unit 640B, it distinguishes corresponding displaced register circuit 500B precharge unit 510B, the first drop-down unit 520B, output unit 530B and the second drop-down unit 540B.Precharge unit 610B, output unit 630B and the second drop-down unit 640B are respectively and figure 6A precharge unit 610A, output unit 630A and the second drop-down unit 640A is identical, therefore will not be described here.

First drop-down unit 620A includes transistor T3, T7.Transistor T3 the 3rd end receives input signal IN3, crystal Pipe T3 first end receives reference potential Vss, and transistor T3 the second end couple nodes X1.Transistor T7 the 3rd end receives Input signal IN6, transistor T7 first end receive reference potential Vss, and transistor T7 the second end couple nodes X1.

If shift register circuit 600B is the shift register circuit 410A (i) of i-stage first and i is more than or equal to 4 and small In or equal to (N-2) positive integer, then input signal IN1~IN3, IN6 are respectively (i-1) level the first scanning signal SA (i- 1), (i-2) level the first scanning signal SA (i-2), (i+2) level the first scanning signal SA (i+2) and commencing signal STV1.It is right For 4th to (N-2) level the first shift register circuit 410A (4)~410A (N-2), input signal IN4 is respectively clock signal C4, C1, C2, C3 circular order are (that is, to the 4th to (N-2) level the first shift register circuit 410A (4)~410A (N- 2) for, input signal IN4 is respectively C4, C1, C2, C3, C4, C1, C2, C3 ...), and input signal IN5 is respectively clock letter Number C2, C3, C4, C1 circular order.If shift register circuit 600A is (N-1) level the first shift register circuit 410A (N- 1), then input signal IN1~IN6 is respectively (N-2) level the first scanning signal SA (N-2), the first scanning signal of (N-3) level SA (N-3), reset signal RST1, clock signal C3, clock signal C1 and commencing signal STV1.If shift register circuit 600A is N levels the first shift register circuit 410A (N), then input signal IN1~IN6 is respectively the first scanning signal of (N-1) level SA (N-1), (N-2) level the first scanning signal SA (N-2), reset signal RST1, clock signal C4, clock signal C2 and letter is started Number STV1.

Similarly, if shift register circuit 600B is the shift register circuit 410B (i) of i-stage second and i is to be more than or wait In 4 and less than or equal to (N-2) positive integer, then input signal IN1~IN3, IN6 be respectively (i-1) level second scanning letter Number SB (i-1), (i-2) level the second scanning signal SB (i-2), (i+2) level the second scanning signal SB (i+2) and commencing signal STV2.For the 4th to (N-2) level the second shift register circuit 410B (4)~410B (N-2), when input signal IN4 is respectively Clock signal C8, C5, C6, C7 circular order, and input signal IN5 is respectively clock signal C6, C7, C8, C5 circular order. If shift register circuit 600A is (N-1) level the second shift register circuit 410B (N-1), input signal IN1~IN6 difference For (N-2) level the second scanning signal SB (N-2), (N-3) level the second scanning signal SB (N-3), reset signal RST2, clock Signal C7, clock signal C5 and commencing signal STV2.If shift register circuit 600A is the second shift register circuit of N levels 410B (N), then input signal IN1~IN6 is respectively (N-1) level the second scanning signal SB (N-1), the scanning letter of (N-2) level second Number SB (N-2), reset signal RST2, clock signal C8, clock signal C6 and commencing signal STV2.

In certain embodiments, display device 100 and 200 of the invention is integrated glass panel (the system on that unite glass；SOG display device), that is to say, that in the present invention, gate driver circuit 124A, 124B (or raster data model Device circuit 224A, 224B) it is to be produced on the substrate (figure does not illustrate) of display device 100 (or display device 200).Such one Come, gate driver circuit 124A, 124B (or gate driver circuit 224A, 224B) can be made using same process In electronic component (such as Fig. 8 A, 8B transistor T1~T7 and/or electric capacity Cx) and (or the viewing area of viewing area 110 210) electronic component (such as Fig. 3 first grid polar curve GA (1)~GA (N), second gate line GB (1)~GB (N), data in Transistor T in line D (1)~D (M) and/or pixel cell P).

In addition, Fig. 8 A, 8B transistor T1~T7 are not limited to low temperature polycrystalline silicon (low temperature polysilicon；LTPS) thin film transistor (TFT).For example, Fig. 8 A, 8B transistor T1~T7 can be non-crystalline silicons (amorphous silicon) thin film transistor (TFT), to reduce production cost.

Fig. 9 A to Fig. 9 C are Fig. 6 the first drive circuit 400A and the second drive circuit 400B in a picture frame cycle Timing diagram.In Fig. 9 A to Fig. 9 C, gap between each time point and its next time point for 1/4 clock signal C1~ C8 clock cycle (being represented below with the H times).As shown in Figure 9 A, each clock signal C1~C8 cycle phase is same.In this reality Apply in example, clock signal C1~C8 clock cycle is 4 H times.In each complete clock cycle, high potential is lasting Time and low potential duration are respectively 1/2 clock cycle (being namely respectively 2 H times).Clock signal C1~C4 2 H times are sequentially translated backward, and clock signal C5~C8 sequentially translates 2 H times backward, and clock signal C5 falls behind clock Mono- H time (i.e. 1/4 clock cycle) of signal C1.Initial signal STV1, STV2 is respectively in time point t₀、t₁From low potential liter To high potential, and respectively in time point t₂、t₃Low potential is down to from high potential.Clock signal C1~C4 is sequentially in time point t₂、 t₄、t₆、t₈High potential is upgraded to, and clock signal C5~C8 is sequentially in time point t₃、t₅、t₇、t₉It is upgraded to high potential.Reset signal STV1, STV2 are respectively in time point t_2N+4、t_2N+5High potential is risen to from low potential, and respectively in time point t_2N+6、t_2N+7From high electricity Potential drop is to low potential.

In time point t₀When, control signal CTRL and the 2nd grade of first shifting of the 1st grade of first shift register circuit 410A (1) Position register circuit 410A (2) control signal CTRL by commencing signal STV1 rise to high potential influenceed and from the first current potential V1 Rise to the second current potential V2.In the present embodiment, the first current potential V1 is corresponding to the reference potential Vss in Fig. 6 A, 6B.

In time point t₁When, control signal CTRL and the 2nd grade of second shifting of the 1st grade of second shift register circuit 410B (1) Position register circuit 410B (2) control signal CTRL by commencing signal STV2 rise to high potential influenceed and from the first current potential V1 Rise to the second current potential V2.

In time point t₂When, the control signal CTRL of the 1st grade of first shift register circuit 410A (1) is by clock signal C1 Rise to the influence of high potential and electric capacity Cx coupling and rise to the 3rd current potential V3, and the 1st of its output from the second current potential V2 The first scanning signal SA (1) of level rises to high potential from low potential.The control signal of 2nd grade of first shift register circuit 410A (2) CTRL maintains the second current potential V2.In addition, 3rd level the first shift register circuit 410A (3) control signal CTRL is by the 1st grade First scanning signal SA (1) rises to the influence of high potential and rises to the second current potential V2 from the first current potential V1.

In time point t₃When, the control signal CTRL of the 1st grade of second shift register circuit 410B (1) is by clock signal C5 Rise to the influence of high potential and electric capacity Cx coupling and rise to the 3rd current potential V3, and the 1st of its output from the second current potential V2 The second scanning signal SB (1) of level rises to high potential from low potential.The control signal of 2nd grade of second shift register circuit 410B (2) CTRL maintains the second current potential V2.In addition, 3rd level the second shift register circuit 410B (3) control signal CTRL is by the 1st grade Second scanning signal SB (1) rises to the influence of high potential and rises to the second current potential V2 from the first current potential V1.

In time point t₄When, the control signal CTRL of the 1st grade of first shift register circuit 410A (1) is by clock signal C1 It is down to the influence of low potential and electric capacity Cx coupling and is down to the 4th current potential V4, and the 1st of its output from the 3rd current potential V3 The first scanning signal SA (1) of level is down to low potential from high potential.It should be noted that in the present embodiment, the 4th current potential V4 electricity Place value is equal to the second current potential V2 potential value, but the present invention is not limited, in other embodiments, the 4th current potential V4 current potential Value can also be greater than the first current potential V1 and the potential value not equal to the second current potential V2.2nd grade of the first shift register circuit 410A (2) control signal CTRL by clock signal C2 rise to high potential influenceed and electric capacity Cx coupling and from second Current potential V2 rises to the 3rd current potential V3, and the 2nd grade of first scanning signal SA (2) of its output rises to high potential from low potential.3rd level First shift register circuit 410A (3) control signal CTRL maintains the second current potential V2.In addition, the 4th grade of the first shift LD Circuit 410A (4) control signal CTRL by the 2nd grade of first scanning signal SA (2) rise to high potential influenceed and from first electricity Position V1 rises to the second current potential V2.

In time point t₅When, the control signal CTRL of the 1st grade of second shift register circuit 410B (1) is by clock signal C5 It is down to the influence of low potential and electric capacity Cx coupling and is down to the 4th current potential V4, and the 1st of its output from the 3rd current potential V3 The second scanning signal SB (1) of level is down to low potential from high potential.The control signal of 2nd grade of second shift register circuit 410B (2) CTRL by clock signal C6 rise to high potential influenceed and electric capacity Cx coupling and from the second current potential V2 rise to the 3rd electricity Position V3, and the 2nd grade of second scanning signal SB (2) of its output rises to high potential from low potential.The shift register circuit of 3rd level second 410B (3) control signal CTRL maintains the second current potential V2.In addition, the control of the 4th grade of second shift register circuit 410B (4) Signal CTRL is risen to high potential by the 2nd grade of second scanning signal SB (2) to be influenceed and rises to the second current potential from the first current potential V1 V2。

In time point t₆When, the 1st grade of first scanning signal SA that the 1st grade of first shift register circuit 410A (1) is exported (1) being risen to high potential by clock signal C3 is influenceed and is reset.The control of 2nd grade of first shift register circuit 410A (2) Signal CTRL by clock signal C2 be down to low potential influenceed and electric capacity Cx coupling and be down to from the 3rd current potential V3 Four current potential V4, and the 2nd grade of first scanning signal SA (2) of its output is down to low potential from high potential.The shift LD of 3rd level first Circuit 410A (3) control signal CTRL by clock signal C3 rise to high potential influenceed and electric capacity Cx coupling and from Second current potential V2 rises to the 3rd current potential V3, and 3rd level the first scanning signal SA (3) of its output rises to high potential from low potential. The control signal CTRL of 4th grade of first shift register circuit 410A (4) maintains the second current potential V2.In addition, the 1st grade of first displacement Register circuit 410A (1) control signal CTRL is risen to high potential by 3rd level the first scanning signal SA (3) to be influenceed and from Four current potential V4 are down to the first current potential V1.

In time point t₇When, the 1st grade of second scanning signal SB that the 1st grade of second shift register circuit 410B (1) is exported (1) being risen to high potential by clock signal C7 is influenceed and is reset.The control of 2nd grade of second shift register circuit 410B (2) Signal CTRL by clock signal C6 be down to low potential influenceed and electric capacity Cx coupling and be down to from the 3rd current potential V3 Four current potential V4, and the 2nd grade of second scanning signal SB (2) of its output is down to low potential from high potential.The shift LD of 3rd level second Circuit 410B (3) control signal CTRL by clock signal C7 rise to high potential influenceed and electric capacity Cx coupling and from Second current potential V2 rises to the 3rd current potential V3, and 3rd level the second scanning signal SB (3) of its output rises to high potential from low potential. The control signal CTRL of 4th grade of second shift register circuit 410B (4) maintains the second current potential V2.In addition, the 1st grade of second displacement Register circuit 410B (1) control signal CTRL is risen to high potential by 3rd level the second scanning signal SB (3) to be influenceed and from Four current potential V4 are down to the first current potential V1.

In time point t₈When, the 2nd grade of first scanning signal SA that the 2nd grade of first shift register circuit 410A (2) is exported (2) being risen to high potential by clock signal C4 is influenceed and is reset.3rd level the first shift register circuit 410A (3) control Signal CTRL by clock signal C3 be down to low potential influenceed and electric capacity Cx coupling and be down to from the 3rd current potential V3 Four current potential V4, and 3rd level the first scanning signal SA (3) of its output is down to low potential from high potential.4th grade of the first shift LD Circuit 410A (4) control signal CTRL by clock signal C4 rise to high potential influenceed and electric capacity Cx coupling and from Second current potential V2 rises to the 3rd current potential V3, and the 4th grade of first scanning signal SA (4) of its output rises to high potential from low potential. The control signal CTRL of 5th grade of first shift register circuit 410A (5) maintains the second current potential V2.In addition, the 2nd grade of first displacement Register circuit 410A (1) control signal CTRL is risen to high potential by the 4th grade of first scanning signal SA (4) to be influenceed and from Four current potential V4 are down to the first current potential V1.

In time point t₉When, the 2nd grade of second scanning signal SB that the 2nd grade of second shift register circuit 410B (2) is exported (2) being risen to high potential by clock signal C8 is influenceed and is reset.3rd level the second shift register circuit 410B (3) control Signal CTRL by clock signal C7 be down to low potential influenceed and electric capacity Cx coupling and be down to from the 3rd current potential V3 Four current potential V4, and 3rd level the second scanning signal SB (3) of its output is down to low potential from high potential.4th grade of the second shift LD Circuit 410B (4) control signal CTRL by clock signal C8 rise to high potential influenceed and electric capacity Cx coupling and from Second current potential V2 rises to the 3rd current potential V3, and the 4th grade of second scanning signal SB (4) of its output rises to high potential from low potential. The control signal CTRL of 5th grade of second shift register circuit 410B (5) maintains the second current potential V2.In addition, the 2nd grade of second displacement Register circuit 410B (2) control signal CTRL is risen to high potential by the 4th grade of second scanning signal SB (4) to be influenceed and from Four current potential V4 are down to the first current potential V1.

As shown in Fig. 9 A~9C, the shift register circuit 410A (i) of i-stage first control signal CTRL is (i-1) level First shift register circuit 410A (i-1) control signal CTRL waveforms translate 2 H times backward, and the displacement of i-stage first is posted The the first scanning signal SA (i) for depositing circuit 410A (i) is the first of (i-1) level the first shift register circuit 410A (i-1) to sweep Retouch signal SA (i-1) waveform and translate 2 H times backward, wherein i is more than or equal to 3 and just whole less than or equal to (N-2) Number.

Similarly, the shift register circuit 410B (i) of i-stage second control signal CTRL is that (i-1) level second shifts Register circuit 410B (i-1) control signal CTRL waveforms translate 2 H times backward, and the shift register circuit of i-stage second 410B (i) the second scanning signal SB (i) is (i-1) level the second shift register circuit 410B (i-1) the first scanning letter Number SB (i-1) waveform translates 2 H times backward, and wherein i is the positive integer more than or equal to 3 and less than or equal to (N-2).

In time point t_(2N-6)With time point t_(2N-4)When, (N-1) level the first shift register circuit 410A (N-1) and N The first shift register circuit 410A (N) of level control signal CTRL rises to the second current potential V2 from the first current potential V1 respectively.In the time Point t_(2N-2)With time point t_(2N)When, (N-1) level the first shift register circuit 410A (N-1) is electric with the shift LD of N levels first Road 410A (N) control signal CTRL rises to the 3rd current potential V3 from the second current potential V2 respectively.In time point t_(2N)When, (N-1) The first shift register circuit 410A (N-1) of level control signal CTRL is down to the 4th current potential V4 from the 3rd current potential V3.

Similarly, in time point t_(2N-5)With time point t_(2N-3)When, (N-1) level the second shift register circuit 410B (N- 1) the control signal CTRL with N levels the second shift register circuit 410B (N) rises to the second current potential V2 from the first current potential V1 respectively. In time point t_(2N-1)With time point t_(2N+1)When, (N-1) level the second shift register circuit 410B (N-1) moves with N levels second Position register circuit 410B (N) control signal CTRL rises to the 3rd current potential V3 from the second current potential V2 respectively.In time point t_(2N+1) When, (N-1) level the second shift register circuit 410B (N-1) control signal CTRL is down to the 4th current potential from the 3rd current potential V3 V4。

In time point t_(2N+2)When, because reset signal RST1 is still in low potential, therefore the first shift LD of (N-1) level Circuit 410A (N-1) control signal CTRL maintains the second current potential V2.N levels the first shift register circuit 410A (N) control Signal CTRL processed by clock signal C4 be down to low potential influenceed and electric capacity Cx coupling and be down to from the 3rd current potential V3 4th current potential V4, and N levels the first scanning signal SA (N) of its output is down to low potential from high potential.

In time point t_(2N+3)When, because reset signal RST2 is still in low potential, therefore the second shift LD of (N-1) level Circuit 410B (N-1) control signal CTRL maintains the second current potential V2.N levels the second shift register circuit 410B (N) control Signal CTRL processed by clock signal C8 be down to low potential influenceed and electric capacity Cx coupling and be down to from the 3rd current potential V3 4th current potential V4, and N levels the second scanning signal SB (N) of its output is down to low potential from high potential.

In time point t_(2N+4)When, reset signal RST1 rises to high potential from low potential so that (N-1) level first shifts Register circuit 410A (N-1) and N levels the first shift register circuit 410A (N) control signal CTRL is down to from the 4th current potential V4 First current potential V1.

In time point t_(2N+5)When, reset signal RST2 rises to high potential from low potential so that (N-1) level second shifts Register circuit 410B (N-1) and N levels the second shift register circuit 410B (N) control signal CTRL is down to from the 4th current potential V4 First current potential V1.

From the timing diagram shown in Fig. 9 A to Fig. 9 C, for the 1st grade of first shift register circuit 410A (1) and the 1st grade For second shift register circuit 410B (1), control signal CTRL from the first current potential V1 rise to the second current potential V2 time point with It rises to the 3rd current potential V3 time point at a distance of 1/2 clock cycle (i.e. 2 H times) from the second current potential V2, and it maintains the Three current potential V3 time span is 1/2 clock cycle (i.e. 2 H times), and it is down to the 4th current potential V4 from the 3rd current potential V3 Time point be down to the first current potential V1 time point at a distance of 1/2 clock cycle (i.e. 2H times) from the 4th current potential V4 with it；It is right For (N-1) level the first shift register circuit 410A (N-1) and (N-1) level the second shift register circuit 410B (N-1), The time point that control signal CTRL rises to the second current potential V2 from the first current potential V1 rises to the 3rd current potential V3 with it from the second current potential V2 Time point at a distance of a clock cycle (i.e. 4 H times), it is 1/2 clock that it, which maintains the 3rd current potential V3 time span, Cycle (i.e. 2 H times), and it is down to the 4th current potential V4 time point from the 3rd current potential V3 and is down to the from the 4th current potential V4 with it One current potential V1 time point is at a distance of a clock cycle (i.e. 4 H times)；For other first shift register circuits (such as 410A (2)~410A (N-2), 410A (N)) and the second shift register circuit for (such as 410B (2)~410B (N-2), 410B (N)), control signal CTRL rises to the second current potential V2 time point from the first current potential V1 and rises to the 3rd electricity from the second current potential V2 with it Position V3 time point, it maintained the 3rd current potential V3 time span as 1/2 at a distance of a clock cycle (i.e. 4 H times) Clock cycle (i.e. 2 H times), and it is down to the 4th current potential V4 time point from the 3rd current potential V3 and dropped with it from the 4th current potential V4 To the first current potential V1 time point at a distance of 1/2 clock cycle (i.e. 2 H times).

In addition, as shown in Figure 9 C, although each first scanning signal SA (1)~SA (N) and with each second scanning signal SB (1)~SB (N) high potential was held time as 2 H times, but each first scanning signal SA (1)~SA (N) and and every Individual second scanning signal SB (1)~SB (N) front half section high potential hold time (1 H time) be preliminary filling pixel cell, and Second half section high potential hold time (1H times) be pixel cell Data writing time.For example, in the first scanning signal SA (2) high potential is held time t₄~t₆In, t₅~t₆Time interval (1 H time) be Data writing time, and Two scanning signal SB (2) high potential is held time t₅~t₇In, t₆~t₇Time interval (1 H time) for data write when Between.

From the foregoing, control signal CTRL current potential is in each first scanning signal SA (1)~SA (N) and each second Scanning signal SB (1)~SB (N) is risen to before high potential by low potential and rises to the second current potential V2 from the first current potential V1 in advance, until right The 3rd current potential V3 is risen to when viewing area is scanned from the second current potential V2 again, and indirect rises to the 3rd electricity from the first current potential V1 Position V3.In addition, when each first scanning signal SA (1)~SA (N) and each second scanning signal SB (1)~SB (N) is by high electricity During potential drop to low potential, control signal CTRL current potential is first down to the 4th current potential V4 from the 3rd current potential V3, and when passing through 1/2 again The first current potential V1 is down to from the 4th current potential V4 after clock cycle or 1 time cycle (namely 2 H or 4 H times), and it is non-straight Connect from the 3rd current potential V3 and be down to the first current potential V1.Consequently, it is possible to the first shift register circuit 410A (1)~410A (N) can be extended With the operating time of the second shift register circuit 410B (1)~410B (N) discharge circuit, it is not easily susceptible to control signal CTRL The interference of other noises and cause the first scanning signal SA (1)~SA (N) and the second scanning signal SB (1)~SB (N) output Waveform is lifted the display quality of display device by being influenceed.

It should be noted that although for the 1st grade of first shift register circuit 410A (1) and the 1st grade of the second shift LD electricity For road 410B (1), control signal CTRL rises to the second current potential V2 time point with it from the second current potential V2 from the first current potential V1 The 3rd current potential V3 time point is risen at a distance of 1/2 clock cycle (i.e. 2 H times), and other grades of the first shift LD is electric The control signal CTRL of road and the second shift register circuit rises to the second current potential V2 time point with it from the from the first current potential V1 Two current potential V2 rise to the 3rd current potential V3 time point at a distance of being then 1 clock cycle (i.e. 4 H times), but art Technical staff can voluntarily adjust the 1st grade of first shift register circuit 410A (1) in Fig. 6,8A, 8B and the 1st grade of second displacement Register circuit 410B (1), with cause its control signal CTRL from the first current potential V1 rise to the second current potential V2 time point with its from Second current potential V2 rises to the 3rd current potential V3 time point also at a distance of 1 clock cycle (i.e. 4 H times).For example, In addition to commencing signal the line SL1 and SL2 in Fig. 6 provide commencing signal STV1 and STV2 respectively, additionally another can be set to open Beginning signal wire SL1 ' and another commencing signal line SL2 ' to provide commencing signal STV1 ' and STV2 ', wherein commencing signal respectively It is 2 H times that STV1 ' high potential, which is held time same with commencing signal STV1, but commencing signal STV1 ' is raised to by low potential The time of high potential is raised to time early 2 H times of high potential, that is, commencing signal compared with commencing signal STV1 by low potential STV1 ' is that commencing signal STV1 waveform is translated forward into 2 H times.Similarly, commencing signal STV2 ' high potential maintains It is 2 H times that time is same with commencing signal STV2, but commencing signal STV2 ' is raised to time of high potential by low potential and relatively opened Beginning signal STV2 early 2 H times.Whereby by the input signal IN2 of the 1st grade of first shift register circuit 410A (1) by letter Number STV1 is changed to commencing signal STV1 ', by the input signal IN2 of the 1st grade of second shift register circuit 410B (1) by commencing signal STV2 is changed to commencing signal STV2 ', then the 1st grade of first shift register circuit 410A (1) and the 1st grade of the second shift register circuit 410B (1) control signal CTRL rises to the second current potential V2 time point from the first current potential V1 and rises to the from the second current potential V2 with it Three current potential V3 time point and the 1st grade of the first shift register circuit of other levels and the 1st grade of the second shift register circuit are also At a distance of 1 clock cycle (i.e. 4 H times).

Similarly, although being shifted for (N-1) level the first shift register circuit 410A (N-1) and (N-1) level second For register circuit 410B (N-1), control signal CTRL is down to the 4th current potential V4 time point with it from the from the 3rd current potential V3 Four current potential V4 are down to the first current potential V1 time point at a distance of a clock cycle (i.e. 4 H times), and other grades first shift The control signal CTRL of register circuit and the second shift register circuit from the 3rd current potential V3 be down to the 4th current potential V4 time point with It is down to the first current potential V1 time point at a distance of 1/2 clock cycle (i.e. 2 H times) from the 4th current potential V4, but affiliated technology The technical staff in field can voluntarily change (N-1) level the first shift register circuit 410A (N-1) and in Fig. 6,8A, 8B (N-1) the second shift register circuit of level 410B (N-1), to cause its control signal CTRL to be down to the 4th current potential from the 3rd current potential V3 V4 time point with its from the 4th current potential V4 be down to the first current potential V1 time point also at a distance of 1/2 clock cycle (i.e. The 2H times).For example, can in addition to reset signal the line RL1 and RL2 in Fig. 6 provide reset signal RST1 and RST2 respectively Another reset signal line RL1 ' and another reset signal line RL2 ' are additionally set to provide reset signal RST1 ' and RST2 ' respectively, It is 2 H times that wherein reset signal RST1 ' high potential, which is held time same with reset signal RST1, but reset signal RST1 ' The time of high potential is raised to compared with reset signal STV1 early 2 H times, that is, in time point t by low potential_(2N+2), reset signal RST1 ' is raised to high potential by low potential, and in time point t_(2N+4), reset signal RST1 ' drops to low potential by high potential.Equally Ground, it is 2 H times that reset signal RST2 ' high potential, which is held time same with reset signal RST2, but reset signal RST2 ' The time of high potential is raised to compared with reset signal RST2 early 2 H times, that is, in time point t by low potential_(2N+3), reset signal RST1 ' is raised to high potential by low potential, and in time point t_(2N+5), reset signal RST1 ' drops to low potential by high potential.Whereby (N-1) level the first shift register circuit 410A (N-1) input signal IN3 is changed to reset signal by reset signal RST1 RST1 ', (N-1) level the second shift register circuit 410B (1) input signal IN3 is changed to reset by reset signal RST2 and believed Number RST2 ', then (N-1) level the first shift register circuit 410A (N-1) and the second shift register circuit of (N-1) level 410B (N-1) control signal CTRL is down to the 4th current potential V4 time point with being down to the first electricity from the 4th current potential V4 from the 3rd current potential V3 Position V1 time point gap can same with other shift register circuits of level first and the second shift register circuit be 1/2 clock week Phase (i.e. 2 H times).

Although the present invention illustrates that as above, so it is not limited to the present invention, any art with embodiment In technical staff, without departing from the spirit and scope of the present invention, when can make a little variation and retouching, therefore the guarantor of the present invention Shield scope is worked as to be defined depending on as defined in claim.

Claims

1. a kind of display device, it is characterised in that the display device has viewing area and neighboring area, and the display dress Put and include：

Multiple pixel cells, it is arranged in the viewing area, the pixel cell is arranged as multiple pixel columns and multiple pixels OK；

N bar first grid polar curves and N bar second gate lines, are staggered in the viewing area, wherein each pixel column It is coupled to one of one of described first grid polar curve and described second gate line；

First drive circuit, it is arranged in the neighboring area, first drive circuit includes the 1st to the 4th clock cable And the 1st grade to the shift register circuit of N levels first, the 1st to the 4th clock cable respectively to provide the 1st to the 4th when Clock signal, first shift register circuit is respectively at least one clock letter in the 1st to the 4th clock signal Number produce and provide the 1st grade to the scanning signal of N levels first to the first grid polar curve；

Second drive circuit, it is arranged in the neighboring area, second drive circuit includes the 5th to the 8th clock cable And the 1st grade to the shift register circuit of N levels second, the 5th to the 8th clock cable respectively to provide the 5th to the 8th when Clock signal, second shift register circuit is respectively at least one clock letter in the 5th to the 8th clock signal Number produce and provide the 1st grade to the scanning signal of N levels second to the second gate line；

Wherein, the clock cycle length of the 1st to the 8th clock signal is identical, and in the described 1st to the 8th clock signal (j+4) clock signal differs 1/4 clock cycle with the jth clock signal in the 1st to the 8th clock signal, and described first The high potential duration of the scanning signal of i-stage first in scanning signal and the i-stage second in second scanning signal The high potential duration of scanning signal is identical, the scanning signal of i-stage first in first scanning signal and described second The scanning signal of i-stage second in scanning signal differs 1/4 clock cycle, and wherein N is the positive integer more than or equal to 2, and j is Positive integer more than or equal to 1 and less than or equal to 4, and i is any positive integer in 1 to N.

2. display device as claimed in claim 1, it is characterised in that being shaped as the viewing area is non-rectangle.

3. display device as claimed in claim 1, it is characterised in that the i-stage first in first shift register circuit The shift register circuit of i-stage second in shift register circuit or second shift register circuit includes：

Precharge unit, first node is coupled, and to export a control signal by the first node；

Output unit, it is to receive the control signal, and to be exported by section point in first scanning signal The scanning signal of i-stage second in the scanning signal of i-stage first or second scanning signal.

4. display device as claimed in claim 1, it is characterised in that the control letter of the shift register circuit of i-stage first Number the second current potential is changed into by the first current potential at the 1st time point, the 3rd electricity is changed into by second current potential at the 3rd time point Position, the 4th current potential is changed into by the 3rd current potential at the 5th time point, and turned at the 7th time point by the 4th current potential It is changed into first current potential, wherein the 3rd current potential is more than second current potential and the 4th current potential, and second electricity Position and the 4th current potential are more than first current potential；

The control signal of the shift register circuit of i-stage second is changed into described at the 2nd time point by first current potential Two current potentials, the 3rd current potential is changed into by second current potential at the 4th time point, at the 6th time point by the 3rd current potential It is changed into the 4th current potential, and first current potential is changed into by the 4th current potential at the 8th time point；

(m+1) time point at one of wherein described 1st to the 8th time point falls behind the m at one of the 1st to the 8th time point 1/4 clock cycle of time point, m are any positive integer in 1,3,5 and 7.

5. display device as claimed in claim 4, it is characterised in that the potential value of second current potential and the 4th current potential Potential value it is equal.

6. display device as claimed in claim 4, it is characterised in that the scanning signal of i-stage first is at the described 3rd Between point high potential is converted to by low potential, and low potential, and the i-stage are converted to by high potential at the 5th time point Second scanning signal is to be converted to high potential by low potential at the 4th time point, and is turned at the 6th time point by high potential It is changed to low potential.

7. display device as claimed in claim 4, it is characterised in that the time at the 5th time point and the 7th time point Difference is at least 1/2 clock cycle, and the time difference at the 6th time point and the 8th time point is at least 1/2 clock week Phase.

8. display device as claimed in claim 4, it is characterised in that the time at the 1st time point and the 7th time point Difference is at least 3/2 clock cycle, and the time difference at the 2nd time point and the 8th time point is at least 3/2 clock week Phase.

9. display device as claimed in claim 1, it is characterised in that first drive circuit and second drive circuit It is the opposite sides for being separately positioned on the viewing area.

10. display device as claimed in claim 1, it is characterised in that each pixel cell includes at least one film Transistor, first drive circuit includes multiple thin film transistor (TFT)s respectively with second drive circuit, and described first drives Dynamic circuit and the thin film transistor (TFT) of second drive circuit and the thin film transistor (TFT) of the pixel cell are to be co-located on one On individual substrate.

11. display device as claimed in claim 10, it is characterised in that first drive circuit and the second driving electricity The thin film transistor (TFT) of the thin film transistor (TFT) on road and the pixel cell is amorphous silicon film transistor.

12. display device as claimed in claim 1, it is characterised in that the 1st to the 8th clock signal is a clock week The high potential duration in phase is respectively 1/2 clock cycle, (k+1) clock letter in the 1st to the 4th clock signal Number differed with kth clock signal 1/2 clock cycle, and (k+5) clock signal in the 5th to the 8th clock signal with (k+4) clock signal differs 1/2 clock cycle, and wherein k is the positive integer more than or equal to 1 and less than or equal to 3.

13. display device as claimed in claim 1, it is characterised in that described 1st grade into the scanning signal of N levels first The scanning signal of i-stage first and the 1st grade of high potential to the scanning signal of i-stage second in the scanning signal of N levels second Duration is respectively 1/2 clock cycle, and during the high potential of the scanning signal of the i-stage first with the i-stage It is 1/4 clock cycle that overlaps in sequential during the high potential of two scanning signals.

14. display device as claimed in claim 3, it is characterised in that the precharge unit is believed to receive the first input Number and the second input signal, and the output unit is receiving the 4th input signal；

In the shift register circuit of i-stage first or second shift register circuit in first shift register circuit The shift register circuit of i levels second also includes：

First drop-down unit, it couples the first node and to receive the 3rd input signal；And

Second drop-down unit, it couples the section point and to receive the 5th input signal；

The 4th input signal and the 5th input signal of the wherein described shift register circuit of i-stage first be respectively the described 1st to The two of which of 4th clock signal, and the 3rd input signal is swept for (i+2) level first in first scanning signal Retouch signal or the first reset signal；

When the 4th input signal and the 5th input signal of the shift register circuit of i-stage second are respectively the described 5th to the 8th The two of which of clock signal, and the 3rd input signal is the scanning letter of (i+2) level second in second scanning signal Number or the second reset signal.

15. display device as claimed in claim 14, it is characterised in that when i is (n-3), the displacement of i-stage first is posted The 4th input signal for depositing circuit is the 1st clock signal, and the 4th input signal of the shift register circuit of i-stage second is institute State the 5th clock signal；

When i is (n-2), the 4th input signal of the shift register circuit of i-stage first is the 2nd clock signal, i-th 4th input signal of the second shift register circuit of level is the 6th clock signal；

When i is (n-1), the 4th input signal of the shift register circuit of i-stage first is the 3rd clock signal, i-th 4th input signal of the second shift register circuit of level is the 7th clock signal；

When i is n, the 4th input signal of the shift register circuit of i-stage first is the 4th clock signal, i-stage 4th input signal of two shift register circuits is the 8th clock signal；

Wherein n is the positive integer less than or equal to N and the multiple for being 4.

16. display device as claimed in claim 14, it is characterised in that when i is 1, the shift LD of i-stage first electricity First input signal and the second input signal on road are all the first commencing signal, and the shift register circuit of the i-stage second First input signal and the second input signal are all the second commencing signal；

When i is 2, the first input signal and the second input signal of the shift register circuit of i-stage first are respectively described The first scanning signal of (i-1) level and first commencing signal in first scanning signal, the shift LD of i-stage second The first input signal and the second input signal of circuit are respectively the scanning letter of (i-1) level second in second scanning signal Number and second commencing signal；And

When i is 3 to N any positive integer, the first input signal of the shift register circuit of i-stage first and the second input Signal is respectively the first scanning signal of (i-1) level and the first scanning signal of (i-2) level in first scanning signal, institute It is respectively in second scanning signal to state the first input signal of the shift register circuit of i-stage first and the second input signal The second scanning signal of (i-1) level and the second scanning signal of (i-2) level.

17. display device as claimed in claim 14, it is characterised in that the precharge unit includes the first transistor and the Two-transistor, the first end of the first transistor and the 3rd end are receiving first input signal, second crystal For the first end of pipe with the 3rd end to receive second input signal, first drop-down unit includes third transistor, institute The 3rd end of third transistor is stated to receive the 3rd input signal, the second end coupling of the third transistor described the One node, the output unit include the 4th transistor and electric capacity, and the 3rd end of the 4th transistor couples the first segment Point, the first end of the 4th transistor is receiving the 4th input signal, second end of the 4th transistor The section point is coupled, and the electric capacity couples the 3rd end and the second end of the 4th transistor.