CN109658861B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN109658861B CN109658861B CN201910152126.3A CN201910152126A CN109658861B CN 109658861 B CN109658861 B CN 109658861B CN 201910152126 A CN201910152126 A CN 201910152126A CN 109658861 B CN109658861 B CN 109658861B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The invention discloses a display panel and a display device, comprising: an array substrate; a plurality of scanning line groups and a pixel array which are positioned on the array substrate; the scanning line group comprises two scanning lines extending along a first direction; the pixel array comprises a plurality of pixel rows and a plurality of pixel columns; the pixel rows and the scanning line groups are arranged in a one-to-one correspondence manner, and in the same pixel row, two adjacent pixels are respectively and electrically connected with different scanning lines in the same scanning line group; a shift register electrically connected to the scanning line; the clock signal output end of the clock control circuit is electrically connected with the clock signal input end of the shift register; the clock signal output end of the clock control circuit outputs periodic pulse signals, the pulse signals comprise enable signals and overdrive signals with opposite electric potentials, and in each period, the clock signal output end outputs the overdrive signals when the enable signals are ended. The problem of insufficient pixel charging is effectively solved, and the display effect of the display panel is effectively improved.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
A conventional display panel includes a plurality of scan lines, a plurality of data lines, a plurality of pixels, and a shift register electrically connected to the scan lines. The shift register is used for sequentially outputting scanning signals to a plurality of scanning lines, and the data lines output data driving signals, so that pixels electrically connected with the scanning lines and the data lines are driven to display images.
The existing display panel generally includes single-gate driving, double-gate driving and triple-gate driving, and the first two are most commonly used. The dual-gate driving means that each row of pixels in the display panel is controlled by two scanning lines. The dual-gate driving display panel provided by the prior art has the condition that the charging capability and the display effect of pixels are poor. Therefore, it is an urgent technical problem to be solved in the art to provide a display panel and a display device with good display effect.
Disclosure of Invention
In view of the above, the present invention provides a display panel, including: an array substrate; a plurality of scanning line groups and a pixel array which are positioned on the array substrate; the scanning line group comprises two scanning lines extending along a first direction; the pixel array comprises a plurality of pixel rows and a plurality of pixel columns; the pixel row comprises a plurality of pixels arranged along a first direction, the pixel column comprises a plurality of pixels arranged along a second direction, and the first direction and the second direction are intersected; the pixel rows and the scanning line groups are arranged in a one-to-one correspondence manner, and in the same pixel row, two adjacent pixels are respectively and electrically connected with different scanning lines in the same scanning line group; a shift register electrically connected to the scanning line; the clock signal output end of the clock control circuit is electrically connected with the clock signal input end of the shift register; the clock signal output end of the clock control circuit outputs periodic pulse signals, the pulse signals comprise enable signals and overdrive signals with opposite electric potentials, and in each period, the clock signal output end outputs the overdrive signals when the enable signals are ended.
The invention also provides a display device comprising the display panel provided by the invention.
Compared with the prior art, the display panel and the display device provided by the invention at least realize the following beneficial effects:
the shift register in the display panel is electrically connected with the scanning line, and the clock signal output end of the clock control circuit is electrically connected with the clock signal input end of the shift register, so that the periodic pulse signals output by the clock signal output end of the clock control circuit are sequentially transmitted to the scanning line through the shift register. A clock signal output end of the clock control circuit outputs periodic pulse signals to the shift register, in each period, the shift register transmits an enable signal to a certain scanning line in a first time interval so as to enable a thin film transistor of a pixel connected with the scanning line to be started, and the pixel is charged when the thin film transistor of the pixel is started so as to enable the pixel connected with the scanning line to display images; the shift register transmits the over-drive signal to the scanning line in the second period, the potentials of the enable signal and the over-drive signal are opposite, the over-drive signal enables the thin film transistor of the pixel connected with the scanning line to be closed, the clock signal output end outputs the over-drive signal when the enable signal is ended in each period, and the potential of the scanning line can be rapidly changed by the over-drive signal, so that the closing time of the thin film transistor of the pixel is reduced.
Of course, it is not necessary for any product in which the present invention is practiced to specifically achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic structural diagram of a display panel according to the prior art;
FIG. 2 is a timing diagram of the clock signal input terminal of the shift register in the display panel of FIG. 1;
FIG. 3 is a schematic structural diagram of a display panel according to the present invention;
FIG. 4 is a timing diagram of clock signals at the input of the shift register of the display panel shown in FIG. 3;
FIG. 5 is a schematic diagram of a clock control circuit according to the present invention;
FIG. 6 is a schematic diagram of another clock control circuit according to the present invention;
FIG. 7 is a schematic structural diagram of another display panel provided in the present invention;
FIG. 8 is a schematic structural diagram of another display panel provided in the present invention;
FIG. 9 is a schematic view of the structure of section E in FIG. 8;
fig. 10 is a schematic structural diagram of a display device according to the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Aiming at the phenomenon that the charging capability and the display effect of the pixels in the display panel provided by the prior art are poor, the inventor carries out the following research on the display panel provided by the prior art:
fig. 1 is a schematic structural diagram of a display panel according to the prior art, fig. 2 is a signal timing diagram of a clock signal input terminal of a shift register in the display panel shown in fig. 1, and referring to fig. 1 and fig. 2, the display panel includes: an array substrate 1; a plurality of scanning line groups 5 and pixel arrays 2 on the array substrate 1; the scanning line group 5 includes two scanning lines 6 extending in the first direction X; the pixel array 2 includes a plurality of pixel rows 3 and a plurality of pixel columns 4; wherein the pixel row 3 comprises a plurality of pixels 8 arranged along a first direction X, the pixel column 4 comprises a plurality of pixels 8 arranged along a second direction Y, the first direction X and the second direction Y intersect; the pixel rows 3 and the scanning line groups 5 are arranged in a one-to-one correspondence manner, and in the same pixel row 3, two adjacent pixels 8 are respectively and electrically connected with different scanning lines 6 in the same scanning line group 5; and a shift register 7 electrically connected to the scanning line 6.
In the display panel provided by the prior art, a periodic driving signal is provided to the shift register 7, and in each period t1, the shift register 7 transmits a high level input by a clock signal input end to a certain scanning line 6 in a first time period t11, so that a thin film transistor of a pixel 8 connected to the scanning line 6 is turned on, and the pixel 8 connected to the scanning line 6 is driven to display an image; then, a pull-down signal is transmitted to the scan line 6 to pull down the potential of the scan line 6, so that the thin film transistor of the pixel 8 connected to the scan line 6 is turned off. Since the shift register 7 cannot pull down the potential of the scan line 6 quickly in the prior art, a second period t12 immediately follows the first period t11 in each period t1, and the shift register 7 gradually pulls down the potential of the scan line 6 in the second period t12 until the potential of the scan line 6 is at a low potential. The time of each cycle t1 is usually set to be a fixed value, the existence of the second time period t12 enables the time of the first time period t11 to be reduced, and since only the first time period t11 in each cycle t1 can charge the corresponding pixel 8, the second time period t12 cannot charge the corresponding pixel 8, so that the pixel 8 has the problem of insufficient charge, which affects the display of the display panel.
In addition, the display panel provided by the prior art adopts dual-gate driving, that is, the two scanning lines 6 in the scanning line group 5 drive the pixels 8 in the pixel row 3 corresponding to the scanning line group 5, and because the number of the scanning lines 6 in the display panel of the prior art is large, the time of each period t1 is correspondingly reduced, the problem of insufficient charging of the pixels 8 is aggravated, and the display of the display panel is further influenced.
In view of the above, the present invention provides a display panel and a display device to solve the problem of poor charging capability and display effect of pixels in the display panel in the prior art. Embodiments of the display panel and the display device provided by the embodiments of the present invention will be described in detail below.
Fig. 3 is a schematic structural diagram of a display panel according to the present invention, fig. 4 is a signal timing diagram of a clock signal input terminal of a shift register in the display panel shown in fig. 3, and referring to fig. 3 and fig. 4, the present embodiment provides a display panel, including:
an array substrate 10;
a plurality of scan line groups G1 and a pixel array 20 on the array substrate 10;
the scan line group G1 includes two scan lines G10 extending in the first direction X;
the pixel array 20 includes a plurality of pixel rows 21 and a plurality of pixel columns 22; wherein the pixel row 21 includes a plurality of pixels 30 arranged along a first direction X, and the pixel column 22 includes a plurality of pixels 30 arranged along a second direction Y, the first direction X and the second direction Y intersecting;
the pixel rows 21 and the scanning line groups G1 are arranged in a one-to-one correspondence, and in the same pixel row 21, two adjacent pixels 30 are respectively and electrically connected with different scanning lines G10 in the same scanning line group G1;
a shift register 40 electrically connected to the scanning line G10;
a clock signal output end of the clock control circuit 50 is electrically connected with a clock signal input end of the shift register 40;
the clock signal output terminal of the clock control circuit 50 outputs a periodic pulse signal including an enable signal and an overdrive signal of opposite potentials, and in each period, the clock signal output terminal outputs the overdrive signal at the end of the enable signal.
Specifically, in the display panel provided by this embodiment, the array substrate 10 is provided with the scan line group G1 and the pixel array 20, the pixel array 20 is formed by arranging a plurality of pixels 30 in an array, the pixel rows 21 and the scan line group G1 are arranged in a one-to-one correspondence, and the pixels 30 in the same pixel row 21 are driven by two scan lines G10 in the scan line group G1 corresponding to the pixels.
The shift register 40 is electrically connected to the scan line G10, and the clock signal output terminal of the clock control circuit 50 is electrically connected to the clock signal input terminal of the shift register 40, so that the periodic pulse signals output from the clock signal output terminal of the clock control circuit 50 are sequentially transmitted to the scan line G10 through the shift register 40. The clock signal output end of the clock control circuit 50 outputs a periodic pulse signal to the shift register 40, and in each period T1, the shift register 40 transmits an enable signal to a certain scanning line G10 in a first period T11 to turn on the thin film transistor of the pixel 30 connected to the scanning line G10, and charges the pixel 30 when the thin film transistor of the pixel 30 is turned on, so that the pixel 30 connected to the scanning line G10 displays an image; the shift register 40 transmits an overdrive signal to the scan line G10 in the second period T12, the potentials of the enable signal and the overdrive signal are opposite, the overdrive signal turns off the thin film transistor of the pixel 30 connected to the scan line G10, in each period T1, the clock signal output terminal outputs the overdrive signal when the enable signal is over, the overdrive signal can rapidly change the potential of the scan line G10, thereby reducing the off time of the thin film transistor of the pixel 30, since the pixel 30 cannot be charged when the thin film transistor of the pixel 30 is off, the off time of the thin film transistor of the pixel 30 can be reduced to increase the time for charging the pixel 30 in the first period T11, thereby effectively improving the problem of insufficient charging of the pixel 30, and effectively improving the display effect of the display panel.
It should be noted that, in the present invention, the fact that the potentials of the enable signal and the overdrive signal are opposite means that one of the enable signal and the overdrive signal is a high potential signal and the other is a low potential signal, and for example, the potential of the enable signal is 15V and the potential of the overdrive signal is-14V, and the present invention is not limited to that the potentials of the enable signal and the overdrive signal are opposite.
It should be noted that the overdrive signal is exemplarily shown in this embodiment, so that the off time of the thin film transistor of the pixel 30 is close to 0, and thus the pixel 30 can be charged nearly in the entire first period T11. In other embodiments of the present invention, there is a portion of time for turning off the tft of the pixel 30 in the first period T11, and the pixel 30 is not charged in the whole first period T11, but compared with the prior art, the overdrive signal effectively shortens the turn-off time of the tft of the pixel 30, effectively improves the problem of insufficient charging of the pixel 30, and effectively improves the display effect of the display panel, and the present invention is not repeated herein.
Fig. 5 is a schematic structural diagram of a clock control circuit provided in the present invention, referring to fig. 5, optionally, wherein the clock control circuit includes a first control module 51 and a second control module 52 electrically connected to each other;
the clock signal output end CLK is electrically connected with the first control module 51;
the first control module 51 and the second control module 52 are used for controlling the clock signal output terminal CLK to output a periodic pulse signal.
Fig. 6 is a schematic structural diagram of another clock control circuit provided by the present invention, referring to fig. 6, optionally, wherein the first control module 1 includes a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, a fourth switching transistor M4, a first input terminal a, a second input terminal B, a first voltage signal terminal VGH, and a clock signal output terminal CLK;
a control terminal of the first switching transistor M1 is connected to the first input terminal a, a first terminal of the first switching transistor M1 is connected to the first voltage signal terminal VGH, and a second terminal of the first switching transistor M1 is connected to the clock signal output terminal CLK;
a control terminal of the second switching transistor M2 is connected to the second input terminal B, a first terminal of the second switching transistor M2 is connected to the first voltage signal terminal VGH, and a second terminal of the second switching transistor M2 is connected to the clock signal output terminal CLK;
a control terminal of the third switching transistor M3 is connected to the first input terminal a, a first terminal of the third switching transistor M3 is connected to the clock signal output terminal CLK, and a second terminal of the third switching transistor M3 is connected to a first terminal of the fourth switching transistor M4;
a control terminal of the fourth switching transistor M4 is connected to the second input terminal B, and a second terminal of the fourth switching transistor M4 is connected to the second control module 2.
With continued reference to fig. 6, optionally, wherein the second control module 2 includes a fifth switching transistor M5, a sixth switching transistor M6, a third input terminal C, a fourth input terminal D, a second voltage signal terminal VGL, and a third voltage signal terminal VGLO;
a control terminal of the fifth switching transistor M5 is connected to the third input terminal C, a first terminal of the fifth switching transistor M5 is connected to the second terminal of the fourth switching transistor M4, and a second terminal of the fifth switching transistor M5 is connected to the second voltage signal terminal VGL;
a control terminal of the sixth switching transistor M6 is connected to the fourth input terminal D, a first terminal of the sixth switching transistor M6 is connected to the second terminal of the fourth switching transistor M4, and a second terminal of the sixth switching transistor M6 is connected to the third voltage signal terminal VGLO.
With continued reference to fig. 6, optionally, the first switching transistor M1 and the second switching transistor M2 are P-type MOS transistors, and the third switching transistor M3, the fourth switching transistor M4, the fifth switching transistor M5 and the sixth switching transistor M6 are N-type MOS transistors. Specifically, the MOS transistor is a Metal Oxide Semiconductor (Metal Oxide Semiconductor) field effect transistor. When a low potential signal is applied to the grid electrode of the P-type MOS tube, the P-type MOS tube is opened; and when a high potential signal is supplied to the N-type MOS tube, the N-type MOS tube is opened.
The first voltage signal terminal VGH inputs a first voltage signal, the second voltage signal terminal VGL inputs a second voltage signal, and the third voltage signal terminal VGLO inputs a third voltage signal.
When the first input terminal a inputs a low-potential signal, the second input terminal B inputs a low-potential signal, and the third input terminal C and the fourth input terminal D do not input signals, at this time, the first switching transistor M1 is turned on, the second switching transistor M2 is turned on, the third switching transistor M3, the fourth switching transistor M4, the fifth switching transistor M5, and the sixth switching transistor M6 are turned off, and the clock signal output terminal CLK outputs a first voltage signal.
When the first input terminal a inputs a low-level signal, the second input terminal B inputs a high-level signal, and the third input terminal C and the fourth input terminal D do not input signals, at this time, the first switching transistor M1 is turned on, the second switching transistor M2, the third switching transistor M3, the fourth switching transistor M4, the fifth switching transistor M5, and the sixth switching transistor M6 are turned off, and the clock signal output terminal CLK outputs a first voltage signal.
When a high-potential signal is input to the first input terminal a, a low-potential signal is input to the second input terminal B, and no signal is input to the third input terminal C and the fourth input terminal D, the second switching transistor M2 is turned on, the first switching transistor M1, the third switching transistor M3, the fourth switching transistor M4, the fifth switching transistor M5 and the sixth switching transistor M6 are turned off, and the clock signal output terminal CLK outputs a first voltage signal.
When a high-potential signal is input at the first input end a, a high-potential signal is input at the second input end B, a high-potential signal is input at the third input end C, and a low-potential signal is input at the fourth input end D, at this time, the first switching transistor M1 and the second switching transistor M2 are turned off, the third switching transistor M3, the fourth switching transistor M4 and the fifth switching transistor M5 are turned on, the sixth switching transistor M6 is turned off, and the clock signal output end CLK outputs a second voltage signal.
When a high-potential signal is input to the first input terminal a, a high-potential signal is input to the second input terminal B, a low-potential signal is input to the third input terminal C, and a high-potential signal is input to the fourth input terminal D, at this time, the first switching transistor M1 and the second switching transistor M2 are turned off, the third switching transistor M3, the fourth switching transistor M4 and the sixth switching transistor M6 are turned on, the fifth switching transistor M5 is turned off, and the clock signal output terminal CLK outputs a third voltage signal.
The clock signal output end CLK of the clock control circuit can be controlled to output a periodic pulse signal by controlling the first input end A, the second input end B, the third input end C and the fourth input end D, wherein the pulse signal comprises an enable signal and an overdrive signal with opposite potentials, and the clock signal output end outputs the overdrive signal when the enable signal is over in each period.
It should be noted that fig. 6 exemplarily shows specific structures of the first control module 1 and the second control module 2 in the clock control circuit, and the specific structures of the first control module 1 and the second control module 2 in the clock control circuit are not limited to the above structures provided in the embodiments of the present invention, and may also be other structures known by those skilled in the art, and are not described herein again.
It should be noted that, in the present embodiment, it is exemplarily shown that the first switching transistor M1 and the second switching transistor M2 are P-type MOS transistors, the third switching transistor M3, the fourth switching transistor M4, the fifth switching transistor M5 and the sixth switching transistor M6 are N-type MOS transistors, the first switching transistor M1, the second switching transistor M2, the third switching Transistor M3, the fourth switching Transistor M4, the fifth switching Transistor M5, and the sixth switching Transistor M6 may also be other types of switching transistors, for example, low temperature polysilicon Thin Film Transistors (TFTs), and it is only necessary that the threshold voltage of the first switching Transistor M1 and the threshold voltage of the third switching Transistor M3 are opposite numbers, and the threshold voltage of the second switching Transistor M2 and the threshold voltage of the fourth switching Transistor M4 are opposite numbers, which is not described herein again.
With reference to fig. 6, optionally, the first voltage signal input by the first voltage signal terminal VGH is a high voltage level, the second voltage signal input by the second voltage signal terminal VGL is a low voltage level, and the third voltage signal input by the third voltage signal terminal VGLO is a voltage level between the high voltage level and the low voltage level.
Illustratively, at normal temperature, the first voltage signal is 15V, the second voltage signal is-14V, the third voltage signal is-10V, at low temperature, the first voltage signal is 18V, the second voltage signal is-14V, and the third voltage signal is-10V.
It should be noted that, this embodiment only exemplifies that the first voltage signal input by the first voltage signal terminal VGH in the clock control circuit is at a high potential, the second voltage signal input by the second voltage signal terminal VGL is at a low potential, and the third voltage signal input by the third voltage signal terminal VGLO is at a potential between the high potential and the low potential, and a person skilled in the art can adjust the circuit of this embodiment according to different voltage signal input modes according to actual situations to achieve the same signal output by the circuit, and the circuit adjustment known to the person skilled in the art is within the protection scope of the embodiment of the present invention.
With continued reference to fig. 4, optionally, the enable signal is a high signal, and the overdrive signal is a low signal.
It should be noted that fig. 4 exemplarily shows that the enable signal is a high-potential signal, and the overdrive signal is a low-potential signal, in other embodiments of the present invention, the enable signal may be a low-potential signal, and the overdrive signal may be a high-potential signal, and it only needs to satisfy that the potentials of the enable signal and the overdrive signal are opposite, which is not described herein again.
Fig. 7 is a schematic structural diagram of another display panel provided in the present invention, and referring to fig. 6 and 7, optionally, the display panel further includes a driving chip 60;
the first input end a, the second input end B, the third input end C and the fourth input end D are all connected with the driving chip 60.
Specifically, the driving chip 60 may control the first input terminal a, the second input terminal B, the third input terminal C, and the fourth input terminal D of the clock control circuit 50, so as to control the clock signal output terminal CLK of the clock control circuit 50 to output a periodic pulse signal.
It should be noted that fig. 7 exemplarily shows that the clock control circuit 50 and the driving chip 60 are both disposed in the display panel, and the electrically connected clock control circuit 50 and the driving chip 60 are independently disposed, in other embodiments of the present invention, the clock control circuit 50 may also be integrated in the driving chip 60, and the clock control circuit 50 and the driving chip 60 may also not be disposed in the display panel, which is not described herein again.
With continued reference to fig. 4, optionally, wherein each overdrive signal has a duration T, and the interval between two adjacent enable signals is T; wherein the content of the first and second substances,
1.5us≤t≤T/2。
specifically, in each cycle T1, the second period T12 outputs the overdrive signal, the second period T12 is at T, and the time from the end of the first period T11 in the previous cycle T1 to the start of the first period T11 in the next cycle T1 is T; t is more than or equal to 1.5us and less than or equal to T/2. When t is less than 1.5us, the panel appears rolling horizontal stripes when displaying; when T > T/2, the overdrive signal affects the enable signal of the next period T1. When T is more than or equal to 1.5us and less than or equal to T/2, the phenomenon that the panel has rolling horizontal stripes during display due to too short overdrive signals is effectively solved while the overdrive signals do not influence the enable signals of the T1 in the next period.
Fig. 8 is a schematic structural diagram of another display panel provided in the present invention, and referring to fig. 8, the display panel further includes a plurality of data lines S10 extending along the second direction Y;
the two adjacent pixel columns 22 are one pixel column group 23, the data lines S10 and the pixel column group 23 are arranged in a one-to-one correspondence, and the pixels 30 in the same pixel column group 23 are electrically connected to the same data line S10.
Specifically, two adjacent pixel columns 22 are a pixel column group 23, and the pixels 30 in the same pixel column group 23 are electrically connected to the same data line S10, so that a data signal can be transmitted to the pixels 30 in the two pixel columns 22 through the data line S10, and the number of the data lines S10 in the display panel is effectively reduced, so that more spaces are provided in the display panel for placing other signal lines, and the circuit arrangement in the display panel is more flexible; and the cost of the driving circuit (not shown in fig. 8) connected to the data line S10 is reduced accordingly, which can reduce the production cost.
Fig. 9 is a schematic structural diagram of a portion E in fig. 8, and referring to fig. 8 and 9, alternatively, the pixel 30 includes a pixel electrode 31 and a thin film transistor 32, a gate 321 of the thin film transistor 32 is connected to the scan line G10, a source 322 of the thin film transistor 32 is connected to a data line S10 corresponding thereto, and a drain 323 of the thin film transistor 32 is connected to the pixel electrode 31.
Specifically, the gate 321 of the tft 32 of the sub-pixel 30 is connected to the corresponding scan line G10, the tft 32 is turned on by applying an enable signal to the tft 32 through the scan line G10, the corresponding pixel electrode 31 is charged through the data line S10, the pixel electrode 31 is turned from the initial potential to the target potential, the tft 32 is turned off by applying a drive signal to the tft 32 through the scan line G10, and the pixel electrode 31 is maintained at the target potential.
An embodiment of the present invention provides a display device, including the display panel 100 as described above.
Referring to fig. 10, fig. 10 is a schematic structural diagram of a display device according to the present invention. Fig. 10 provides a display device 1000 including the display panel 100 according to any of the above embodiments of the present invention. The embodiment of fig. 10 is only an example of a mobile phone, and the display device 1000 is described, but it should be understood that the display device 100 provided in the embodiment of the present invention may be other display devices having a display function, such as a computer, a television, and a vehicle-mounted display device, and the present invention is not limited thereto. The display device provided in the embodiment of the present invention has the beneficial effects of the display panel provided in the embodiment of the present invention, and specific reference may be made to the specific description of the display panel in each of the above embodiments, which is not repeated herein.
As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:
the shift register in the display panel is electrically connected with the scanning line, and the clock signal output end of the clock control circuit is electrically connected with the clock signal input end of the shift register, so that the periodic pulse signals output by the clock signal output end of the clock control circuit are sequentially transmitted to the scanning line through the shift register. A clock signal output end of the clock control circuit outputs periodic pulse signals to the shift register, in each period, the shift register transmits an enable signal to a certain scanning line in a first time interval so as to enable a thin film transistor of a pixel connected with the scanning line to be started, and the pixel is charged when the thin film transistor of the pixel is started so as to enable the pixel connected with the scanning line to display images; the shift register transmits the over-drive signal to the scanning line in the second period, the potentials of the enable signal and the over-drive signal are opposite, the over-drive signal enables the thin film transistor of the pixel connected with the scanning line to be closed, the clock signal output end outputs the over-drive signal when the enable signal is ended in each period, and the potential of the scanning line can be rapidly changed by the over-drive signal, so that the closing time of the thin film transistor of the pixel is reduced.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (9)
1. A display panel, comprising:
an array substrate;
a plurality of scanning line groups and a pixel array which are positioned on the array substrate;
the scanning line group comprises two scanning lines extending along a first direction;
the pixel array comprises a plurality of pixel rows and a plurality of pixel columns; wherein the pixel row includes a plurality of pixels arranged in the first direction, the pixel column includes a plurality of the pixels arranged in a second direction, and the first direction and the second direction intersect;
the pixel lines and the scanning line groups are arranged in a one-to-one correspondence manner, and in the same pixel line, two adjacent pixels are respectively and electrically connected with different scanning lines in the same scanning line group;
a shift register electrically connected to the scan line;
the clock signal output end of the clock control circuit is electrically connected with the clock signal input end of the shift register;
the clock control circuit comprises a first control module and a second control module which are electrically connected; the clock signal output end is electrically connected with the first control module; the first control module and the second control module are used for controlling the clock signal output end to output periodic pulse signals, the pulse signals comprise enable signals and over-drive signals with opposite potentials, and in each period, the clock signal output end outputs the over-drive signals when the enable signals are ended;
the first control module comprises a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first input end, a second input end, a first voltage signal end and the clock signal output end; the control end of the first switching transistor is connected with the first input end, the first end of the first switching transistor is connected with the first voltage signal end, and the second end of the first switching transistor is connected with the clock signal output end; the control end of the second switching transistor is connected with the second input end, the first end of the second switching transistor is connected with the first voltage signal end, and the second end of the second switching transistor is connected with the clock signal output end; the control end of the third switching transistor is connected with the first input end, the first end of the third switching transistor is connected with the clock signal output end, and the second end of the third switching transistor is connected with the first end of the fourth switching transistor; the control end of the fourth switching transistor is connected with the second input end, and the second end of the fourth switching transistor is connected with the second control module;
the second control module comprises a fifth switching transistor, a sixth switching transistor, a third input end, a fourth input end, a second voltage signal end and a third voltage signal end; a control end of the fifth switching transistor is connected with the third input end, a first end of the fifth switching transistor is connected with a second end of the fourth switching transistor, and a second end of the fifth switching transistor is connected with the second voltage signal end; the control end of the sixth switching transistor is connected with the fourth input end, the first end of the sixth switching transistor is connected with the second end of the fourth switching transistor, and the second end of the sixth switching transistor is connected with the third voltage signal end.
2. The display panel according to claim 1,
the first switch transistor and the second switch transistor are P-type MOS tubes, and the third switch transistor, the fourth switch transistor, the fifth switch transistor and the sixth switch transistor are N-type MOS tubes.
3. The display panel according to claim 1, further comprising a driving chip;
the first input end, the second input end, the third input end and the fourth input end are all connected with the driving chip.
4. The display panel according to claim 1,
the first voltage signal input by the first voltage signal end is at a high potential, the second voltage signal input by the second voltage signal end is at a low potential, and the third voltage signal input by the third voltage signal end is at a potential between the high potential and the low potential.
5. The display panel according to claim 1,
the enable signal is a high potential signal, and the overdrive signal is a low potential signal.
6. The display panel according to claim 3,
the duration of each overdrive signal is T, and the interval time between two adjacent enable signals is T; wherein the content of the first and second substances,
1.5us≤t≤T/2。
7. the display panel according to claim 1,
the data lines extend along the second direction;
two adjacent pixel columns are a pixel column group, the data lines and the pixel column group are arranged in a one-to-one correspondence mode, and the pixels in the same pixel column group are electrically connected with the same data line.
8. The display panel according to claim 7,
the pixel comprises a pixel electrode and a thin film transistor, the grid electrode of the thin film transistor is connected with the scanning line, the source electrode of the thin film transistor is connected with the corresponding data line, and the drain electrode of the thin film transistor is connected with the pixel electrode.
9. A display device characterized by comprising the display panel according to any one of claims 1 to 8.
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| CN110322827B (en) * | 2019-08-15 | 2022-05-10 | 成都辰显光电有限公司 | Digital driving method of display panel and display panel |
| CN110531557B (en) * | 2019-08-29 | 2021-12-10 | 上海中航光电子有限公司 | Array substrate, liquid crystal display panel and display device |
| CN111522161B (en) * | 2020-05-29 | 2021-09-17 | 厦门天马微电子有限公司 | Array substrate, display panel, display device and driving method |
| CN111766746B (en) * | 2020-06-24 | 2022-06-03 | 厦门天马微电子有限公司 | Display panel, driving method thereof and display device |
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