CN109658861A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN109658861A CN109658861A CN201910152126.3A CN201910152126A CN109658861A CN 109658861 A CN109658861 A CN 109658861A CN 201910152126 A CN201910152126 A CN 201910152126A CN 109658861 A CN109658861 A CN 109658861A
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- pixel
- signal
- switching transistor
- display panel
- transistor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a kind of display panel and display devices, comprising: array substrate；Multiple scanline groups and pixel array in array substrate；Scanline groups include two scan lines extended in a first direction；Pixel array includes multiple pixel columns and multiple pixel columns；Pixel column and scanline groups are arranged in a one-to-one correspondence, and in same pixel column, different from the same scanline groups scan line electrical connections respectively of two neighboring pixel；The shift register being electrically connected with scan line；Clock control circuit, the clock signal input terminal electrical connection of the clock signal output terminal and shift register of clock control circuit；The clock signal output terminal of clock control circuit exports periodically pulsing signal, and pulse signal includes the opposite enable signal of current potential and crosses drive signal, and in each cycle, clock signal output terminal exported drive signal at the end of enable signal.The problem of being effectively improved pixel undercharge effectively improves the display effect of display panel.
Description
Technical field
The present invention relates to field of display technology, more particularly, to a kind of display panel and display device.
Background technique
A kind of existing display panel, including multi-strip scanning line, multiple data lines, multiple pixels and shift register move
Bit register is electrically connected with scan line.Shift register is used to be sequentially output scanning signal, data line output to multi-strip scanning line
Data drive signal, so that the pixel that driving is electrically connected with scan line, data line carries out the display of image.
Existing display panel generally comprises the working method of single grid driving, double grid driving and the driving of three grid, most common
For first two.Wherein, double grid driving refers to that every row pixel passes through two scanning line traffic controls in display panel.What the prior art provided
The case where there are the charging ability of pixel and poor display effects in the display panel of double grid driving.Therefore it provides a kind of display
The good display panel of effect and display device are this field technical problems urgently to be resolved.
Summary of the invention
In view of this, the present invention provides a kind of display panels, comprising: array substrate；It is multiple in array substrate
Scanline groups and pixel array；Scanline groups include two scan lines extended in a first direction；Pixel array includes multiple pictures
Plain row and multiple pixel columns；Wherein, pixel column includes multiple pixels arranged in the first direction, and pixel column includes in a second direction
Multiple pixels of arrangement, first direction and second direction intersection；Pixel column and scanline groups are arranged in a one-to-one correspondence, and same pixel
In row, different from the same scanline groups scan line electrical connections respectively of two neighboring pixel；The displacement being electrically connected with scan line
Register；Clock control circuit, the clock signal output terminal of clock control circuit and the clock signal input terminal of shift register
Electrical connection；The clock signal output terminal of clock control circuit exports periodically pulsing signal, and pulse signal includes that current potential is opposite
Enable signal and cross drive signal, in each cycle, clock signal output terminal exported drive signal at the end of enable signal.
The present invention also provides a kind of display devices, including display panel provided by the invention.
Compared with prior art, display panel provided by the invention and display device at least realize following beneficial effect
Fruit:
Shift register is electrically connected with scan line in display panel, the clock signal output terminal of clock control circuit and displacement
The clock signal input terminal of register is electrically connected, thus the periodic arteries and veins that the clock signal output terminal of clock control circuit exports
It rushes signal and scan line is successively transferred to by shift register.The clock signal output terminal output of clock control circuit is periodic
Pulse signal is to shift register, and in each period, enable signal is transmitted to a certain scanning in the first period by shift register
Line is filled when the thin film transistor (TFT) of pixel is opened to pixel so that the thin film transistor (TFT) for the pixel being connected with the scan line is opened
Electricity, the pixel for keeping the scan line connected carry out the display of image；Shift register is transmitted to this for drive signal is crossed in the second period
Scan line, enable signal and the current potential for driving signal excessively make the film crystal for the pixel being connected with the scan line on the contrary, mistake drives signal
Pipe is closed, and in each cycle, clock signal output terminal exported drive signal at the end of enable signal, and crossing drive signal can be quick
Change the current potential of scan line, so that the shut-in time of the thin film transistor (TFT) of pixel is reduced, due in the thin film transistor (TFT) pass of pixel
It can not charge to pixel when closing, the shut-in time for reducing the thin film transistor (TFT) of pixel can increase in the first period to pixel charging
Time, effectively improves the display effect of display panel at the problem of being effectively improved pixel undercharge.
Certainly, implementing any of the products of the present invention specific needs while need not reach all the above technical effect.
By referring to the drawings to the detailed description of exemplary embodiment of the present invention, other feature of the invention and its
Advantage will become apparent.
Detailed description of the invention
It is combined in the description and the attached drawing for constituting part of specification shows the embodiment of the present invention, and even
With its explanation together principle for explaining the present invention.
Fig. 1 is the structural schematic diagram of display panel described in the prior art；
Fig. 2 is the signal timing diagram of the clock signal input terminal of shift register in display panel described in Fig. 1；
Fig. 3 is a kind of structural schematic diagram of display panel provided by the invention；
Fig. 4 is a kind of signal timing diagram of the clock signal input terminal of shift register in display panel described in Fig. 3；
Fig. 5 is a kind of structural schematic diagram of clock control circuit provided by the invention；
Fig. 6 is the structural schematic diagram of another clock control circuit provided by the invention；
Fig. 7 is the structural schematic diagram of another display panel provided by the invention；
Fig. 8 is the structural schematic diagram of another display panel provided by the invention；
Fig. 9 is the structural schematic diagram in the portion E in Fig. 8；
Figure 10 is a kind of structural schematic diagram of display device provided by the invention.
Specific embodiment
Carry out the various exemplary embodiments of detailed description of the present invention now with reference to attached drawing.It should also be noted that unless in addition having
Body explanation, the unlimited system of component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
The range of invention.
Be to the description only actually of at least one exemplary embodiment below it is illustrative, never as to the present invention
And its application or any restrictions used.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of, the technology, method and apparatus should be considered as part of specification.
It is shown here and discuss all examples in, any occurrence should be construed as merely illustratively, without
It is as limitation.Therefore, other examples of exemplary embodiment can have different values.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, then in subsequent attached drawing does not need that it is further discussed.
In the display panel provided for the prior art the phenomenon that the charging ability and poor display effect of pixel, inventor
The display panel provided for the prior art carries out the following studies:
Fig. 1 is the structural schematic diagram of display panel described in the prior art, and Fig. 2 is shifted in display panel described in Fig. 1
The signal timing diagram of the clock signal input terminal of register, with reference to Fig. 1 and Fig. 2, display panel includes: array substrate 1；Positioned at battle array
Multiple scanline groups 5 and pixel array 2 on column substrate 1；Scanline groups 5 include two scan lines extended along first direction X
6；Pixel array 2 includes multiple pixel columns 3 and multiple pixel columns 4；Wherein, pixel column 3 includes along the multiple of first direction X arrangement
Pixel 8, pixel column 4 include multiple pixels 8 of Y arrangement in a second direction, first direction X and second direction Y intersection；Pixel column 3
Be arranged in a one-to-one correspondence with scanline groups 5, and in same pixel column 3, two neighboring pixel 8 respectively in same scanline groups 5 not
Same scan line 6 is electrically connected；The shift register 7 being electrically connected with scan line 6.
In the display panel that the prior art provides, the periodic driving signal of shift register 7 is given, in each period t1,
The high level that clock signal input terminal inputs is transmitted to certain scan line 6 in the first period t11 by shift register 7, so that with
The thin film transistor (TFT) of the connected pixel 8 of the scan line 6 is opened, and the pixel 8 being connected with the scan line 6 is driven to carry out the aobvious of image
Show；The backward scan line 6 transmission pulldown signal to pull down the current potential of the scan line 6 make the pixel 8 being connected with the scan line 6
Thin film transistor (TFT) close.Due to shift register 7 in the prior art can not quick pull-down scan line 6 current potential, every
And then there is the second period t12 in one period t1 after first period t11, in the second period t12, shift register 7 is gradually
The current potential of scan line 6 is pulled down, until the current potential of scan line 6 is low potential.The time of each period t1 is typically set at fixed value,
The presence of second period t12 reduces the time of the first period t11, due to only having the first period t11 can in each period t1
To charge to corresponding pixel 8, the second period t12 can not charge to corresponding pixel 8, so that there are undercharges for pixel 8
Problem influences the display of display panel.
And the display panel that the prior art provides is driven using double grid, i.e., is driven by two scan lines 6 in scanline groups 5
Pixel 8 in dynamic pixel column 3 corresponding with the scanline groups 5, due to scan line 6 in the display panel of the prior art quantity compared with
It is more, therefore the time of each period t1 accordingly reduces, exacerbating pixel 8 has undercharge, further influences display
The display of panel.
In view of this, the present invention provides a kind of display panel and display device, to solve the display of prior art proposition
In panel the problem of the charging ability and poor display effect of pixel.About display panel provided in an embodiment of the present invention and display
The embodiment of device, is discussed further below.
Fig. 3 is a kind of structural schematic diagram of display panel provided by the invention, and Fig. 4 is moved in display panel described in Fig. 3
A kind of signal timing diagram of the clock signal input terminal of bit register, with reference to Fig. 3 and Fig. 4, the present embodiment provides a kind of display surfaces
Plate, comprising:
Array substrate 10；
Multiple scanline groups G1 and pixel array 20 in array substrate 10；
Scanline groups G1 includes the two scan line G10 extended along first direction X；
Pixel array 20 includes multiple pixel columns 21 and multiple pixel columns 22；Wherein, pixel column 21 includes along first direction X
Multiple pixels 30 of arrangement, pixel column 22 include multiple pixels 30 of Y arrangement in a second direction, first direction X and second direction Y
Intersection；
Pixel column 21 and scanline groups G1 are arranged in a one-to-one correspondence, and in same pixel column 21, and two neighboring pixel 30 is distinguished
The scan line G10 electrical connection different from same scanline groups G1；
The shift register 40 being electrically connected with scan line G10；
Clock control circuit 50, the clock signal output terminal of clock control circuit 50 and the clock signal of shift register 40
Input terminal electrical connection；
The clock signal output terminal of clock control circuit 50 exports periodically pulsing signal, and pulse signal includes current potential phase
Anti- enable signal and drive signal excessively, in each cycle, clock signal output terminal exported drive letter at the end of enable signal
Number.
Specifically, scanline groups G1 and pixel array are provided in display panel provided in this embodiment in array substrate 10
20, pixel array 20 is formed by multiple 30 array arrangements of pixel, and pixel column 21 and scanline groups G1 are arranged in a one-to-one correspondence, and same
Pixel 30 in one pixel column 21 passes through two scan line G10 drivings in corresponding scanline groups G1.
Shift register 40 is electrically connected with scan line G10, and the clock signal output terminal of clock control circuit 50 and displacement are posted
The clock signal input terminal of storage 40 is electrically connected, thus the clock signal output terminal of clock control circuit 50 export it is periodic
Pulse signal is successively transferred to scan line G10 by shift register 40.The clock signal output terminal of clock control circuit 50 is defeated
Periodically pulsing signal is to shift register 40 out, and in each cycle T 1, shift register 40 will be enabled in the first period T11
Signal is transmitted to certain scan line G10, so as to open with the thin film transistor (TFT) of the scan line G10 pixel 30 being connected, in pixel
It charges when 30 thin film transistor (TFT) is opened to pixel 30, the pixel 30 for keeping scan line G10 connected carries out the display of image；Displacement
Register 40 will cross drive signal in the second period T12 and be transmitted to scan line G10, enable signal and the current potential phase for crossing drive signal
Instead, drive signal makes excessively and the thin film transistor (TFT) of the scan line G10 pixel 30 being connected is closed, in each cycle T 1, clock letter
Number output end exported drive signal at the end of enable signal, crosses and drives signal and can quickly change the current potential of scan line G10, to subtract
The shut-in time of the thin film transistor (TFT) of few pixel 30, due to that can not be filled to pixel 30 in the thin film transistor (TFT) closing of pixel 30
Electricity, the shut-in time for reducing the thin film transistor (TFT) of pixel 30 can increase the time charged in the first period T11 to pixel 30, effectively
The problem of improving 30 undercharge of pixel, effectively improve the display effect of display panel.
It should be noted that enable signal refers to enable signal with the current potential for crossing drive signal on the contrary and crosses drive letter in the present invention
One is high potential signal in number, another is low-potential signal, and illustratively, the current potential of enable signal is 15V, crosses drive signal
Current potential be -14V, the present invention in do not limit enable signal and cross drive the potential value of signal it is opposite.
The thin film transistor (TFT) that signal makes pixel 30 is driven it should be noted that illustratively showing in the present embodiment
Shut-in time is close to 0, to can charge close in entire first period T11 to pixel 30.In other implementations of the present invention
It is not entire first period T11 there are the closing that part-time makes the thin film transistor (TFT) of pixel 30 in the first period T11 in example
It all charges to pixel 30, but compared with prior art, spends the shut-in time for driving the thin film transistor (TFT) that signal effectively makes pixel 30
The problem of shortening, being effectively improved 30 undercharge of pixel, effectively improves the display effect of display panel, the present invention no longer goes to live in the household of one's in-laws on getting married
It states.
Fig. 5 is a kind of structural schematic diagram of clock control circuit provided by the invention, with reference to Fig. 5, optionally, wherein when
Clock control circuit includes the first control module 51 and the second control module 52 of electrical connection；
Clock signal output terminal CLK is electrically connected with the first control module 51；
First control module 51 and the second control module 52 are for controlling the periodic arteries and veins of clock signal output terminal CLK output
Rush signal.
Fig. 6 is the structural schematic diagram of another clock control circuit provided by the invention, with reference to Fig. 6, optionally, wherein
First control module 1 includes first switch transistor M1, second switch transistor M2, third switching transistor M3, the 4th switch
Transistor M4, first input end A, the second input terminal B, first voltage signal end VGH and clock signal output terminal CLK；
The control terminal of first switch transistor M1 is connected with first input end A, the first end of first switch transistor M1
It is connected with first voltage signal end VGH, the second end of first switch transistor M1 is connected with clock signal output terminal CLK；
The control terminal of second switch transistor M2 is connected with the second input terminal B, the first end of second switch transistor M2
It is connected with first voltage signal end VGH, the second end of second switch transistor M2 is connected with clock signal output terminal CLK；
The control terminal of third switching transistor M3 is connected with first input end A, the first end of third switching transistor M3
It is connected with clock signal output terminal CLK, the second end of third switching transistor M3 and the first end of the 4th switching transistor M4
It is connected；
The control terminal of 4th switching transistor M4 is connected with the second input terminal B, the second end of the 4th switching transistor M4
It is connected with the second control module 2.
With continued reference to Fig. 6, optionally, wherein the second control module 2 includes the 5th switching transistor M5, the 6th switch crystalline substance
Body pipe M6, third input terminal C, the 4th input terminal D, second voltage signal end VGL and tertiary voltage signal end VGLO；
The control terminal of 5th switching transistor M5 is connected with third input terminal C, the first end of the 5th switching transistor M5
It is connected with the second end of the 4th switching transistor M4, the second end and second voltage signal end VGL of the 5th switching transistor M5
It is connected；
The control terminal of 6th switching transistor M6 is connected with the 4th input terminal D, the first end of the 6th switching transistor M6
It is connected with the second end of the 4th switching transistor M4, the second end and tertiary voltage signal end VGLO of the 6th switching transistor M6
It is connected.
With continued reference to Fig. 6, optionally, wherein first switch transistor M1 and second switch transistor M2 is p-type metal-oxide-semiconductor,
Third switching transistor M3, the 4th switching transistor M4, the 5th switching transistor M5 and the 6th switching transistor M6 are N-type MOS
Pipe.Specifically, metal-oxide-semiconductor is metal-oxide semiconductor (MOS) (Metal Oxide Semiconductor) field effect transistor.Its
In, when leading to low-potential signal to the grid of p-type metal-oxide-semiconductor, p-type metal-oxide-semiconductor is opened；When leading to high potential signal to N-type metal-oxide-semiconductor, N-type
Metal-oxide-semiconductor is opened.
First voltage signal end VGH inputs first voltage signal, and second voltage signal end VGL inputs second voltage signal,
Tertiary voltage signal end VGLO inputs tertiary voltage signal.
When first input end A inputs low-potential signal, the second input terminal B input low-potential signal, third input terminal C and the
Four input terminal D not input signal, at this point, first switch transistor M1 is opened, second switch transistor M2 is opened, and third switch is brilliant
Body pipe M3, the 4th switching transistor M4, the 5th switching transistor M5 and the 6th switching transistor M6 are closed, clock signal output terminal
CLK exports first voltage signal.
When first input end A inputs low-potential signal, the second input terminal B input high potential signal, third input terminal C and the
Four input terminal D not input signal, at this point, first switch transistor M1 is opened, second switch transistor M2, third switching transistor
M3, the 4th switching transistor M4, the 5th switching transistor M5 and the 6th switching transistor M6 are closed, clock signal output terminal CLK
Export first voltage signal.
When first input end A inputs high potential signal, the second input terminal B input low-potential signal, third input terminal C and the
Four input terminal D not input signal, at this point, second switch transistor M2 is opened, first switch transistor M1, third switching transistor
M3, the 4th switching transistor M4, the 5th switching transistor M5 and the 6th switching transistor M6 are closed, clock signal output terminal CLK
Export first voltage signal.
When first input end A inputs high potential signal, the second input terminal B input high potential signal, third input terminal C input
High potential signal, the 4th input terminal D input low-potential signal, at this point, first switch transistor M1 and second switch transistor M2
It closes, third switching transistor M3, the 4th switching transistor M4 and the 5th switching transistor M5 are opened, the 6th switching transistor M6
It closes, clock signal output terminal CLK exports second voltage signal.
When first input end A inputs high potential signal, the second input terminal B input high potential signal, third input terminal C input
Low-potential signal, the 4th input terminal D input high potential signal, at this point, first switch transistor M1 and second switch transistor M2
It closes, third switching transistor M3, the 4th switching transistor M4 and the 6th switching transistor M6 are opened, the 5th switching transistor M5
It closes, clock signal output terminal CLK exports tertiary voltage signal.
Pass through clock when control first input end A, the second input terminal B, third input terminal C and the 4th input terminal D controllable
The clock signal output terminal CLK of circuit processed exports periodically pulsing signal, wherein pulse signal, which includes that current potential is opposite, to be enabled
Signal and excessively drive signal, in each cycle, clock signal output terminal exported drive signal at the end of enable signal.
It should be noted that Fig. 6 illustratively shows the first control module 1 and the second control mould in clock control circuit
The specific structure of block 2, the specific structure of the first control module 1 and the second control module 2 is not limited to this hair in clock control circuit
The above structure that bright embodiment provides, can also be skilled person will appreciate that other structures, therefore not to repeat here.
It should be noted that the present embodiment exemplary shows first switch transistor M1 and second switch transistor M2
For p-type metal-oxide-semiconductor, third switching transistor M3, the 4th switching transistor M4, the 5th switching transistor M5 and the 6th switching transistor
M6 is N-type metal-oxide-semiconductor, first switch transistor M1, second switch transistor M2, third switching transistor M3, the 4th switch crystal
Pipe M4, the 5th switching transistor M5 and the 6th switching transistor M6 can also use other kinds of switching transistor, exemplary
, or low-temperature polysilicon film transistor (TFT, Thin Film Transistor) need to only meet first switch crystalline substance
The threshold voltage of the threshold voltage of body pipe M1 and third switching transistor M3 opposite number each other, the threshold value of second switch transistor M2
The threshold voltage of voltage and the 4th switching transistor M4 opposite number each other, therefore not to repeat here by the present invention.
With continued reference to Fig. 6, optionally, wherein the first voltage signal of first voltage signal end VGH input is high potential,
The second voltage signal of second voltage signal end VGL input is low potential, the tertiary voltage of tertiary voltage signal end VGLO input
Signal is the current potential between high potential and low potential.
Illustratively, at room temperature, first voltage signal is 15V, and second voltage signal is -14V, tertiary voltage signal
For -10V, in low temperature, first voltage signal is 18V, and second voltage signal is -14V, and tertiary voltage signal is -10V, at this
In invention other embodiments, first voltage signal, second voltage signal and tertiary voltage signal can also be according to actual production need
Other voltage values are designed as, the present invention is not limited this.
It is inputted it should be noted that the present embodiment is merely illustrative of first voltage signal end VGH in clock control circuit
First voltage signal be high potential, second voltage signal end VGL input second voltage signal be low potential, tertiary voltage letter
The tertiary voltage signal of number end VGLO input is current potential between high potential and low potential, and those skilled in the art can basis
Actual conditions are adjusted the circuit of the present embodiment for different voltage signal input modes, to realize and the circuit output
Identical signal, above well known to a person skilled in the art the regulation of electrical circuit within protection scope of the embodiment of the present invention.
With continued reference to Fig. 4, optionally, wherein enable signal is high potential signal, and crossing drive signal is low-potential signal.
It should be noted that it is high potential signal that Fig. 4, which illustratively shows enable signal, drive signal is crossed as low potential letter
Number, enable signal can be low-potential signal in other embodiments of the present invention, and crossing drive signal can be high potential signal, only need
It is opposite with the drive current potential of signal is crossed to meet enable signal, therefore not to repeat here.
Fig. 7 is the structural schematic diagram of another display panel provided by the invention, with reference to Fig. 6 and Fig. 7, optionally, display
Panel further includes driving chip 60；
First input end A, the second input terminal B, third input terminal C and the 4th input terminal D are connect with driving chip 60.
Specifically, can by driving chip 60 control clock control circuit 50 in first input end A, the second input terminal B,
Third input terminal C and the 4th input terminal D, to control the clock signal output terminal CLK output of clock control circuit 50 periodically
Pulse signal.
It should be noted that illustratively show clock control circuit 50 in Fig. 7 and driving chip 60 be all set in it is aobvious
Show in panel, and the clock control circuit 50 and driving chip 60 that are electrically connected are independently arranged, in other embodiments of the present invention, also
Clock control circuit 50 can be integrated in driving chip 60, clock control circuit 50 and driving chip 60 can also be not provided with
In display panel, therefore not to repeat here by the present invention.
With continued reference to Fig. 4, optionally, wherein each duration for crossing drive signal is t, two neighboring enable signal
Between interval time be T；Wherein,
1.5us≤t≤T/2。
Specifically, second period T12 exported drive signal, and the time of the second period T12 is t, previous in each cycle T 1
Time of the end of first period T11 into the latter cycle T 1 between the beginning of first period T11 is T in a cycle T 1；
1.5us≤t≤T/2.As t < 1.5us, panel occurs rolling band in display；As t > T/2, crossing drive signal be will affect
The enable signal of next cycle T 1.As 1.5us≤t≤T/2, the enable signal of one cycle T 1 under the influence of crossing drive signal not
Meanwhile effectively solved drive signal it is too short caused by panel there is the phenomenon that rolling band in display.
Fig. 8 is the structural schematic diagram of another display panel provided by the invention, and with reference to Fig. 8, optionally, display panel is also
The multiple data lines S10 extended including Y in a second direction；
Two adjacent pixel columns 22 are a pixel column groups 23, and data line S10 and pixel column groups 23 are arranged in a one-to-one correspondence,
And the pixel 30 in the same pixel column groups 23 is electrically connected with same data line S10.
Specifically, two adjacent pixel columns 22 are a pixel column groups 23, and the pixel in the same pixel column groups 23
30 are electrically connected with same data line S10, can transmit number to the pixel 30 in two pixel columns 22 by a data line S10
It is believed that number, the quantity of data line S10 in display panel is effectively reduced, to there are more spaces to place other signals in display panel
Line, so that the trace arrangements in display panel are more flexible；And connect data line S10 driving circuit (being not shown in Fig. 8) at
This also corresponding reduction, can reduce production cost.
Fig. 9 is the structural schematic diagram in the portion E in Fig. 8, with reference to Fig. 8 and Fig. 9, optionally, wherein pixel 30 includes pixel electrode
31 and thin film transistor (TFT) 32, the grid 321 of thin film transistor (TFT) 32 connect with scan line G10,322 He of source electrode of thin film transistor (TFT) 32
Data line S10 connection corresponding thereto, the drain electrode 323 of thin film transistor (TFT) 32 are connect with pixel electrode 31.
Specifically, the grid 321 of the thin film transistor (TFT) 32 of sub-pixel 30 is connected to scan line G10 corresponding thereto, lead to
It over-scans line G10 and leads to enable signal to thin film transistor (TFT) 32, so that thin film transistor (TFT) 32 is in the conductive state, then pass through data line
S10 charges to corresponding pixel electrode 31, so that the pixel electrode 31 is reached target potential from initial potential, then pass through scan line
G10, by driving signal, is in close state thin film transistor (TFT) 32, pixel electrode 31 keeps target electricity to thin film transistor (TFT) 32
Position.
The embodiment of the present invention provides a kind of display device, including display panel as described above 100.
Referring to FIG. 10, Figure 10 is a kind of structural schematic diagram of display device provided by the invention.The display that Figure 10 is provided
Device 1000 includes the display panel 100 that any of the above-described embodiment of the present invention provides.Figure 10 embodiment only takes the mobile phone as an example, to aobvious
Showing device 1000 is illustrated, it is to be understood that display device 100 provided in an embodiment of the present invention can be computer, electricity
This is not specifically limited depending on other display devices having a display function, the present invention such as, display device for mounting on vehicle.The present invention is implemented
The display device that example provides, the beneficial effect with display panel provided in an embodiment of the present invention specifically can be with reference to above-mentioned each
Embodiment is illustrated for display panel, and details are not described herein for the present embodiment.
Through the foregoing embodiment it is found that display panel provided by the invention and display device, at least realizing following has
Beneficial effect:
Shift register is electrically connected with scan line in display panel, the clock signal output terminal of clock control circuit and displacement
The clock signal input terminal of register is electrically connected, thus the periodic arteries and veins that the clock signal output terminal of clock control circuit exports
It rushes signal and scan line is successively transferred to by shift register.The clock signal output terminal output of clock control circuit is periodic
Pulse signal is to shift register, and in each period, enable signal is transmitted to a certain scanning in the first period by shift register
Line is filled when the thin film transistor (TFT) of pixel is opened to pixel so that the thin film transistor (TFT) for the pixel being connected with the scan line is opened
Electricity, the pixel for keeping the scan line connected carry out the display of image；Shift register is transmitted to this for drive signal is crossed in the second period
Scan line, enable signal and the current potential for driving signal excessively make the film crystal for the pixel being connected with the scan line on the contrary, mistake drives signal
Pipe is closed, and in each cycle, clock signal output terminal exported drive signal at the end of enable signal, and crossing drive signal can be quick
Change the current potential of scan line, so that the shut-in time of the thin film transistor (TFT) of pixel is reduced, due in the thin film transistor (TFT) pass of pixel
It can not charge to pixel when closing, the shut-in time for reducing the thin film transistor (TFT) of pixel can increase in the first period to pixel charging
Time, effectively improves the display effect of display panel at the problem of being effectively improved pixel undercharge.
Although some specific embodiments of the invention are described in detail by example, the skill of this field
Art personnel it should be understood that example above merely to being illustrated, the range being not intended to be limiting of the invention.The skill of this field
Art personnel are it should be understood that can without departing from the scope and spirit of the present invention modify to above embodiments.This hair
Bright range is defined by the following claims.
Claims (12)
1. a kind of display panel characterized by comprising
Array substrate；
Multiple scanline groups and pixel array in the array substrate；
The scanline groups include two scan lines extended in a first direction；
The pixel array includes multiple pixel columns and multiple pixel columns；Wherein, the pixel column includes along the first direction
Multiple pixels of arrangement, the pixel column include the multiple pixels arranged in a second direction, the first direction and described
Second direction intersection；
The pixel column and the scanline groups are arranged in a one-to-one correspondence, and in the same pixel column, the two neighboring pixel
The scan line different from same scanline groups electrical connection respectively；
The shift register being electrically connected with the scan line；
The clock signal of clock control circuit, the clock signal output terminal of the clock control circuit and the shift register is defeated
Enter end electrical connection；
The clock signal output terminal of the clock control circuit exports periodically pulsing signal, and the pulse signal includes
The opposite enable signal of current potential and excessively drive signal, in each cycle, the clock signal output terminal is in the enable signal knot
The drive signal excessively is exported when beam.
2. display panel according to claim 1, which is characterized in that
The clock control circuit includes the first control module and the second control module of electrical connection；
The clock signal output terminal is electrically connected with first control module；
First control module and second control module are periodic for controlling the clock signal output terminal output
Pulse signal.
3. display panel according to claim 2, which is characterized in that
First control module includes first switch transistor, second switch transistor, third switching transistor, the 4th switch
Transistor, first input end, the second input terminal, first voltage signal end and the clock signal output terminal；
The control terminal of the first switch transistor is connected with the first input end, and the first of the first switch transistor
End is connected with the first voltage signal end, the second end of the first switch transistor and the clock signal output terminal phase
Connection；
The control terminal of the second switch transistor is connected with second input terminal, and the first of the second switch transistor
End is connected with the first voltage signal end, the second end of the second switch transistor and the clock signal output terminal phase
Connection；
The control terminal of the third switching transistor is connected with the first input end, and the first of the third switching transistor
End is connected with the clock signal output terminal, the second end of the third switching transistor and the 4th switching transistor
First end is connected；
The control terminal of 4th switching transistor is connected with second input terminal, and the second of the 4th switching transistor
End is connected with second control module.
4. display panel according to claim 3, which is characterized in that
Second control module include the 5th switching transistor, the 6th switching transistor, third input terminal, the 4th input terminal,
Second voltage signal end and tertiary voltage signal end；
The control terminal of 5th switching transistor is connected with the third input terminal, and the first of the 5th switching transistor
End is connected with the second end of the 4th switching transistor, the second end and the second voltage of the 5th switching transistor
Signal end is connected；
The control terminal of 6th switching transistor is connected with the 4th input terminal, and the first of the 6th switching transistor
End is connected with the second end of the 4th switching transistor, the second end of the 6th switching transistor and the tertiary voltage
Signal end is connected.
5. display panel according to claim 4, which is characterized in that
The first switch transistor and the second switch transistor are p-type metal-oxide-semiconductor, the third switching transistor, described
4th switching transistor, the 5th switching transistor and the 6th switching transistor are N-type metal-oxide-semiconductor.
6. display panel according to claim 4, which is characterized in that the display panel further includes driving chip；
The first input end, second input terminal, the third input terminal and the 4th input terminal with the driving
Chip connection.
7. display panel according to claim 4, which is characterized in that
The first voltage signal of the first voltage signal end input is high potential, the second of the second voltage signal end input
Voltage signal is low potential, and the tertiary voltage signal of tertiary voltage signal end input is between the high potential and described low
Current potential between current potential.
8. display panel according to claim 1, which is characterized in that
The enable signal is high potential signal, and the drive signal of crossing is low-potential signal.
9. display panel according to claim 6, which is characterized in that
Each described duration for crossing drive signal is t, and the interval time between the two neighboring enable signal is T；Its
In,
1.5us≤t≤T/2。
10. display panel according to claim 1, which is characterized in that
It further include the multiple data lines extended along the second direction；
Two adjacent pixels are classified as a pixel column groups, and the data line and the pixel column groups are arranged in a one-to-one correspondence,
And the pixel in the same pixel column groups is electrically connected with data line described in same.
11. display panel according to claim 10, which is characterized in that
The pixel includes pixel electrode and thin film transistor (TFT), and the grid of the thin film transistor (TFT) is connect with the scan line, institute
The source electrode for stating thin film transistor (TFT) is connected with data line corresponding thereto, the drain electrode of the thin film transistor (TFT) and the pixel electrode
Connection.
12. a kind of display device, which is characterized in that including the described in any item display panels of claim 1-11.
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| CN201910152126.3A CN109658861B (en) | 2019-02-28 | 2019-02-28 | Display panel and display device |
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| CN201910152126.3A CN109658861B (en) | 2019-02-28 | 2019-02-28 | Display panel and display device |
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| CN109658861B (en) | 2021-12-03 |
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