CN107180788A - 元件芯片的制造方法 - Google Patents
元件芯片的制造方法 Download PDFInfo
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- CN107180788A CN107180788A CN201710082554.4A CN201710082554A CN107180788A CN 107180788 A CN107180788 A CN 107180788A CN 201710082554 A CN201710082554 A CN 201710082554A CN 107180788 A CN107180788 A CN 107180788A
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Dicing (AREA)
- Plasma Technology (AREA)
- Drying Of Semiconductors (AREA)
Abstract
提供一种元件芯片的制造方法,抑制拾取时元件芯片的破裂。元件芯片的制造方法包括载置工序和等离子体切割工序。载置工序,将具备第1主面以及第2主面、并且具备多个元件区域以及划定元件区域的分割区域、并且形成了在元件区域中覆盖第1主面在分割区域中使第1主面露出的掩模的具有可挠性的半导体基板载置到载置台。等离子体切割工序,在载置台上将半导体基板的第1主面侧暴露于等离子体,从而在分割区域形成槽并且进行蚀刻,由此将半导体基板单片化为具备元件区域的多个元件芯片。半导体基板的厚度小于保持片的厚度。在等离子体切割工序中,在使槽的底部总是露出的状态下进行蚀刻,从而在元件芯片的侧面不形成扇形凹凸地将半导体基板单片化。
Description
技术领域
本公开涉及在侧面没有通过重复蚀刻和保护膜的沉积而形成的扇形凹凸(scallop)(阶梯)的元件芯片的制造方法。
背景技术
以往,在等离子体处理中,通过等离子体蚀刻将半导体基板单片化来制造元件芯片时,采用了能够进行深挖加工的所谓波希(Bosch)法(也称为TDM法)(例如,专利文献1)。在该工艺中,依次重复多次:在保持在切割胶带等保持片的半导体基板的表面沉积保护膜的工序、除去保护膜的一部分的工序、和在除去了保护膜的区域中对半导体基板进行等离子体蚀刻的工序。
图5是示意性表示Bosch法的切割过程的概略剖视图。在Bosch工序中,首先,在一个主面(第2主面)被保持在保持片302的基材层302b上的粘合剂层302a上的半导体基板303的另一个主面(第1主面)形成掩模301(a)。掩模301形成为覆盖半导体基板303的第1主面具备的多个元件区域、并且露出分割多个元件区域的分割区域。通过各向同性的等离子体蚀刻从第1主面侧蚀刻分割区域,来形成槽304(b)。通过等离子体CVD在第1主面侧形成保护膜305(c),通过各向异性的等离子体蚀刻,主要从槽304的底部除去保护膜305(d)。进而,通过进行各向同性的等离子体蚀刻,从而对槽304在深度方向上挖入(e)。而且,通过依次重复(c)(d)以及(e),从而将槽304从第1主面侧挖入到第2主面,从而除去分割区域,使半导体基板单片化(切割)。以这种方式,得到具备元件区域的元件芯片(f)。
如此,在Bosch法中,通过重复保护膜305向半导体基板的表面(也包含槽的表面)的形成、槽304的底部的保护膜305的除去、和各向同性的等离子体蚀刻,从而进行深度方向的深挖。但是,在通过各向同性的等离子体蚀刻在深度方向上挖入时,在水平方向上也进行蚀刻,所以若重复保护膜305的形成、保护膜305的除去以及等离子体蚀刻,则如图5所示,在槽304的侧壁(也就是说,元件芯片306的侧面),必然会形成横条状的凹凸(扇形凹凸S)。
现有技术文献
专利文献
专利文献1:JP特开2014-513868号公报
发明内容
在Bosch法中,消除扇形凹凸是困难的。若存在扇形凹凸,则有可能以扇形凹凸为起点而在元件芯片产生破裂。
本公开所涉及的发明的目的是提供一种运输时、拾取时难以破裂的元件芯片的制造方法。
本公开所涉及的发明的一方面涉及一种如下所示的元件芯片的制造方法。即,涉及一种元件芯片的制造方法,包括:将半导体基板载置到等离子体处理装置具备的载置台的载置工序;和等离子体切割工序。这里,半导体基板具备第1主面以及第1主面的相反侧的第2主面,并且具备多个元件区域以及划定元件区域的分割区域,形成了在元件区域中覆盖第1主面、并且在分割区域中使第1主面露出的掩模,具有可挠性。载置工序,将该半导体基板在第2主面保持于保持片的状态下载置到等离子体处理装置具备的载置台。
等离子体切割工序,在载置台上将半导体基板的第1主面侧暴露于等离子体,从而在分割区域形成槽并且从第1主面一侧蚀刻到第2主面,从而将半导体基板单片化为具备元件区域的多个元件芯片。
此外,半导体基板的厚度小于所述保持片的厚度。
此外,在等离子体切割工序中,通过在使槽的底部总是露出的状态下进行从第1主面侧到第2主面的蚀刻,从而在元件芯片的侧面不形成扇形凹凸地将半导体基板单片化。
发明效果
根据本公开所涉及的发明的元件芯片的制造方法,在运输保持在保持片上的元件芯片、或者从保持片拾取元件芯片时,元件芯片难以破裂。
附图说明
图1A是表示本公开的实施方式中使用的保持在保持片上的状态的半导体基板的俯视图。
图1B是图1A的IB-IB线的向视剖视图。
图2是示意性表示本公开的实施方式所涉及的元件芯片的制造方法的概略剖视图。
图3是示意性表示本公开的实施方式所涉及的等离子体切割工序中切割进展的状态的概略剖视图。
图4是示意性表示本公开的实施方式所涉及的元件芯片的制造方法所使用的等离子体处理装置的构造的概略剖视图。
图5是示意性表示现有Bosch法的切割过程的概略剖视图。
图6A是示意性表示从保持片拾取在侧面具有扇形凹凸的厚的元件芯片时的元件芯片的状态的概略剖视图。
图6B是示意性表示从保持片拾取在侧面具有扇形凹凸的厚的元件芯片时的元件芯片的状态的概略剖视图。
图6C是示意性表示从保持片拾取在侧面具有扇形凹凸的厚的元件芯片时的元件芯片的状态的概略剖视图。
图7A是示意性表示从保持片拾取在侧面具有扇形凹凸的薄的元件芯片时的元件芯片的状态的概略剖视图。
图7B是示意性表示从保持片拾取在侧面具有扇形凹凸的薄的元件芯片时的元件芯片的状态的概略剖视图。
图7C是示意性表示从保持片拾取在侧面具有扇形凹凸的薄的元件芯片时的元件芯片的状态的概略剖视图。
图7D是示意性表示从保持片拾取在侧面具有扇形凹凸的薄的元件芯片时的元件芯片的状态的概略剖视图。
图8A是示意性表示本公开的实施方式所涉及的从保持片拾取薄的元件芯片时的元件芯片的状态的概略剖视图。
图8B是示意性表示本公开的实施方式所涉及的从保持片拾取薄的元件芯片时的元件芯片的状态的概略剖视图。
图8C是示意性表示本公开的实施方式所涉及的从保持片拾取薄的元件芯片时的元件芯片的状态的概略剖视图。
图8D是示意性表示本公开的实施方式所涉及的从保持片拾取薄的元件芯片时的元件芯片的状态的概略剖视图。
符号说明
10:基板
R1:分割区域
R2:元件区域
M:掩模
20:运输载体
21:框架
22:保持片
22a:粘合剂层
22b:基材层
5:槽
110:元件芯片
(1):载置工序
(2):等离子体蚀刻工序
(3):灰化工序
(4):分离(拾取)工序
200:等离子体处理装置
203:真空腔
203a:气体导入口
203b:排气口
208:电介质构件
209:天线
210A:第1高频电源
210B:第2高频电源
211:载置台
212:工艺气体源
213:灰化气体源
214:减压机构
215:电极层
216:金属层
217:基台
218:外周部
219:ESC电极
220:高频电极部
221:升降杆
222:支承部
223A,223B:升降机构
224:盖
224W:窗部
225:冷媒循环装置
226:直流电源
227:冷媒流路
228:控制装置
229:外周环
301:掩模
302:保持片
302a:粘合剂层
302b:基材层
303:半导体基板
304:槽
305:保护膜
306、306A、306B:元件芯片
S:扇形凹凸
具体实施方式
在说明本公开所涉及的元件芯片的制造方法之前,以下对于具有扇形凹凸的元件芯片的制造方法以及该元件具有的问题进行说明。
在图6A以及图7A中,分别示出具有扇形凹凸S的单片化的元件芯片306(306A、306B)的立体图。元件芯片306在保持在保持片302上的状态下从等离子体处理装置取出,被运输到拾取工序。保持片302具备可挠性,在运输时会挠曲。在元件芯片306较厚的情况下,即使保持片302挠曲,在元件芯片306也难以产生挠曲。若元件芯片306变薄,则保持片302挠曲时,在元件芯片306也容易产生挠曲。
图6B是示意性表示从保持片302拾取在侧面具有扇形凹凸S的比较厚的元件芯片306A时的元件芯片306的状态的概略剖视图。图7B是示意性表示从保持片302拾取在侧面具有扇形凹凸S的比较薄的元件芯片306B时的元件芯片306的状态的概略剖视图。
在拾取元件芯片306A、306B时,首先,通过对具有粘合剂层302a和基材层302b的保持片302的粘合剂层302a照射紫外线,从而使粘合剂层302a固化,使保持片302与元件芯片306A、306B之间的粘接力降低。而且,通过对保持片302施加张力而拉伸,从而扩大相邻的元件芯片彼此的间隔,通过上推夹具307上推保持片302的保持元件芯片306A、306B的区域(图6C、图7C)。用吸附头吸附被上推了的元件芯片306A、306B的上表面,从保持片302的粘合剂层302a剥离元件芯片306A、306B。
在上推元件芯片306A、306B时,具有可挠性的保持片302挠曲。此时,通过在保持片302与元件芯片306A、306B之间残留的粘接力,在元件芯片306A、306B也施加应力。
在比较厚的元件芯片306A的情况下,在隔着保持片302上推元件芯片306时,即使保持片302如图6C所示那样挠曲,因为元件芯片306A具有刚性,所以几乎不挠曲。因此,从其外缘部分向内侧依次从保持片302剥离元件芯片306A。
另一方面,如图7A所示,在比较薄的元件芯片306B的情况下,因为元件芯片306B的刚性不足,所以隔着保持片302上推元件芯片306B时,如图7C所示在元件芯片306B也产生较大的挠曲,如图7D所示,容易产生以侧面的扇形凹凸S为起点的破裂、碎裂Ds。
在Bosch法中,通过控制切割条件,从而能够使扇形凹凸S的尺寸变小,但是难以消除扇形凹凸S。在元件芯片较薄的情况下,在运输、拾取时若元件芯片挠曲,则会以扇形凹凸为起点在元件芯片产生破裂。
以下,叙述本公开的一实施方式所涉及的元件芯片的制造方法。
本公开的一实施方式所涉及的元件芯片的制造方法具备(1)载置工序和(2)等离子体切割工序。
(1)载置工序
载置工序将半导体基板载置到等离子体处理装置具备的载置台。半导体基板具备第1主面以及第1主面的相反侧的第2主面,并且具备多个元件区域以及划定元件区域的分割区域,形成在元件区域中覆盖第1主面、并且在分割区域中使第1主面露出的掩模,其具有可挠性。将该半导体基板在第2主面被保持片进行了保持的状态下载置到等离子体处理装置具备的载置台。
(2)等离子体切割工序
等离子体切割工序,在载置台上将半导体基板的第1主面侧暴露于等离子体,从而在分割区域形成槽的同时从第1主面侧蚀刻到第2主面,由此将半导体基板单片化为具备元件区域的多个元件芯片。
这里,半导体基板的厚度比保持片的厚度小,在等离子体切割工序(2)中,通过在使槽的底部总是露出的状态下进行从第1主面侧到第2主面的蚀刻,从而在元件芯片的侧面不形成扇形凹凸地将半导体基板单片化。在等离子体切割工序(2)中,例如,可以以包含六氟化硫以及氧气的工艺气体为原料来产生等离子体。
在本实施方式中,在等离子体切割工序(2)中,因为在使槽的底部总是露出的状态下进行等离子体蚀刻,所以在元件芯片的侧面不形成扇形凹凸。因此,在半导体基板的厚度比保持片的厚度小,从保持片拾取元件芯片时,即使在元件芯片挠曲的情况下,也能够抑制以元件芯片侧面的凹凸为起点的破裂、碎裂。
另外,在使槽的底部总是露出的状态下进行等离子体蚀刻,意味着不是通过Bosch法进行等离子体蚀刻(等离子体切割)。也就是说,在本实施方式中,在等离子体蚀刻工序(具体而言,从半导体基板的第1主面到第2主面蚀刻分割区域的期间)中,在槽的底部不形成保护膜,使蚀刻进展。
以下,参照图1A~图4来详细说明本发明所涉及的制造方法。
载置在等离子体处理装置具备的载置台的半导体基板,虽然载置在等离子体处理装置具备的载置台,但是图1A是表示保持于保持片的状态的半导体基板的俯视图。此外,图1B是图1A的IB-IB线的向视剖视图。保持片22具备粘合剂层22a和支承粘合剂层22a的基材层22b。保持片22通过粘合剂层22a的与基材层22b相反侧的表面(粘合面)保持半导体基板10,与配置在半导体基板10的周围的环状的框架21固定。将该框架21和固定于框架21的保持片22一起称为运输载体20。框架21具有刚性,保持片22具有可挠性,能够弹性地伸展。
半导体基板10具有保持于保持片22的第2主面和与第2主面相反侧的第1主面。在半导体基板10的第1主面形成掩模,但是在图1中省略了掩模。另外,在图1中,对于框架21以及基板10都呈大致圆形的情况进行了图示,但是本发明不限定于该情况。
图2是示意性表示本发明的实施方式所涉及的元件芯片的制造方法的概略剖视图。图2的制造方法包括:载置工序(1),将形成了掩模的半导体基板载置到载置台;和等离子体切割工序(2),在分割区域中蚀刻半导体基板从而单片化(或者分割)为元件芯片。图2的制造方法在等离子体切割工序(2)之后还包括除去掩模的灰化工序(3)以及从保持片分离元件芯片的分离(拾取)工序(4)。此外,通常,在载置工序(1)之前,进行准备形成了掩模的半导体基板的准备工序、研磨半导体基板的研磨工序、以及将半导体基板保持到保持片的保持工序等。
以下,详细地说明各工序。
(半导体基板的准备工序)
在半导体基板的准备工序中,准备形成了掩模M的半导体基板10。
(半导体基板)
半导体基板10具备多个元件区域R2和划定多个元件区域R2的分割区域R1。在半导体基板10的第1主面形成了掩模M,掩模M在元件区域R2中覆盖第1主面,在分割区域R1中露出第1主面。
半导体基板10是等离子体处理的对象物,被区划为分割区域R1和由分割区域R1划定的多个元件区域R2。在元件区域R2的表面,可以形成半导体电路、电子部件元件、MEMS等的电路层(均未图示)。即,半导体基板10可以具备由半导体构成的本体层(或者半导体层)、和电路层。通过利用后述的等离子体切割工序(2)蚀刻半导体基板10的分割区域R1,从而得到包含元件区域R2的元件芯片110。
作为构成半导体基板(的半导体层)的半导体,例如可以列举硅(Si)、砷化镓(GaAs)、氮化镓(GaN)、碳化硅(SiC)等。电路层至少包含绝缘膜,此外,还可以包含金属材料、树脂保护层、抗蚀剂层、电极焊盘、凸起(bump)等。还可以包含绝缘膜,作为与布线用的金属材料的层叠体(多层布线层)。绝缘膜例如包含二氧化硅(SiO2)、氮化硅(Si3N4)、低介电常数膜(Low-k膜)、聚酰亚胺等的树脂膜、钽酸锂(LiTaO3)、铌酸锂(LiNbO3)等。
半导体基板10的大小没有特别限定,例如,最大直径50mm~300mm左右。半导体基板10的形状也没有特别限定,例如呈圆形、方型。
绝缘膜或者多层布线层的厚度没有特别限定,例如是2~10μm。抗蚀剂层的厚度也没有特别限定,例如是5~20μm。
此外,还可以在半导体基板10设置定向平面(orientation flat)、凹口等缺口(均未图示)。
进而,在半导体层的电路层的相反侧,还可以配置背金属(バツクメタル)层。在得到的元件芯片110是功率器件的情况下等,配置背金属层。背金属层例如包括金(Au)、镍(Ni)、钛(Ti)、铝(Al)、锡(Sn)、银(Ag)、铂(Pt)、钯(Pd)等。这些可以单独使用,也可以组合两种以上进行使用。背金属层,例如可以是单独包含上述金属的单层,也可以是单独包含上述金属的层的层叠体。背金属层的厚度没有特别限定,例如是0.5~1.5μm。
(掩模)
作为覆盖半导体基板10的元件区域R2的掩模M,可以使用抗蚀剂、SiO2膜、氮化硅膜、金属薄膜等。掩模M,根据其构成材料的种类利用公知方法形成在半导体基板10的第1主面。
例如,在抗蚀剂掩模的情况下,可以通过旋涂法等在半导体基板10的表面形成抗蚀剂膜后,通过曝光、显影,从而形成掩模M。此外,也可以代替通常的抗蚀剂,而通过旋涂法涂敷含有填料的感光性聚酰亚胺、感光性聚硅氧烷,通过曝光、显影,从而形成掩模M。在该情况下,能够形成含有SiO2等无机成分的抗蚀剂掩模。
此外,在SiO2掩模的情况下,首先,通过CVD法等气相法,在半导体基板10的表面形成SiO2薄膜。接下来,通过光刻法,在SiO2薄膜上形成在与槽对应的部分具有开口部的抗蚀剂膜。而且,通过蚀刻抗蚀剂膜的开口部的SiO2膜,从而形成在与槽对应的位置具有开口部的SiO2掩模。SiO2膜的蚀刻可以通过干式蚀刻来进行。在SiO2膜的蚀刻后,残留在SiO2掩模上的抗蚀剂膜,通过氧等离子体等的灰化、溶解于丙酮等有机溶剂,从而除去。
(研磨工序)
半导体基板10可以根据需要而通过研磨工序进行薄化。在研磨工序中,通过从形成了掩模M的半导体基板10的第2主面侧进行研磨,从而使半导体基板10的半导体层变薄。该半导体层的研磨,一般是称为背面研磨(BG)加工的处理。
另外,在研磨工序之前,根据需要,可以预先通过保护胶带保护掩模M侧的表面,在研磨工序后剥离保护胶带。
研磨,例如可以通过使用磨粒等对半导体基板10的第2主面进行抛光来进行。对于研磨,没有特别限制地可以采用一般的半导体基板的BG加工的条件。研磨的程度,可以根据元件芯片的用途来适当决定。
此外,在研磨工序之后,根据需要,可以进行对半导体基板10的第2主面进行抛光的抛光工序。
(保持工序)
在保持工序中,使半导体基板10的第2主面侧保持到保持片22。此时,保持片22优选与框架21一体化从而构成运输载体20。根据操作性的观点,保持片22固定于框架21。
(保持片)
保持片22的材质没有特别限定。其中尤其是,根据容易粘接半导体基板10的观点,保持片22优选包含具有柔韧性的树脂膜作为粘合剂层22a和基材层22b。包含树脂膜的保持片22具有可挠性。
保持片22的厚度(t),例如是50~400μm,优选50~300μm或者50~150μm。所谓保持片22的厚度t,是指粘合剂层22a以及基材层22b的合计厚度,可以是基于电子显微镜照片等对任意多个位置(例如,10个位置)所测量的厚度的平均值。
树脂膜的材质没有特别限定,例如可以列举,聚乙烯以及聚丙烯等聚烯烃、聚对苯二甲酸乙酯等聚酯等的热可塑性树脂。在树脂膜中,可以混合用于附加伸缩性的橡胶成分(例如,乙烯-丙烯橡胶(EPM)、乙烯-丙烯-二烯橡胶(EPDM)等)、增塑剂、软化剂、抗氧化剂、导电性材料等的各种添加剂。此外,上述热可塑性树脂也可以具有丙烯酸基等表示光聚合反应的官能基。
粘合剂层22a的外周缘粘接到框架21的一个面上,覆盖框架21的开口。在粘合剂层22a的从框架21的开口露出的部分粘接半导体基板10的第2主面来进行支承。在等离子体处理时,保持片22被载置到载置台,使得等离子体处理装置内所设置的载置台与基材层22b相接。即,从与第2主面相反的第1主面侧进行等离子体蚀刻。
作为构成粘合剂层22a的粘合剂,优选使用通过紫外线(UV)的照射而粘合力减小的粘合成分。据此,在等离子体切割后拾取元件芯片110时,通过进行UV照射,从而元件芯片110容易从粘合剂层22a剥离,变得易于拾取。例如,粘合剂层22a通过在基材层22b的单面涂敷UV固化型丙烯酸粘合剂来得到。
另外,粘合剂层22a的厚度,例如是5~100μm,优选5~15μm。
(框架)
被固定在保持片22的框架21是具有与半导体基板10的整体相同或其以上的面积的开口的框体,具有规定宽度以及基本恒定的薄的厚度。框架21具有在保持了保持片22以及半导体基板10的状态下能够运输的程度的刚性。框架21的开口的形状没有特别限定,例如可以是圆形、矩形、六边形等多边形。在框架21上可以设置用于定位的凹口、切角。作为框架21的材质,例如可以列举铝、不锈钢等金属、树脂等。
(半导体基板的载置工序(1))
在载置工序(1)中,半导体基板10在保持于图1所示那样的运输载体20的保持片22的状态下供给到等离子体处理装置具备的真空腔的处理室(反应室),载置到处理室内的载置台211上(图2(1))。此时,运输载体20载置到载置台211上,使得保持片22的保持了半导体基板10的面(粘合剂层22a的粘合面)朝向上方。
载置到载置台的半导体基板10的厚度,优选比分割区域R1的宽度小。在该情况下,在运输保持在保持片22的元件芯片110,或者拾取保持在保持片的元件芯片110时,相邻的元件芯片110的对置的侧面彼此变得更加难以碰撞。
若分割区域R1的宽度较小,则在拾取时,相邻的元件芯片110的对置的侧面彼此容易碰撞。在本实施方式中,通过使半导体基板10的厚度比保持片22的厚度小,从而即使在分割区域R1的宽度较小的情况下,也能够减少元件芯片110的侧面彼此的碰撞。
半导体基板10(尤其是半导体层)的厚度(T),优选不足100μm,优选50μm以下或者30μm以下。半导体基板10(尤其是半导体层)的厚度T,例如是约20μm。若使用具有这种厚度T的半导体基板10,则即使在半导体基板10的可挠性增加了的情况下,也能够抑制拾取时以元件芯片侧面为起点而发生的破裂、碎裂。
半导体基板10的厚度T,是半导体层的厚度,能够基于电子显微镜照片等来测量。半导体基板10的厚度T,可以是对任意多个位置(例如,10个位置)测量的厚度的平均值。分割区域R1的宽度,能够基于电子显微镜照片等来测量,可以是对任意多个位置(例如,10个位置)测量的宽度的平均值。
(等离子体切割工序(2))
在等离子体切割工序(2)中,通过在使半导体基板10保持于保持片22的状态下将第1主面侧暴露于等离子体,从而对分割区域R1从第1主面侧等离子体蚀刻到第2主面。通过该等离子体蚀刻,半导体基板10被分割为具备元件区域R2的多个元件芯片110(图2(2))。
图3是示意性表示等离子体切割工序(2)中切割进展的状态的概略剖视图。在等离子体切割工序(2)中,首先,将在第1主面形成了掩模M的半导体基板10供给到等离子体切割工序(2)(图3的(2a))。将半导体基板10的分割区域R1暴露于等离子体时,蚀刻分割区域R1,形成槽5(图3的(2b))。在分割区域R1形成槽5,并且使蚀刻从第1主面侧进展到第2主面(图3的(2c))。此时,在使槽5的底部不由保护膜覆盖而总是露出的状态下进行从第1主面侧到第2主面的蚀刻。据此,能够在元件芯片的侧面不形成扇形凹凸而将半导体基板10单片化为元件芯片110。
接下来,参照图4来具体说明等离子体切割工序(2)中所使用的等离子体处理装置200,但是等离子体处理装置不限定于此。图4是示意性表示本实施方式中使用的等离子体处理装置200的构造的概略剖视图。
等离子体处理装置200具备载置台211。运输载体20搭载在载置台211上,使得保持片22的保持了基板10的面(粘合面22a)朝向上方。在载置台211的上方,配置了覆盖框架21以及保持片22的至少一部分并且具有用于使基板10的至少一部分露出的窗部224W的盖224。
载置台211以及盖224配置在反应室(真空腔203)内。真空腔203呈上部开口了的大概圆筒状,上部开口由作为盖体的电介质构件208封闭。作为构成真空腔203的材料,可以例示铝、不锈钢(SUS)、对表面进行了防蚀铝处理的铝等。作为构成电介质构件208的材料,可以例示氧化钇(Y2O3)、氮化铝(AlN)、氧化铝(Al2O3)、石英(SiO2)等电介质材料。在电介质构件208的上方,配置了作为上部电极的天线209。天线209与第1高频电源210A电连接。载置台211配置在真空腔203内的底部侧。
在真空腔203连接了气体导入口203a。在气体导入口203a分别通过配管连接了作为工艺气体的供给源的工艺气体源212以及灰化气体源213。此外,在真空腔203设置了排气口203b,在排气口203b连接了包含用于排放真空腔203内的气体从而减压的真空泵的减压机构214。
载置台211具备分别呈大致圆形的电极层215、金属层216、支承电极层215以及金属层216的基台217和包围电极层215、金属层216以及基台217的外周部218。外周部218由具有导电性以及耐蚀刻性的金属构成,从等离子体保护电极层215、金属层216以及基台217。在外周部218的上表面配置了圆环状的外周环229。外周环229具有从等离子体保护外周部218的上表面的作用。电极层215以及外周环229例如由上述电介质材料构成。
在电极层215的内部配置了构成静电吸附机构的电极部(以下称为ESC电极)219和电连接于第2高频电源210B的高频电极部220。在ESC电极219电连接了直流电源226。静电吸附机构由ESC电极219以及直流电源226构成。另外,等离子体蚀刻,可以对高频电极部220施加高频电力从而施加偏置电压的同时来进行。
金属层216例如由在表面形成了防蚀铝被覆的铝等构成。在金属层216内形成了冷媒流路227。冷媒流路227对载置台211进行冷却。通过冷却载置台211,从而冷却搭载在载置台211上的保持片22,并且还冷却其一部分与载置台211接触的盖224。据此,抑制基板10、保持片22由于在等离子体处理中被加热而被损伤。冷媒流路227内的冷媒通过冷媒循环装置225而循环。
在载置台211的外周附近配置了贯通载置台211的多个支承部222。支承部222由升降机构223A进行升降驱动。若运输载体20被运输到真空腔203内,则交接给上升到规定位置的支承部222。支承部222支承运输载体20的框架21。通过保持片22的上端面下降到与载置台211相同的水平以下,从而运输载体20搭载到载置台211的规定位置。
在盖224的端部联结了多个升降杆221,使盖224能够升降。升降杆221通过升降机构223B进行升降驱动。基于升降机构223B的盖224的升降动作,能够与升降机构223A独立地进行。
控制装置228控制构成包括第1高频电源210A、第2高频电源210B、工艺气体源212、灰化气体源213、减压机构214、冷媒循环装置225、升降机构223A、升降机构223B以及静电吸附机构的等离子体处理装置200的要素的动作。
以分割区域R1被蚀刻的条件,产生等离子体。上述蚀刻条件,能够根据半导体基板10的材质来适当选择。这里,对于半导体基板10由硅构成的情况下的蚀刻条件进行例示。
在掩模M是抗蚀剂掩模的情况下,例如能够以如下条件进行蚀刻,即:作为原料气体以90sccm供给六氟化硫(SF6)、以60sccm供给O2、以850sccm供给He,并且将真空腔203内的压力调整为35Pa,并且将第1高频电源210A对天线209的投入功率设为3600W,将第2高频电源210B对高频电极部220的投入功率设为200W,将载置台温度设为-20℃。根据上述条件,能够以掩模选择比30左右、以5~10μm/分钟的速度在深度方向上几乎垂直地蚀刻半导体基板10。此时通过蚀刻而形成的侧壁,成为没有扇形凹凸的平滑的侧壁。另外,sccm是流量的单位,1sccm是指一分钟流过1cm3的标准状态(0℃、一个大气压)的气体的量。
在掩模M是SiO2掩模的情况下,例如,能够作为原料气体以67sccm供给SF6、以33sccm供给O2、以600sccm供给He、以15sccm供给SiF4,并且将真空腔203内的压力调整为11Pa,并且将第1高频电源210A对天线209的投入功率设为2400W,将第2高频电源210B对高频电极部220的投入功率设为280W,将载置台温度设为-20℃。根据上述条件,能够以掩模选择比70左右、以5~10μm/分钟的速度在深度方向上几乎垂直地蚀刻半导体基板10。此时通过蚀刻而形成的侧壁,成为没有扇形凹凸的平滑的侧壁。
该蚀刻条件因为掩模选择比比较高,为70左右,所以若在半导体基板10的分割区域R1的表面残留氧化膜,则有可能阻碍蚀刻。在该情况下,在上述蚀刻之前,可以进行用于除去有可能残留在半导体基板10的分割区域R1的表面的薄的SiO2层的蚀刻(穿透(breakthrough))。穿透例如能够以如下条件进行,即:作为原料气体以67sccm供给SF6、以33sccm供给O2、以600sccm供给He,并且将真空腔203内的压力调整为11Pa,并且将第1高频电源210A对天线209的投入功率设为2400W,将第2高频电源210B对高频电极部220的投入功率设为280W,将载置台温度设为-20℃。
在抗蚀剂掩模以及SiO2掩模的任一情况下,都例示了使用He作为稀释气体的蚀刻条件,但是也可以使用Ar代替He。但是,使用He作为稀释气体的情况下,蚀刻速度较快、选择比较大、蚀刻形状的垂直性也容易变得良好。
(灰化工序(3))
在掩模M为抗蚀剂掩模的情况下,可以在等离子体切割工序(2)之后进行灰化工序(图2(3))。在灰化工序(3)中,只要能够除去掩模M即可。灰化工序(3)例如可以在进行等离子体切割工序的反应室内进行。在灰化工序(3)中,在反应室内导入灰化用的工艺气体(例如,氧气),并且使反应室内维持规定压力,供给高频电力来在反应室内产生等离子体,从而照射半导体基板10。通过氧等离子体的照射,从半导体基板10的表面除去掩模M。
(分离(拾取)工序(4))
拾取工序(4)在等离子体切割工序(2)之后进行,或者在等离子体切割工序(2)之后进行灰化工序(3)的情况下,在灰化工序(3)之后进行。由等离子体切割工序(2)而单片化了的半导体基板10成为被分离为具备元件区域R2的元件芯片110的状态的状态。元件芯片110被保持在保持片22的粘合剂层22a的粘合面。
图8A~D是示意性表示从保持片22拾取元件芯片110时的元件芯片110的状态的概略剖视图。在拾取图8A所示的元件芯片110的情况下,首先,通过对保持片22照射紫外线,从而使保持片22的粘合剂层22a固化,使保持片22与元件芯片110之间的粘接力降低。而且,通过对保持片22施加张力而拉伸,从而扩大相邻的元件芯片110彼此的间隔,通过上推夹具307上推保持片22的保持元件芯片110的区域。元件芯片110因为较薄所以缺乏刚性。因此,若在保持片22与元件芯片110之间残留粘接力,则如图8C所示在元件芯片110也产生较大的挠曲。但是,因为元件芯片110的侧面是平滑的,所以难以产生以侧面的凹凸为起点的破裂、碎裂。即,因为在元件芯片110的侧面没有形成在Bosch法形成的那样的扇形凹凸,所以在拾取工序(4)中即使元件芯片110挠曲,元件芯片也难以破裂。
若由上推夹具307进一步进行上推,使挠曲变大,则如图8D所示,挠曲了的元件芯片110的恢复力超过保持片22与元件芯片110之间的粘接力,从元件芯片110的外缘部分向内侧依次从保持片22剥离。之后,通过用吸附头吸附元件芯片110的上表面,从而能够从保持片22拾取元件芯片110。
产业可用性
根据本公开的一实施方式,能够抑制运输保持于保持片的元件芯片、或者从保持片拾取元件芯片时的元件芯片的破裂、碎裂。尤其,本发明所涉及的制造方法作为用于从厚度较小的半导体基板通过等离子体切割来制造元件芯片的方法是有用的。
Claims (3)
1.一种元件芯片的制造方法,包括:
载置工序,将具备第1主面以及所述第1主面的相反侧的第2主面并且具备多个元件区域以及划定所述元件区域的分割区域的半导体基板在所述第2主面保持在保持片的状态下载置到等离子体处理装置具备的载置台,所述半导体基板具有可挠性,并且形成了在所述元件区域中覆盖所述第1主面、并且在所述分割区域中使所述第1主面露出的掩模;和
等离子体切割工序,在所述载置台上将所述半导体基板的所述第1主面一侧暴露于等离子体,从而在所述分割区域形成槽并且从所述第1主面一侧蚀刻到所述第2主面,由此将所述半导体基板单片化为具备所述元件区域的多个元件芯片,
所述半导体基板的厚度比所述保持片的厚度小,
在所述等离子体切割工序中,通过在使所述槽的底部总是露出的状态下进行从所述第1主面一侧到所述第2主面的蚀刻,从而在所述元件芯片的侧面不形成扇形凹凸地将所述半导体基板单片化。
2.根据权利要求1所述的元件芯片的制造方法,
所述半导体基板的厚度是50μm以下。
3.根据权利要求1或2所述的元件芯片的制造方法,
在所述等离子体切割工序中,将包含六氟化硫以及氧的工艺气体作为原料来产生所述等离子体。
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CN110098218A (zh) * | 2018-01-31 | 2019-08-06 | 松下知识产权经营株式会社 | 摄像装置 |
CN110729186A (zh) * | 2019-10-24 | 2020-01-24 | 东莞记忆存储科技有限公司 | 一种晶圆切割及分离的加工工艺方法 |
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JP2018110156A (ja) * | 2016-12-28 | 2018-07-12 | キヤノン株式会社 | 半導体装置、その製造方法およびカメラ |
GB201708927D0 (en) * | 2017-06-05 | 2017-07-19 | Spts Technologies Ltd | Methods of plasma etching and plasma dicing |
KR102133279B1 (ko) * | 2018-06-20 | 2020-07-13 | 주식회사 엘지화학 | 회절 격자 도광판용 몰드의 제조방법 및 회절 격자 도광판의 제조방법 |
JP7304557B2 (ja) * | 2019-07-16 | 2023-07-07 | パナソニックIpマネジメント株式会社 | プラズマエッチング方法および素子チップの製造方法 |
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