CN107017305A - Soi电力ldmos装置 - Google Patents

Soi电力ldmos装置 Download PDF

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CN107017305A
CN107017305A CN201710054493.0A CN201710054493A CN107017305A CN 107017305 A CN107017305 A CN 107017305A CN 201710054493 A CN201710054493 A CN 201710054493A CN 107017305 A CN107017305 A CN 107017305A
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layer
doping
drift region
ldmos devices
local buried
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CN107017305B (zh
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扎卡里·K·李
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Texas Instruments Inc
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Abstract

本发明涉及一种LDMOS装置(200)，其包含具有掩埋电介质层(112)及其上掺杂第二掺杂类型的半导体层(115)的处置部分(110)。掺杂第一类型的漂移区域(120)在提供漏极延伸的所述半导体层内。栅极堆叠包含在与所述漂移区域的结的相应侧上的栅极电介质层(122)上的栅极电极(123)。DWELL区域(130)在所述半导体层内。掺杂所述第一类型的源极区域(148)在所述DWELL区域内。掺杂所述第一类型的漏极区域(145)在所述漂移区域内。掺杂所述第二类型的第一局部掩埋层在包含于所述栅极电极下方的所述漂移区域的第一部分中。掺杂所述第一类型的第二局部掩埋层在包含于所述漏极下方的所述漂移区域的第二部分中。

Description

SOI电力LDMOS装置
技术领域
所揭示的实施例涉及绝缘体上半导体(SOI)横向扩散金属氧化物半导体(LDMOS)装置。
背景技术
SOI是与传统的基于块状硅的技术相比生产更高性能、更低电力(动态)装置的半导体技术。SOI通过在例如硅的半导体材料的较薄顶层与通常是硅衬底的支撑处置部分之间放置例如氧化硅或玻璃的较薄电介质(电绝缘)层而运作。
电力集成电路(IC)归因于其小尺寸、低成本、低电力消耗及增加的可靠性等优点而变得重要。以低到中电压范围(例如，30V到120V)操作的电力IC用于例如汽车电子器件、发光二极管驱动器、等离子显示面板、PC***设备及便携式电力管理产品的应用中。通常通过LDMOS装置设计中的降低表面场(RESURF)结构实现低接通电阻。所述RESURF结构经设计以耗尽LDMOS装置在垂直与横向方向两者上的漂移空间，借此降低接近漂移区域处的表面的电场，且因此提升装置的断开状态击穿电压(BVdss)。
SOI对例如LDMOS装置的电力IC是已知的，这是因为SOI在芯片上的各种装置之间提供优越的电隔离以及更好性能。在LDMOS装置中，漏极经横向布置以允许电流横向流动，且漂移区域被***于沟道与漏极之间以将较高漏极提供到源极BV。因此，LDMOS装置通常经设计以实现更高BV同时最小化特定接通电阻以便降低传导电力损耗。
特定接通电阻(RON)被定义为装置的总接通电阻与面积的积。SOI LDMOS的电压击穿电压(VBR)与接通电阻两者都取决于漂移区域的长度及掺杂。通常需要较长的漂移区域长度及低掺杂以在常规LDMOS装置中实现较高的击穿电压，不幸的是，这增加装置的接通电阻。相反地，具有较高掺杂级的较短的漂移区域长度降低接通电阻，但不利地影响击穿电压。因此，在击穿电压与接通电阻之间通常存在权衡。
发明内容
提供此发明内容来以简化形式介绍所揭示概念的简短选择，下文在包含所提供图式的具体实施方式中进一步描述所述概念。此发明内容并不意图限制所主张主题的范围。
在正常的绝缘体上半导体(SOI)横向扩散金属氧化物半导体(LDMOS)装置操作下，偏压被施加于形成于LDMOS装置的掩埋氧化物(BOX)层上方的半导体层中的装置端子，其中处置部分在物理上处于0V(接地)的BOX层下方，所述BOX层在LDMOS装置端子与处置部分之间建立差分装置处置电压(DDH电压)。所揭示的实施例识别高电压SOI LDMOS或具有大约85V及以上的典型操作电压范围的漏极延伸的MOS装置，DDH电压可显著影响LDMOS装置的击穿电压(BV)及驱动电流。此结果是因为相对于LDMOS装置端子上的电压的处置部分电压可影响与漂移区域相关联的耗尽区域。如本文所使用，LDMOS装置与扩散(或漏极延伸的)金属氧化物半导体(DMOS)装置同义，且包含n沟道LDMOS(NLDNMOS)与P沟道PLDMOS装置两者。解决此DDH电压问题的一种已知设计是使用轻掺杂漂移区域(有时与场板组合)。然而，此已知设计经识别为具有高Rsp、低Idsat及准饱和问题等缺点。
本文描述的LDMOS装置结构包含n型局部掩埋层以及p型局部掩埋层两者，其包含具有与栅极电极的部分下方的漂移区域包含的掺杂类型相反的掺杂类型的这些局部掩埋层中的一者。已发现，此局部掩埋层布置最小化DDH电压敏感度，使得LDMOS装置可进行操作而无显著的BV降级，使得可使所述装置提供良好的Rsp、Idsat并在广泛范围的DDH电压条件下最小化准饱和效应。因此，对于所揭示的包含与栅极电极的部分下方的漂移区域的类型相反的类型的局部掩埋层的LDMOS装置，PLDMOS中归因于DDH电压的负DDH条件(例如，低于参考NLDMOS中的接地处置的接地装置电压)及正DDH(高侧情形)中的降低的resurf效应(例如，PLDMOS源极电压高于处置部分电势)可被补偿。
结合任选揭示的(使用各种背端金属级金属1(M1)、金属2(M2)…及栅极电极中的一或多者构造的)交错场板运作，LDMOS装置可因为局部掩埋层与交错场板结构彼此互补而进一步变成DDH电压不变。因此可设计具有相对于DDH电压的各种操作条件需求的使用所揭示的不同局部掩埋层布置以及任选交错FP的LDMOS装置，且可跨越裸片使用相同漂移区域掺杂浓度分布将其集成于相同的IC裸片上。
附图说明
现将参考不一定按比例绘制的附图，其中：
图1是展示根据实例实施例的用于形成具有第一局部掩埋层及第二局部掩埋层的SOI横向LDMOS装置的实例方法的步骤的流程图。
图2是根据实例实施例的具有第一及第二局部掩埋层的实例揭示的SOI NLDMOS装置的横截面描绘。
图3是根据实例实施例的具有第一及第二局部掩埋层的实例SOI LDMOS装置的俯视图，其中栅极电极呈跑道配置。
图4A是展示根据实例实施例的各自被展示为共同裸片上的半装置的实例NLDMOS装置及PLDMOS装置的裸片的横截面描绘，所述半装置针对正DDH电压被设计为具有所揭示的局部掩埋层布置及所揭示的交错FP布置。
图4B是展示根据实例实施例的被展示为半装置的实例PLDMOS装置的裸片的横截面描绘，所述半装置针对负DDH电压被设计为具有所揭示的局部掩埋层布置及所揭示的交错FP布置。
具体实施方式
参考图式描述实例实施例，其中相似的元件符号用于标示类似或等效元件。所说明的动作或事件的排序不应被认为是具限制性，这是因为一些动作或事件可以不同顺序发生及/或与其它动作或事件同时发生。此外，可能不需要所说明的一些动作或事件来实施根据本发明的方法。
此外，如本文所使用的术语“耦合到”或“与……耦合”(及类似物)(无进一步限制)希望描述间接或直接电连接。因此，如果第一装置“耦合”到第二装置，那么那个连接可为通过直接电连接(其中在通路中仅存在寄生现象)，或为经由包含其它装置及连接的中介物通过间接电连接。针对间接耦合，中介物通常不会修改信号的信息但可能会调整其电流电平、电压电平及/或电力电平。
图1是展示根据实例实施例的用于形成具有第一局部掩埋层及第二局部掩埋层的SOI LDMOS装置的实例方法100的步骤的流程图。图2是根据实例实施例的具有被展示为局部PBL 161的第一局部掩埋层及被展示为局部NBL 162的第二局部掩埋层的实例揭示的NLDMOS装置200的横截面描绘。尽管在图2中展示并在本文中大体上描述NLDMOS装置200，但所属领域的一般技术人员应清楚，通过由p掺杂区域替代的n掺杂区域(且反之亦然)来使用此信息形成PLDMOS晶体管，所以，举例来说，NLDMOS装置200的pbody区域将为PLDMOS装置的nbody区域。
步骤101包括提供其上具有毯覆掩埋电介质(BOX)层112及BOX层112上的半导体层115的处置部分110，如图2中所展示。半导体层115掺杂第二掺杂类型(针对NLDMOS装置200是p半导体层115(或pwell区域)，且针对PLDMOS装置是n半导体层115(或nwell区域))。BOX层112具有从0.5μm到4μm变化的典型厚度，例如大约2μm的厚度。处置部分110可包括硅或其它材料，且BOX层112可包括氧化硅。半导体层115可包括硅锗或其它半导体材料。半导体层115可在从1μm到9μm的厚度内变化，通常是4μm到5μm厚。半导体层115中的掺杂级可在5x1013cm-3与5x1015cm-3之间，通常是约1x1015cm-3。
步骤102包括在半导体层115的第一部分中形成掺杂第二掺杂类型的第一局部掩埋层。在图2中，局部PBL 161的p型掺杂与如ndrift区域120所展示的漂移区域中的掺杂类型相反。如图2中所展示，ndrift区域120形成于pbody区域140内，pbody区域140本身形成于半导体层115的部分中。pbody区域140可为无任何掺杂改质的半导体层115的部分，或可通过一或多个离子植入到半导体层115的部分中而形成。
步骤103包括在半导体层115的第二部分中形成掺杂第一掺杂类型的第二局部掩埋层。在图2中，如局部NBL 162所展示的第二局部掩埋层具有与如ndrift区域120所展示的漂移区域中的掺杂类型相同的掺杂类型。典型的局部掩埋层各自占漂移区域的长度的大约二分之一(1/2)，这两者都在从10％到90％的范围内，使得其总数稍微超过100％(较小重叠)。应认识到，如果局部掩埋层(针对NLDMOS是局部PBL 161)越过整个漂移区域120，那么在局部掩埋层与接近漏极的漂移区域之间将存在结BV限制，这将增加漏极结电容。
在一个实施例中，半导体层115是在形成掩埋层(步骤102、103)之后，在BOX层112上的薄半导体层上生长外延层的结果。在此实施例中，起始半导体层厚度通常是从0.5μm到2.5μm，且在外延沉积过程的结束处，半导体层115的厚度是从1μm到9μm厚，通常是4μm到5μm厚。
如本文所使用，“局部掩埋层”具有与半导体层115中的掺杂级相比至少2倍(2x)高的掺杂浓度，通常是10x高，且局部掩埋层具有从1x1015cm-3到1x1018cm-3的掺杂范围，例如，在1x1016cm-3与3x1016cm-3之间。所揭示的局部掩埋层还具有距半导体层115的顶表面最小0.5μm的深度。局部掩埋层距半导体层115的顶表面的典型深度是半导体层115厚度的50％，例如，当半导体层115厚度是4μm时距顶表面2μm。
局部掩埋层161、162两者通常都是通过离子植入形成。在一个实施例中，如图2中的局部PBL 161所展示的第一局部掩埋层是毯覆层，且如图2中的局部NBL 162所展示的第二局部掩埋层是局部化层，其具有足够高的掺杂级以反掺杂第一局部掩埋层中的掺杂级。在另一实施例中，第二局部掩埋层是毯覆层，且第一局部掩埋层是局部化层，其具有足够高的掺杂级以反掺杂第二局部掩埋层中的掺杂级。在又一实施例中，第一局部掩埋层及第二局部掩埋层两者都是经图案化的层。局部掩埋层也可通过在植入掩膜中颤振而被“稀释”，使得局部掩埋层结(例如，局部PBL 161/局部NBL 162)处的浓度渐变以改进BV。
步骤104包括在半导体层115内形成掺杂第一掺杂类型的漂移区域。如上文所提及，漂移区域提供漏极延伸，例如图2中所展示的ndrift区域120为NLDMOS装置200提供漏极延伸区域。离子植入通常用于形成漂移区域。
通常可以任何顺序执行步骤102、步骤103及步骤104中的植入。在全部这些植入之后，所述方法也可包含快速热退火(RTA)损坏退火以修复植入诱发的晶格损坏。另外，在步骤104之后，还可形成浅nwell(SNW)或浅pwell(SPW)。在图2中，SNW被展示为SNWell 155。然而，SNW及SPW也可在STI及DTI步骤之后形成。
接着，在步骤104之后，通常通过蚀刻(例如，DRIE)及接着沟槽填充过程接着形成沟槽隔离(例如，浅沟槽隔离(STI)或深沟槽隔离(DTI))。在图2中展示STI 126。下文描述的图3展示DTI槽240。DTI延伸到BOX层112的顶部。然而，可在漂移区域形成之前或之后执行DTI或STI(步骤104)。在STI的情况中，通常很多漂移区域都在STI下方。
步骤105包括横向于漂移区域120对半导体层115的部分进行植入，包含将包括第二掺杂类型的至少一第一阱植入物(DWELL植入物)植入到半导体层中以形成DWELL区域130。在图2中，展示DWELL区域130形成于pbody区域140中。在针对NLDMOS200的p型区域的情况中，DWELL可包括具有不同剂量及从20KeV到2MeV变化的能量的多个(或一串)硼植入物，且其中剂量从3.0x1012cm-2与3.0x1014cm-2变化，且可使用小于5度的倾斜角，例如2度。
步骤106包括形成栅极堆叠，其包含在邻近与如图2中的ndrift区域120所展示的漂移区域的结的相应侧且在所述相应侧上的半导体层115中的沟道区域上方形成如图2中的栅极电介质层122所展示的栅极电介质层，接着在图2中的栅极电介质层122上形成如栅极电极123所展示的经图案化的栅极电极。栅极堆叠至少部分形成于如图2中的局部PBL161所展示的第一局部掩埋层上方。
栅极电介质层122可为包括氧化硅的5V栅极电介质，其为大约10到15nm厚。也可能使用与大约3nm的二氧化硅一样薄的栅极电介质层122或稍微薄但具有比大约3.9的二氧化硅的电介质常量更高的电介质常量的氮氧化硅(SION)栅极电介质。多晶硅是栅极电极123的一种实例栅极电极材料。然而，也可使用金属栅极或基于CMOS的取代栅极过程提供栅极电极。
如图2中的138所展示的侧壁间隔件通常形成于栅极电极123的侧壁上。任选地，在图2中还展示栅极电极123的顶部上的间隔件材料薄层。图2中所展示的栅极电极123的顶部上的间隔件材料可能存在或可能不存在。在一个实施例中，侧壁间隔件138包括氮化硅。在图2中展示包含于间隔件138上方的预金属(premetal)电介质(PMD)139。
步骤107包括在DWELL区域130内形成如图2中的148所展示的源极区域。步骤108包括在如图2中的ndrift区域120所展示的漂移区域内及如图2中的局部NBL 162所展示的第二局部掩埋层上方形成如图2中的145所展示的漏极区域。通常接着接触件(例如，任选硅化物PMD 139及通孔)及金属化处理，其包含如图2中所展示的到接触DWELL区域130的背部栅极142的接触件、到源极143的接触件、到漏极144的接触件及到栅极147的接触件。
图3是根据实例实施例的具有第一及第二局部掩埋层的实例NLDMOS装置200'的俯视图，其中栅极电极123'呈跑道配置。尽管在此俯视图中不可见，但如图2中的局部PBL 161所展示的第一局部掩埋层在包含于栅极电极123'的至少一部分下方的ndrift区域120的第一部分中。如图2中的局部NBL 162所展示的第二局部掩埋层在包含于漏极145下方的ndrift区域120的第二部分中。展示构架NLDMOS装置200'的沟槽隔离240，其可包括例如DTI的延伸到BOX层112的顶部的电介质沟槽隔离。沟槽隔离240可包括单独DTI或位于STI内的DTI。
被展示为142a的背部栅极/主体接触区域是集成背部栅极接触件，其在Dwell区域130的表面处。背部栅极/主体接触区域142a可通过添加用于CMOS区段的p+SD(PSD)植入物而形成于DWELL区域130内，所述区段经非常重的(p+)硼掺杂。一种布置具有呈常规几何形状的多个背部栅极PSD条带或方块，其中为实现到源极148的低电阻接触，覆盖源极/背部栅极区域的区的NSD植入物未被PSD覆盖。背部栅极/主体接触区域142a允许p型主体区域(Dwell区域130及p主体区域140)以欧姆方式通过硅化物层被短接到掺杂n+的源极148。
所揭示的LDMOS装置通常还包含至少一个FP。所揭示的交错FP的金属FP通常使用也连接到主体的任选连接连接到源极，但替代地，其还可被连接到具有固定电压的任何节点，只要FP上的电压＜漏极上(NLDMOS上)的电压，针对PLDMOS则极性相反。可使用绝对值，即，FP上的电压|＜|漏极上的电压|。当栅极电极被用作FP中的一者时，其被约束为另一固定电势(栅极偏压)。所揭示的交错FP降低栅极与漏极端子之间的电场，随后形成FP诱发的耗尽区域并降低泄漏电流或增加BV以显著改进由LDMOS装置提供的电力输出。
所揭示的交错FP布置跨越如图2中的ndrift区域120所展示的漂移区域的整个长度提供较高的平均电场，以使能够实现更高BV。FP还有助于耗尽漂移区域以使能够使用更高的掺杂浓度，借此降低LDMOS装置的Rdson。
FP的典型数目是2到3，其中范围是1到6(或更多)。相应FP可从栅极电极123及背端金属级(例如，M1、M2、M3…)中选出。如本文所使用的交错FP是指随着其到漂移区域120的垂直距离增加，重叠如图2中的ndrift区域120所展示的漂移区域的较大部分的每一FP，例如下文所描述的图4A及4B中所展示。关于典型揭示的交错FP定位，对于每一级增加(多晶硅栅极或金属)，x的增加是y增加的6倍，其中范围在1.2倍到10倍之间(例如，相对于M1FP的M2FP延伸是M2与M1之间的ILD氧化物厚度的1.2倍到10倍)。对于0.5μm的ILD厚度，在使用6倍增加/突出情况下，M2FP横向延伸超过M1FP 3μm。
图4A是根据实例实施例的包含各自被展示为处置部分110上的BOX层112上的半导体层115上的半装置的NLDMOS装置420及PLDMOS装置430的横截面描绘，其各自都具有所揭示的交错FP。NLDMOS装置420及PLDMOS装置430被展示为通过DTI240'而与彼此隔离，且其各自针对正DDH电压而被设计(相对于处置部分110的正LDMOS装置电压)。在图4A中展示STI126。
NLDMOS装置420具有DWELL区域130中的源极148、漏极145及栅极123。PLDMOS装置430具有DWELL区域130a中的源极148a、漏极145a及栅极123a。NLDMOS装置420具有ndrift区域120及局部PBL 161及局部NBL 162，而PLDMOS装置430具有pdrift区域120a、局部PBL161a及局部NBL 162a。对于到其漏极145的接触，NLDMOS装置420具有到漏极1521的多层接触件，而对于到其漏极145a的接触，PLDMOS装置420具有包含如所展示的接触件、通孔及多层金属互连件的到漏极152a1的多层接触件。
NLDMOS装置420的交错FP被展示为栅极123、1511(M1)及1522(M2)。在本文，栅极123是交错FP***的部分，但如上文所提及，其是被单独偏压的。PLDMOS装置430的交错FP与NLDMOS装置420的交错FP相比不同，且被展示为栅极123a、151a1(M1)及151a2(M2)。同样，栅极电极123a是交错FP***的部分。PMD层及ILD层被统一展示为电介质435。
图4B是展示被展示为针对负DDH(相对于VH＝0的负装置电压)设计的半装置的PLDMOS装置430'的横截面描绘，可见，其具有被展示为现仅占漂移区域120a的面积的大约50％的162a'的局部NBL。FP展示为未改变。在图4B中还展示STI 126。局部PBL被展示为现占漂移区域120a的面积的大约50％的161a'。PLDMOS装置430'可被集成于与PLDMOS装置430相同的裸片上。
结合FP运作，所揭示的LDMOS装置可通过选定局部掩埋层相对于漂移区域的适当重叠被设计为在某一操作电压范围内具有降低的DDH电压敏感度。举例来说，如果NLDMOS420仅以高于处置部分110的偏压的偏压进行操作(负DDH)，那么局部PBL 161可重叠ndrift区域120的近似一半(50％)(其被定义为电介质435下方的漂移区域面积)。尽管展示电介质435未被标定，但在半导体层115内可存在延伸到栅极123a下方的STI。这防止局部PBL 161与漏极145之间的击穿，且还降低RON以及提供降低的准饱和效应(例如，参见展示大约50％重叠的图4A)。另一方面，如果NLDMOS装置以低于处置部分110的偏压的偏压进行操作，那么局部PBL 161可经设计以重叠大量漂移区域(例如，>80％)(其被定义为电介质435下方(例如，STI下)的区域)以便提供所需的resurf效应以在这些负DDH偏压条件下避免击穿。
此相同原理也应用于PLDMOS装置。在图4A中，PLDMOS装置430希望用高于处置部分110的电压的其源极电压进行正DDH操作，这归因于当用高于处置部分电势的其源极进行操作时PLDMOS遇到的降低的resurf效应。另一方面，如果PLDMOS装置需要负DDH电压(源极电压低于处置部分110的电压)，那么图4B中所展示的局部NBL 162'仅重叠电介质435下的漂移区域面积的大约一半(50％)以开发由处置部分提供的resurf效应，因此使RON下降并改进准饱和。因此，如上文所提及，具有各种DDH操作条件需求的LDMOS装置可使用相同漂移区域掺杂浓度分布经设计并被集成于相同的IC裸片上。
所揭示的实施例可用于形成半导体裸片且其可被集成到多种组装流程中以形成多种不同装置及相关产品。半导体裸片中可包含各种元件及/或半导体裸片上可包含各种层，包含障壁层、电介质层、装置结构、有源元件及无源元件，其包含源极区域、漏极区域、位线、基极、发射极、集电极、导电线、导电通孔等等。此外，半导体裸片可由各种过程形成，其包含双极、绝缘栅极双极晶体管(IGBT)、CMOS、BICMOS及MEMS。
本发明涉及的所属领域的技术人员应了解，在所主张的发明的范围内，许多其它实施例及实施例的变化是可能的，且可在不背离本发明的范围的情况下，对所描述的实施例做出另外添加、删除、替代及修改。举例来说，高电压二极管及高电压双极晶体管也从所揭示的实施例获益。

Claims (18)

1.一种横向扩散金属氧化物半导体LDMOS装置，其包括：
处置部分，其上具有毯覆掩埋电介质BOX层及所述BOX层上的半导体层，所述半导体层掺杂第二掺杂类型；
漂移区域，其在所述半导体层内掺杂第一掺杂类型以提供漏极延伸区域；
栅极堆叠，其包含邻近与所述漂移区域的结的相应侧且在所述相应侧上的所述半导体层的沟道部分上方的栅极电介质层及所述栅极电介质层上的经图案化的栅极电极；
DWELL区域，其在所述半导体层内；
源极区域，其在所述DWELL区域内掺杂所述第一掺杂类型；
漏极区域，其在所述漂移区域内掺杂所述第一掺杂类型；
第一局部掩埋层，其在包含于所述栅极电极的至少一部分下方的所述漂移区域的第一部分中掺杂所述第二掺杂类型，及
第二局部掩埋层，其在包含于所述漏极区域下方的所述漂移区域的第二部分中掺杂所述第一掺杂类型。
2.根据权利要求1所述的LDMOS装置，其进一步包括在所述半导体层内掺杂所述第二掺杂类型的主体区域，且所述漂移区域及所述DWELL区域与所述主体区域一起形成。
3.根据权利要求1所述的LDMOS装置，其中所述第一局部掩埋层是毯覆层，且所述第二局部掩埋层是局部化层，其具有足够高的掺杂级以反掺杂所述第一局部掩埋层中的掺杂级。
4.根据权利要求1所述的LDMOS装置，其中所述第二局部掩埋层是毯覆层，且所述第一局部掩埋层是局部化层，其具有足够高的掺杂级以反掺杂所述第二局部掩埋层中的掺杂级。
5.根据权利要求1所述的LDMOS装置，其进一步包括从所述栅极电极及至少一个金属层选出的交错FP布置中的多个场板FP，其中所述交错FP布置包括相对于彼此交错的所述FP，其中随着其到所述漂移区域的垂直距离增加，每一所述FP重叠所述漂移区域的较大部分。
6.根据权利要求1所述的LDMOS装置，其中所述LDMOS装置包括NLDMOS装置。
7.根据权利要求1所述的LDMOS装置，其中所述LDMOS装置包括PLDMOS装置。
8.根据权利要求1所述的LDMOS装置，其中所述衬底包括硅，其中所述栅极电介质层包括氧化硅或氮氧化硅SiON，且其中所述栅极电极包括多晶硅。
9.根据权利要求1所述的LDMOS装置，其中所述LDMOS装置包括第一LDMOS装置及第二LDMOS装置，所述第一LDMOS装置与所述第二LDMOS装置相比具有不同的所述局部掩埋层。
10.一种形成横向扩散金属氧化物半导体LDMOS装置的方法，其包括：
提供处置部分，其上具有毯覆掩埋电介质BOX层及所述BOX层上的半导体层，所述半导体层掺杂第二掺杂类型；
在所述半导体层的第一部分中形成掺杂所述第二掺杂类型的第一局部掩埋层；
在所述半导体层的第二部分中形成掺杂第一掺杂类型的第二局部掩埋层；
在所述半导体层内形成掺杂所述第一掺杂类型的漂移区域；
横向于所述漂移区域对所述半导体层的部分进行植入，包含将包括所述第二掺杂类型的至少一第一阱植入物(DWELL植入物)植入到所述半导体层中以形成DWELL区域；
形成栅极堆叠，其包含在邻近与所述漂移区域的结的相应侧且在所述相应侧上的所述半导体层中的沟道区域上方形成栅极电介质层，接着在所述栅极电介质层上形成经图案化的栅极电极，其中所述栅极堆叠至少部分形成于所述第一局部掩埋层上方；
在所述DWELL区域内形成源极区域，及
在所述漂移区域内及所述第二局部掩埋层上方形成漏极区域。
11.根据权利要求10所述的方法，其进一步包括：在所述半导体层中形成掺杂所述第二掺杂类型的主体区域，其中所述漂移区域及所述DWELL区域两者都与所述主体区域一起形成。
12.根据权利要求11所述的方法，其进一步包括：在所述形成所述第一局部掩埋层及所述形成所述第二局部掩埋层之后，在所述半导体层上生长外延层，其中所述主体区域形成于所述外延层中。
13.根据权利要求10所述的方法，其中所述形成所述第一局部掩埋层包括形成毯覆层，且所述形成所述第二局部掩埋层包括屏蔽植入，其用于形成具有足够高的掺杂级以反掺杂所述第一局部掩埋层中的掺杂级的局部化层。
14.根据权利要求10所述的方法，其中所述形成所述第二局部掩埋层包括形成毯覆层，且形成所述第一局部掩埋层包括屏蔽植入，其用于形成具有足够高的掺杂级以反掺杂所述第二局部掩埋层中的掺杂级的局部化层。
15.根据权利要求10所述的方法，其中所述形成所述第一局部掩埋层包括用于形成局部化层的屏蔽植入，且其中所述形成所述第二局部掩埋层包括用于形成局部化层的屏蔽植入。
16.根据权利要求10所述的方法，其进一步包括：形成从所述栅极电极及至少一个金属层选出的多个场板FP，其中所述FP相对于彼此交错，其中随着其到所述漂移区域的垂直距离增加，每一所述FP重叠所述漂移区域的较大部分。
17.根据权利要求10所述的方法，其中所述衬底包括硅，其中所述栅极电介质层包括氧化硅或氮氧化硅SiON，且其中所述栅极电极包括多晶硅。
18.根据权利要求10所述的方法，其中所述LDMOS装置包括第一LDMOS装置及第二LDMOS装置，所述第一LDMOS装置与所述第二LDMOS装置相比具有不同的所述局部掩埋层。
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