CN107301981B - 集成的扇出型封装件以及制造方法 - Google Patents

集成的扇出型封装件以及制造方法 Download PDF

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CN107301981B
CN107301981B CN201710219639.2A CN201710219639A CN107301981B CN 107301981 B CN107301981 B CN 107301981B CN 201710219639 A CN201710219639 A CN 201710219639A CN 107301981 B CN107301981 B CN 107301981B
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device die
die
top surface
vias
encapsulation material
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CN107301981A (zh
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余振华
余国宠
蔡豪益
郭庭豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US15/130,211 external-priority patent/US9917072B2/en
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Abstract

本发明实施例公开了一种方法，包括从第一器件管芯的第一导电焊盘形成第一通孔，以及从第二器件管芯的第二导电焊盘形成第二通孔。第一导电焊盘和第二导电焊盘分别在第一器件管芯和第二器件管芯的顶面处。第一和第二导电焊盘可用作晶种层。第二器件管芯粘附到第一器件管芯的顶面。该方法还包括将第一器件管芯和第二器件管芯以及第一通孔和第二通孔封装到封装材料中，并且在同一封装工艺在封装第一器件管芯和第二器件管芯以及第一通孔和第二通孔。对封装材料平坦化以显露第一通孔和第二通孔。形成再分布线以电连接第一通孔和第二通孔。本发明实施例涉及集成的扇出型封装件以及制造方法。

Description

集成的扇出型封装件以及制造方法
技术领域
本发明实施例涉及集成的扇出型封装件以及制造方法。
背景技术
堆叠管芯通常用在三维集成电路中。通过管芯的堆叠，减少封装件的占用空间(形状因数)。另外，通过堆叠管芯的形成明显简化布线在管芯中的金属线。
在一些应用中，多个管芯被堆叠以形成管芯堆叠件，其中多个管芯包括穿透衬底的通孔(TSV，有时被称为硅穿孔)。堆叠管芯的总数量有时可达到八个或更多。当形成这样的管芯堆叠件时，第一管芯首先通过倒装接合接合到封装衬底上，其中对焊区或焊球回流以将第一管芯结合到封装衬底。第一底部填充物被分配到位于第一管芯和封装衬底之间的间隙中。然后，固化第一底部填充物。然后，实施测试以确保第一管芯正确地连接到封装衬底以及第一管芯和封装衬底起所期望的作用。
接下来，第二管芯通过倒装接合被接合到第一管芯上，其中对焊区/焊球进行回流以将第二管芯接合到第一管芯。第二底部填充物被分配到位于第二管芯和第一管芯之间的间隙中。然后，固化第二底部填充物。然后，实施测试以确保第二管芯正确地连接到第一管芯和封装衬底以及第一管芯、第二管芯和封装衬底起所期望的作用。接着，第三管芯通过与用作接合第二管芯和第一管芯相同的工艺步骤接合到第二管芯上。重复该工艺直到所有的管芯被接合。
发明内容
根据本发明的一个实施例，提供了一种制造扇出型封装件的方法，包括：从第一器件管芯的第一导电焊盘形成第一通孔，其中，所述第一导电焊盘位于所述第一器件管芯的顶面处；从第二器件管芯的第二导电焊盘形成第二通孔，其中，所述第二导电焊盘位于所述第二器件管芯的顶面处；将所述第二器件管芯粘附到所述第一器件管芯的所述顶面；将所述第一器件管芯和所述第二器件管芯以及所述第一通孔和所述第二通孔封装在封装材料中，其中，在相同的封装工艺中封装所述第一器件管芯和所述第二器件管芯以及所述第一通孔和所述第二通孔；平坦化所述封装材料以显露所述第一通孔和所述第二通孔；以及形成位于所述第一通孔和所述第二通孔上方并且电连接至所述第一通孔和所述第二通孔的再分布线。
根据本发明的另一实施例，还提供了一种制造扇出型封装件的方法，包括：在第一器件管芯的第一导电焊盘上形成第一通孔；在第二器件管芯的第二导电焊盘上形成第二通孔；将所述第一器件管芯和所述第二器件管芯置放在载具上方；在第三器件管芯的第三导电焊盘上形成第三通孔；以及在第四器件管芯的第四导电焊盘上形成第四通孔；将所述第三器件管芯和所述第四器件管芯分别粘附到所述第一器件管芯的顶面和所述第二器件管芯的顶面；将所述第一器件管芯、所述第二器件管芯、所述第三器件管芯和所述第四器件管芯以及所述第一通孔、所述第二通孔、所述第三通孔和所述第四通孔同时封装在封装材料中；平坦化所述封装材料以显露所述第一通孔、所述第二通孔、所述第三通孔和所述第四通孔；以及形成位于所述第一通孔、所述第二通孔、所述第三通孔和所述第四通孔上方并且电连接至所述第一通孔、所述第二通孔、所述第三通孔和所述第四通孔的再分布线。
根据本发明的又一实施例，还提供了一种封装件，包括：第一器件管芯；第一通孔，具有与所述第一器件管芯的第一导电焊盘的顶面接触的第一底面；第二器件管芯，包括与所述第一器件管芯的部分重叠的第一部分；第二通孔，包括：与所述第一器件管芯在同一层级的下部分，其中，所述下部分具有与所述第二器件管芯的第二导电焊盘的顶面接触的第二底面；以及与所述第二器件管芯在同一层级的上部分，其中，所述下部分连续地连接到所述上部分并且在所述上部分和所述下部分之间没有可辨识的界面；封装材料，将所述第一器件管芯、所述第二器件管芯、所述第一通孔和所述第二通孔封装在所述封装材料中；再分布线，位于所述第一通孔和所述第二通孔上方并且电连接至所述第一通孔和所述第二通孔。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1A到图1I示出了根据一些实施例的形成扇出型封装件的中间阶段的横截面图。
图2A到图2I示出了根据一些实施例的形成扇出型封装件的中间阶段的横截面图。
图3A到图3J示出了根据一些实施例的形成扇出型封装件的中间阶段的横截面图。
图4A到图4J示出了根据一些实施例的形成扇出型封装件的中间阶段的横截面图。
图5到图10示出了根据一些实施例的扇出型封装件的横截面图。
图11示出了根据一些实施例的扇出型封装件的顶视图。
图12示出了根据一些实施例的形成扇出型封装件的工艺流程。
图13A到图13C示出了根据一些实施例的用于将各自的器件管芯与上覆的再分布层连接的一些顶部结构。
图14示出了根据一些实施例的表示图13A到图13C中示出的结构的示例性符号。
图15A到图15K示出了根据一些实施例的形成扇出型封装件的中间阶段的横截面图。
图16A和图16B分别示出了根据一些实施例的扇出型封装件的横截面图和顶视图。
图17A和图17B分别示出了根据一些实施例的扇出型封装件的横截面图和顶视图。
图18A到图18C分别示出了根据一些实施例的包括存储立方体的扇出型封装件的横截面图。
图19示出了根据一些实施例的用于使用单一的模制工艺形成扇出型封装件的工艺流程。
具体实施方式
下列公开提供了许多不同的实施例或例子，以实现本发明的不同特征。下面描述了部件和布置的具体例子以简化本发明。当然，这些仅是例子以及并不旨在限制。例如，下面描述中第一部件在第二部件上或上方形成可包括第一部件和第二部件以直接接触方式形成的实施例以及也可包括另外的部件形成在第一部件和第二部件之间使得第一部件和第二部件不直接接触的实施例。另外，本发明在各种例子中可能重复参考数字和/或字母。这种重复是为了简单和清楚的目的，并不是以其本身指定所讨论的各种实施例和/或配置之间的关系。
进一步，为了易于描述，空间关系术语，例如“下方”、“之下”、“下部”、“之上”、“上方”和类似术语可在此使用以描述图中示例出的一个元件或部件相对于另一个元件或部件的关系。除了各图中描述的方向之外空间关系术语旨在包括器件使用或操作时的不同方向。装置可以其他方式定位(旋转90度或者在其他方向)并且在此使用的空间关系描述符可因此同样地被解释。
根据各种示范性实施例提供了集成的扇出型封装件以及形成集成的扇出型封装件的方法。示例说明了形成扇出型封装件的中间阶段。讨论了一些实施例的一些变化。贯穿各种视图和示例性实施例，相似的参考标号被用于指定相似的元件。
图1A到图1I示出了根据一些实施例的形成扇出型封装件的中间阶段的横截面图。在如图12示出的工艺流程中还示意性地示例说明了图1A到图1I示出的步骤。在随后的讨论中，参考图12的工艺步骤讨论图1A到图1I示出的工艺步骤。
参考图1A，提供了器件管芯10(其是具有多个器件管芯的相应的晶圆2的一部分)。根据本发明的一些实施例，器件管芯10是逻辑管芯，其可以是中央处理单元(CPU)管芯、微控制单元(MCU)管芯、输入-输出(IO)管芯、基带(BB)管芯、或者应用处理器(AP)管芯。虽然未示出，器件管芯10可包括半导体衬底，其中诸如晶体管和/或二极管的有源器件形成在半导体衬底的顶面。此外，金属线和通孔(未示出)形成在器件管芯10的位于半导体衬底上方的互连结构中(未示出)，以互连器件管芯10中的集成电路器件。
金属焊盘12被形成在器件管芯10的顶面10A处。器件管芯10的顶面10A还称作前表面。器件管芯10具有背表面10B，其还可以是器件管芯10中的各自半导体衬底的背表面。金属焊盘12可以是铝焊盘、铜焊盘、铝铜焊盘等。金属焊盘12可被形成在器件管芯10的第一表面区中，以及器件管芯10的第二表面区没有形成在其中的金属焊盘。例如，根据如图1A所示的一些示范性实施例，右表面区具有在其中的金属焊盘12，而左表面区没有金属焊盘。
图1B至图1C示出了通孔14的形成。对应的步骤被示例说明为图12中示出的工艺步骤中的步骤202。根据一些实施例，如图1B所示，光刻胶16形成在晶圆2上方，然后被图案化以形成开口15,通过开口15暴露每一个金属焊盘12的一部分。然后在开口15中镀通孔14。然后去除光刻胶16，从而得到图1C中的结构。根据本发明一些实施例，在镀前没有晶种层形成在晶圆2上，因而金属焊盘12充当晶种层。根据可选实施例，在光刻胶16形成之前形成晶种层(未示出)，因而在晶种层上镀通孔14。在光刻胶16的去除之后，晶种层的未直接位于通孔14下方的部分在蚀刻工艺中被去除。因此，晶种层的剩余部分成为通孔14的底部部分。
接着，参考图1D，通过管芯附着膜(DAF)22将器件管芯20粘附到器件管芯10上。对应的步骤被示例说明为在图12示出的工艺步骤中的步骤204。器件管芯20的背表面粘附到器件管芯10的前表面，并因此相应的管芯堆叠是脸对背堆叠。根据本发明的一些实施例，器件管芯20是存储管芯，其可以是闪存(Flash)管芯、静态随机存取存储器(SRAM)管芯、低功率双倍数据速率(DDR)管芯或者类似管芯。虽然未示出，器件管芯20可以是单个的存储管芯或者堆叠的存储管芯。同样，器件管芯20还可包括半导体衬底，其中诸如晶体管和/或二极管的有源器件被形成在半导体衬底的顶面。而且，金属线和通孔(未示出)被形成在器件管芯20的互连结构中以互连器件管芯20中的集成电路器件。器件管芯20的背表面也可以是器件管芯20中的半导体衬底的背表面。
图11示出了器件管芯10和相应的上覆器件管芯20和通孔14的示范性顶视图。在一些示范性实施例中，器件管芯20与器件管芯10的角区重叠，并且通孔14与器件管芯20的两个侧壁邻近。根据可选的实施例，器件管芯20与器件管芯10的中心区重叠，并且通孔14环绕器件管芯20。器件管芯20和通孔14还可使用其他布局方案来进行布局。
DAF 22是粘合剂膜，并且可由聚合物形成。根据本发明一些实施例，DAF 22具有低热传导性，其可以比约0.5W/m*K低。
返回参考图1D，器件管芯20包括导电柱28，其可以是形成在表面介电层26中的金属柱。金属柱28可由铜、镍、钯、金、它们的多层，和/或它们的合金形成。表面介电层26可以由聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等形成。下方的金属柱28可位于可由铜、铝或其他金属形成的金属焊盘24处。
参考图1E，封装材料30被封装在器件管芯20和通孔14上。对应的步骤被示例说明为图12中示出的工艺步骤的步骤206。封装材料30被作为流体分配，然后被压缩和固化(例如在热固化工艺中)。封装材料30填充器件管芯20和通孔14之间的间隙。封装材料30可包括模塑料、模制底部填充物、环氧树脂或者树脂。在封装工艺之后，封装材料30的顶面高于金属柱28和通孔12的顶端。
接着，实施诸如机械研磨、化学机械抛光(CMP)和/或它们的组合的平坦化步骤以平坦化封装材料30、通孔14、表面介电层26和金属柱28。对应的步骤被示例说明为图12示出的工艺步骤中的步骤206。图1E也示出了最后得到的结构。由于平坦化，通孔14的顶面与金属柱28的顶面齐平(共面)，以及与封装材料30的顶面齐平(共面)。
参考图1F，一个或多个介电层32以及各自的再分布层(RDL)34形成在封装材料30、通孔14和金属柱28上方。对应的步骤被示例说明为图12中示出的工艺步骤的步骤208。根据本发明的一些实施例，介电层32由诸如PBO、聚酰亚胺、BCB等的聚合物形成。
RDL形成为与金属柱28和通孔14电连接。注意到，贯穿所有附图RDL34的示例是示意性的。例如，RDL可实际上被图案化为多个被各自的介电层相互隔离开的离散部分。RDL中的离散部分的每一个连接到各自的下方金属柱28和/或通孔14。RDL 34还可以将一些金属柱28与各自的通孔14互连。RDL 34可包括金属迹线(金属线)和位于金属迹下方且与金属迹连接的通孔。根据本发明的一些实施例，RDL 34通过镀工艺形成，其中RDL34中的每个包括晶种层(未示出)和位于晶种层上方的镀的金属化材料。晶种层和镀的金属化材料可由相同的材料或不同的材料形成。
图1G示出了器件管芯10的背侧研磨，从器件管芯10的背侧(示例的底侧)研磨。对应的步骤在图12示出的工艺步骤中的步骤210中被示例说明。因此，如图1G所示，器件管芯10的厚度从厚度T1(图1F)减小到厚度T2。
图1H示出了根据本发明一些示范性实施例的电连接器36的形成。对应的步骤被示例说明为图12示出的工艺步骤中的步骤212。电连接器36电连接到RDL、金属柱28和/或通孔14。电连接器36的形成可包括将焊球置放到RDL 34上方，然后对焊球回流。根据本发明的可选实施例，电连接器36的形成包括实施镀步骤以在RDL 34上方形成焊区，然后对焊球回流。电连接器36还可包括金属柱、或者金属柱和焊帽，其也可通过镀形成。
另外，集成的无源器件(IPD)39可接合到RDL 34。IPD 39可用于调整最后得到的封装件的性能，并且可包括例如电容器。根据一些可选实施例，没有接合IPD 39。贯穿整个描述，包括器件管芯10和20、通孔14、封装材料30、RDL 34和介电层32的结合的结构将被称为复合晶圆38，复合晶圆38可以是包括多个器件管芯10和20的复合晶圆。
在后续的步骤中，复合晶圆38被锯开成多个封装件40，每个封装件包括器件管芯10中的一个、器件管芯20中的一个和相应的通孔14。对应的步骤被示例说明为图12示出的工艺步骤中的步骤214。根据一些实施例，封装件40因而用单独的封装(模制)工艺形成，虽然封装件40包括堆叠在一起的两层器件管芯。这与使用两次封装工艺来封装两层的器件管芯的传统器件堆叠工艺不同。另外，在封装件40中没有使用封装件衬底。这导致有利地减少封装件40的厚度，并因此封装件40适于要求非常薄的封装的移动应用。
根据一些实施例，尽管封装件40是扇出型封装件，但是因为RDL延伸超过器件管芯20的边缘，所以封装件40的占用面积(顶视图区域)与器件管芯10的顶视图区域一样大，假如器件管芯10的顶视图区域适合于设置所有的电连接器36。因此，封装区40的顶视图区域是小的。另外，金属焊盘12和电连接器36之间的距离小，因而导致最后的封装件40在电性能方面的改进。
而且，可以是逻辑管芯的器件管芯10通常比诸如器件管芯20的存储管芯产生更多的热量。存储管芯由于热量遭受严重的性能下降。根据本发明的一些实施例，具有低热传导系数的DAF 22被用于减少器件管芯10产生的热而避免将热引导到器件管芯20。相反，器件管芯10中的热可通过通孔14传导到电连接器36。通孔14中的一些还可设计为不用于器件管芯10和电连接器36之间的电连接的伪通孔。伪通孔14可以是电浮置的，并且用于将管芯器件10中的热传导到电连接器36。
图2A到图4J示出了根据一些实施例的形成扇出型封装件的中间阶段的横截面图。除非另外指定，这些部件的材料和形成方法基本与图1A示出的实施例中类似参考标号指示的类似部件相同。因而，通过图1A到图1H示出的实施例的讨论，可发现或意识到关于图2A到图4J示出的部件(和图5到图10中的实施例)的形成工艺和材料的细节。
图2A和2B示出了一些实施例的初始步骤，这些步骤与图1A至图1C中示出的工艺步骤基本相同。通孔14形成在器件管芯10的金属焊盘12上。接下来，晶圆2被锯成单个的器件管芯10。
参考图2C，器件管芯10通过粘附剂膜被粘附到载具46。根据本发明的一些实施例，载具46是玻璃载具。虽然示出了一个器件管芯10，然而具有置放在载具46上的多个器件管芯10，并且器件管芯10可被布局为阵列。然后，器件管芯20通过DAF 22粘附到管芯10的前表面，如图2D所示。在后续步骤中，如图2E所示，封装材料30被分配以封装器件管芯10和20。与图1E中示出的实施例不同，还封装器件管芯10。与图1E示出的实施例不同，器件管芯10也被封装。因为在单个封装工艺中实现了器件管芯10和20的封装，因此封装材料的上部分(用于封装器件管芯20)和下部分(用于封装器件管芯10)之间没有可辨识的界面。
在后续的步骤中，如图2F所示，介电层32和RDL 34形成在封装材料34上方，并且RDL 34电连接到金属柱28和通孔14。根据一些示范性实施例，RDL 34扩大超出器件管芯10和20的边缘。因此，图2F示出的实施例(与图1F相比)可用于器件管芯10的顶视图区域没有足够大以容纳所有的电连接器36(图2I)的实施例，并因此RDL 34需要从器件管芯10扇出。
接着，载具46从上覆的结构剥离，从而形成了图2G示出的结构。然后实施背侧研磨以去除粘附膜14和薄化器件管芯10，并因而在图2H示出了最后得到的结构。在图2I中，IPD39可以(或可以不)接合到RDL 34。最后得到的复合晶圆38被锯成单个的封装件40，复合晶圆38包括器件管芯10、器件管芯20、封装材料30、通孔14、RDL 34和介电层32。
图3A到3J示出了根据一些实施例的扇出型封装件40的形成。参考图3A，形成晶圆4，晶圆4包括在晶圆4中的器件管芯20。导电焊盘(诸如金属焊盘)24形成在器件管芯20的前表面20A处。器件管芯20具有背表面20B，背表面20B可以是在器件管芯20中的各半导体衬底的背表面。接着，参考图3B，形成通孔14，其中形成工艺可以类似图1B和1C中示出的工艺。然后，晶圆4被锯开成单个的器件管芯20。
参考图3C，器件管芯20(包括20-1和20-2)被拾取和放置到载具46和上覆的粘附膜44上。粘附层44可由光热转换(LTHC)材料形成。另外，DAF 50可用于将器件管芯20粘附到粘附膜44。选择器件管芯20-1和20-2之间的距离，以致器件管芯20-1上方的通孔14和器件管芯20-2上方的通孔14之间的距离足够大以容纳器件管芯10(图3D)。根据本发明的一些实施例，器件管芯20-1和20-2彼此完全相同，并且器件管芯20-1相对于器件管芯20-2旋转180度。根据可选实施例，器件管芯20-1和20-2彼此部分相同，诸如有源器件和互连结构(未示出)的下部分20-1-L(器件管芯20-1的)与器件管芯20-2的下部分20-2-L相同。然而，包括顶部再分布层(未示出)的上部分20-1-U和20-2-U互相不同，以便器件管芯20-1中的导电焊盘24集中在器件管芯20-1的左侧，而器件管芯20-2中的导电电24集中在器件管芯20-2的右侧。根据本发明的可选实施例，器件管芯20-1和20-2是不同类型的管芯，并且具有不同的结构。根据本发明的可选实施例，器件管芯20可包括多于两个管芯，例如四个管芯，并且器件管芯10可包括多于一个的管芯，例如两个管芯，以用于依据设计需要的多个逻辑和多个存储器芯片的集成。根据本发明一些可选实施例，器件管芯20可包括在每一单个器件管芯20-1、20-2(未示出)中的多芯片堆叠的立方体结构。每个堆叠的立方体结构可包括诸如2个芯片到9个芯片的多个芯片。在每个堆叠的立方体结构中，堆叠芯片中的每一个可以是诸如存储器功能芯片的同质功能芯片和/或诸如逻辑功能控制器芯片的异质功能芯片。堆叠的芯片还可以是多个同质存储器芯片(未示出)。根据诸如高带宽存储器(HBM)立方体的设计需要，堆叠的芯片可具有硅穿孔(也称为衬底贯穿通孔，或TVS)。
接着，参考图3D，器件10放置在器件管芯20上方，并且通过DAF 22粘附到器件管芯20的前表面。器件管芯10的一部分还与器件管芯20之间的间隙重叠。根据一些实施例，器件管芯10包括位于金属焊盘12上方的金属柱52，并且没有介电层围绕金属柱52。根据可选实施例，在与金属柱52相同的水平位置具有介电层，并且介电层围绕金属柱52。根据又一些可选实施例，没有金属柱形成在金属焊盘12上方，并且金属焊盘12是器件管芯10的顶部导电部件。
图3E示出了器件管芯10和20以及通孔14在封装材料30中的封装，然后进行机械研磨、化学机械抛光(CMP)和/或它们的组合以暴露金属柱52和通孔14。在后续步骤中，形成介电层32和RDL 34，RDL 34电连接到金属柱52和通孔14，如图3F所示。接着，器件管芯41可以可选地接合到RDL 34(图3G)，以及电连接器36被形成为连接到RDL 34(图3H)。器件管芯41可包括穿透器件管芯41中的半导体衬底的通孔(有时也称为硅穿孔或者衬底贯穿通孔)。根据一些实施例，IPD也可以接合到RDL 34。电连接器36可包括用于焊接到印刷电路板(PCB)的焊球网格阵列。电连接器36还可以是诸如C4焊料凸块、铜柱凸块等的倒装凸块以用于接合封装衬底(未示出)。该配置可应用于贯穿本发明的所有实施例。
然后，从上覆的结构剥离载具46，并且最后的结构如图3I所示。在后续步骤中，从背侧研磨器件管芯20-1和20-2，并且通过研磨去除DAF 50。图3J示出了最后得到的结构。图3J进一步示出了盖54例如通过热界面材料(TIM)56粘附到器件管芯20。TIM 56的热传导系数大于DAF 22的热传导系数(图1I、2I和3J)。例如，TIM 56的热传导系数可高于约1W/m*K或者甚至更高。盖54可由具有好的热传导系数的材料形成。根据一些示范性实施例，盖54包括诸如铝、铜、铝/铜合金、不锈钢等的金属。
图4A到4J示出了根据一些实施例的封装件40(图4J)的形成。这些实施例基本与图3A到图3J示出的实施例相同，除了器件管芯10不具有形成在金属焊盘12上方的金属柱52(图3J)。下面提供形成工艺的简要讨论。这些实施例的细节可在图3A到3J的实施例中发现，并且在此不再重复。
图4A到图4C示出的步骤基本与图3A到图3C示出的步骤相同。接着，如图4D所示，器件管芯10粘附到器件管芯20(包括20-1和20-2)。器件管芯10包括作为顶面导电部件的金属焊盘12，并且没有金属柱形成在金属焊盘12上方。器件10也置放直接在器件管芯20-1上方的通孔14和直接在器件管芯20-2上方的通孔14之间。
图4E示出了封装材料30的直接形成而在没有平坦化的情况下暴露金属焊盘12和通孔14。图4F到图4J示出的工艺步骤基本与图3F到图3J示出的工艺步骤相同，因而在此不再重复细节。
图5到图10示出了根据本发明一些实施例形成的封装件。从图1A到图4J中的实施例可理解形成工艺。图5示出的封装件40与图1I中示出的封装件类似，除了在图5中，没有金属柱形成且金属焊盘24是管芯20的顶部导电部件之外。RDL 34包括与金属焊盘24物理接触的通孔。
图6示出的封装件40与图2I示出的封装件类似，除了在图6中，没有金属柱形成且金属焊盘24是管芯20的顶部导电部件之外。RDL 34包括与金属焊盘24物理接触的通孔。
图7示出了封装件40，其与图2I中的封装件40相类似，除了器件管芯20相对于器件管芯10部分偏移之外。由于部分偏移，器件管芯20的第一部分与封装材料30的部分重叠，并且与器件管芯10的任何部分不重叠。器件管芯20的第二部分与器件管芯的部分重叠。因此，器件管芯20的第一部分被悬垂，没有器件10的下方支撑。器件管芯20相对于器件管芯10的部分偏移有利地减少了器件管芯10和20的重叠区域。因此，器件管芯10的顶面区域的增加百分比能够用于形成金属焊盘12和通孔14，而不是与器件管芯20重叠。然而，根据一些实施例，器件管芯20与器件管芯10的偏移没有导致封装件40的形状因数(顶视图区域)中的不期望增长。例如，当通过要求容纳所有电连接器36的区域决定封装件40的顶视图区域时，只要器件管芯10和20的总占用区域不超过要求容纳所有电连接器36的区域，器件管芯20相对于器件管芯10的部分偏移将不会造成形状因数(顶视图区域)的增长。图8示出了与图7示出的封装件类似的封装件40，除了没有金属柱形成在金属焊盘24上方之外。
图9示出了根据一些实施例的封装件40，其中存在两个器件管芯10和相对于各自的器件管芯10部分偏移的两个器件管芯20。每个器件管芯10具有与各自下方的器件管芯20的部分重叠的第一部分，并且具有相对于各自的下方器件管芯20偏移的第二部分。通孔14直接形成在器件管芯20中的每一的金属焊盘24上。
图10示出了根据一些实施例的封装件40，其中存在四个器件管芯20(包括20-3和20-4)以及一个器件管芯10。四个器件管芯20包括两个较高水平的器件管芯20-4和位于两个较高水平的器件管芯20-4下方的两个较低水平的器件管芯20-3。较高水平的器件管芯20-4中每一个具有与各自下方的较低水平的器件管芯20-3的一部分重叠的第一部分，以及具有相对于各自下方的较低水平的器件管芯20-3偏移的第二部分。四个器件管芯20被以第一封装工艺封装在第一封装材料30A中。
器件管芯10位于较高水平的器件管芯20-4上方，并且被以第二封装工艺封装在第二封装材料30B中。器件管芯10相对于两个较高水平的器件管芯部分偏移。例如，器件管芯10具有与较高水平的器件管芯20-4的部分重叠的第一部分，以及与较高水平的器件管芯20-4之间的间隙重叠的第二部分。
封装材料30A和30B可以彼此相同或者彼此不同。通孔14A直接形成在较低水平的器件管芯20-3的金属焊盘24A上。通孔14B中的一些直接形成在较高水平的器件管芯20-4的金属焊盘24B上。由于对封装材料30A的顶面实施CMP，封装材料30A和30B的界面彼此可以是可辨识的，这造成封装材料30中的一些球形填充物58被研磨成具有平坦的(而非球形)顶面。另一方面，在封装材料30B中且与封装材料30A接触的球形填充物60保持为具有圆形。而且，由于通孔14A和14B的形成工艺的性质，通孔14A和14B中的每一个具有大于各自底部宽度的顶部宽度。通孔14B到各自下方的通孔14A的过渡还将显示非连续性，并且通孔14A的顶部宽度可大于各自上方的通孔14B的底部宽度。
在图9和图10中，较高水平的管芯相对于较低水平的管芯的偏移导致在较低水平的管芯20-3的表面区域方面的有利增长，其中较低水平的管芯20-3的表面区域能够用于形成金属焊盘和通孔。另一方，因为较低水平的管芯20-3占据封装件40的大部分顶视图区域，因而封装件的翘曲不严重。
图13A、13B和13C示出了根据本发明一些实施例中的在器件管芯中的顶部导电部件的结构。参考图13A，示出了器件管芯S1。根据一些实施例，器件管芯S1是逻辑管芯，其具有GPU管芯、CPU管芯、GPU-CPU组合功能管芯、MCU管芯、IO管芯、BB管芯或者AP管芯。虽然没有示出，器件管芯S1可包括半导体衬底，其可以根据一些实施例的硅衬底，其中诸如晶体管和/或二极管的有源元件(未示出)形成在半导体衬底的顶面处。而且，金属线和通孔(未示出)形成在互连结构(未示出)中，其中互连结构位于半导体衬底上方以互连器件管芯S1中的集成电路器件。
金属焊盘104形成在器件管芯S1中。根据本发明的一些实施例，金属焊盘104是铝焊盘，但也可包括在其中的一些铜。金属焊盘104电连接到器件管芯S1中的诸如有源器件的集成电路器件。
钝化层106被形成为具有覆盖金属焊盘104的边缘部分的一些部分。金属焊盘104的中心部分通过钝化层106中的开口暴露。钝化层106可以是单一层或者复合层，并且可由无孔材料形成。根据本发明的一些实施例，钝化层106是包括氧化硅层(未示出)和位于氧化硅层上方的氮化硅层(未示出)的复合层。钝化层106还可由其他无孔介电材料形成，例如未掺杂的硅酸盐玻璃(USG)、氮氧化硅等。
介电层108形成在钝化层106上方。介电层108可以是由诸如聚酰亚胺、PBO、BCB等的聚合物形成的聚合物层。介电层108的形成方法可包括例如旋涂。介电层108可以以液体形式分配，然后固化。介电层108上方可驻留介电层110，介电层110可由选自用于形成介电层108的相同候选材料的材料形成，候选材料可包括聚酰亚胺、PBO、BCB等。根据一些实施例，介电层108和110由不同的材料形成。例如，介电材料108可由聚酰亚胺形成，而介电层110可由PBO形成。
导电桩112形成在金属焊盘104上方并与金属焊盘104连接。导电桩112有时也称为金属柱或金属桩。根据一些实施例，导电桩112由诸如铜、镍、金、它们的合金或者它们的多层的金属材料形成。导电桩112延伸进介电层106、108和110内。根据一些实施例，介电层110包括覆盖金属桩112的部分。在模制器件管芯S1后，介电层110覆盖金属桩112的部分可在研磨工艺中被去除，这将在后续工艺中讨论。
图13B示意性示出了根据一些可选实施例中的在器件管芯S1中的顶部导电部件的结构。在一些实施例中，器件管芯S1的顶部部件包括金属焊盘104和钝化层106，其中金属焊盘104的中心部分被暴露。没有金属桩形成在金属焊盘104上方。相反，后续形成的RDL与金属焊盘104直接连接。
图13C示意性示出了根据可选实施例中的在器件管芯S1中的顶部导电部件的结构。根据这些实施例的器件管芯S1与图13A中示出的器件管芯相类似，除了图13A中的介电层110在图13C中省略了。因此，介电层108，其是器件管芯S1中的顶部介电层，具有比金属桩112的顶面低的顶面。
图14示出了器件管芯S1的象征性视图。贯穿整个描述，当图14中示出的器件管芯S1被示例说明时，所示例的器件管芯D1可实际上具有如图13A、13B或者13C中任一个示出的结构。例如，所示例的在器件管芯S1中的导电部件114可表示图13A或者图13C中的金属柱112，或者图13B中金属焊盘114。而且，在图14中示例的介电层116可表示图13A中的介电层106、108和110，图13B中的介电层106，或者图13C中的介电层106和108。
图15A到图15J示出了根据一些实施例的形成扇出型封装件的中间阶段的横截面图。参考图15A，形成晶圆120。晶圆120包括在其中的多个器件管芯M1。根据本发明的一些实施例，器件管芯M1是包括逻辑电路、存储管芯、模拟管芯、传感器管芯等的逻辑管芯。例如，当器件管芯M1是存储管芯时，器件管芯M1可以是闪存管芯、SRAM存储管芯、低功率DDR管芯等。虽然未示出，器件管芯M1可包括半导体衬底，其中诸如晶体管和/或二极管的有源器件形成在半导体衬底的顶面。而且，金属线和通孔(未示出)形成在器件管芯M1的互连结构中以互连各自的器件管芯M1中的集成电路器件。器件管芯M1的背面还可以是在各自器件管芯M1中的半导体衬底的背面。而且，器件管芯M1的背面粘附到DAF 22。
金属焊盘122形成在器件管芯M1的顶面(前表面)。金属焊盘122可以是铝垫、铜垫、铝铜垫等。在器件管芯M1的每一个中，金属焊盘122可相对于各自的器件管芯M1偏移。例如，金属焊盘122可形成在各自的器件管芯M1的所示例的左侧，而器件管芯M1的右侧没有形成在其中的金属焊盘。
通孔124形成在器件管芯M1的顶面上。对应的步骤被示例说明为在图19示出的工艺流程300中的步骤302。根据本发明的一些实施例，使用如图1B和1C示出的类似方法形成通孔124。而且，通孔123的材料可选自用于形成图1C中的通孔的相同候选材料。因而，细节不在此重复。因为通孔124在单个形成工艺(例如镀)中形成，并且通孔124中每个形成在单个开口(与图1B中的开口15类似)中，通孔124的上部分和对应的下部分之间没有可视的界面。而且，通孔124中的每一个的边缘可大体上是直的，且边缘的倾斜角没有突变。通孔124的侧轮廓可以是竖直的或锥形的，并且通孔124的顶视图横截面形状可以是圆形的和/或非圆形的，例如椭圆形、六角形、八角形等。为了简化起见，所讨论的用于通孔124的部件在整个本发明中可应用于所有其他的通孔。
根据本发明的一些实施例，通孔124直接形成在金属焊盘122上。因此，晶种层可用于或者不用于通孔124的形成，并且通孔124的材料是同质的。根据可选实施例，RDL(未示出)可形成为靠近器件管芯M1的顶面，其中RDL用于对例如各自器件管芯M1的左侧的电连接重新布线。然后在RDL的顶部上形成通孔124。在后续步骤中，器件管芯M1从晶圆120被分隔为离散的器件管芯。
图15B示出了晶圆128的形成，晶圆128包括在晶圆128中的器件管芯M2。根据一些实施例，器件管芯M1和M2是相同类型的器件管芯。例如，器件管芯M1和M2可以都是SRAM管芯。而且，器件管芯M1和M2可以在底部具有相同的结构。例如，包括低k介电层(未示出)、在低k介电层中的金属线和通孔(未示出)、晶体管和存储器件(未示出)的器件管芯M1和M2的结构和布局可以彼此相同。器件管芯M1的顶部布线部分可以与器件管芯M2的顶部布线部分不同，以致器件管芯M2的电连接被布线到与器件管芯M1相对的各自器件管芯M2的右侧。
器件管芯M2的背侧还可粘附到DAF 22。器件管芯M2还具有形成在器件管芯M2中的金属焊盘122。通孔124例如通过镀形成在金属焊盘122上方。对应的步骤被示例说明为在图19示出的工艺流程300中的步骤304。金属焊盘122的材料和形成工艺可参考图15A的讨论找到，并因而在此不再重复。然后，器件管芯M2从晶圆128分隔为离散的器件管芯。
参考图15C，形成晶圆130。晶圆130包括在晶圆130中的多个器件管芯M3。根据本发明的一些实施例，器件管芯M3是包括逻辑电路、存储管芯、模拟管芯、传感器管芯等的逻辑管芯。当器件管芯M3是存储管芯时，器件管芯M3可以是闪存管芯、SRAM存储管芯、低功率DDR管芯等。另外，器件管芯M3可具有与器件管芯M1和/或M2相同或不同的结构。
金属焊盘132形成在器件管芯M3的顶面(前表面)处，并且可以铝焊盘、铜焊盘、铝铜焊盘等。与器件管芯M1类似，金属焊盘132还可相对于各自的器件管芯M3的中心偏移。例如，金属焊盘132可形成在各自的器件管芯M3的所示例的左侧中，而器件管芯M3的右侧没有形成在其中的金属焊盘。
通孔134形成在器件管芯M3的顶面上，并且可使用如图1B和1C示出的类似方法(和类似材料)形成。对应的步骤被示例说明为在图19示出的工艺流程300中的步骤306。根据本发明一些实施例，通孔134直接形成在金属焊盘132上。因此，通孔134的形成过程中可以使用或不使用晶种层。根据可选实施例，RDL(未示出)形成为靠近器件管芯M3的顶面，其中，RDL被用于对例如各自的器件管芯M3的左侧的电连接再布线。然后，在再布线RDL的上方形成通孔134。器件管芯M3从晶圆130被分隔成离散的器件管芯。
图15D示出了晶圆138的形成，晶圆138包括在晶圆138中的器件管芯M4。根据一些实施例，器件管芯M3和M4是相同类型的器件管芯。而且，器件管芯M3和M4之间的关系与器件管芯M1和M2之间的关系相类似。器件管芯M4的背侧还可粘附到DAF 22。器件管芯M4还具有形成在器件管芯M4中的金属焊盘132。通孔134形成在金属焊盘132上。对应的步骤被示例说明为在图19示出的工艺流程300中的步骤308。金属焊盘132和通孔134的材料和形成工艺可参考图15A的讨论找到，并因而在此不再重复。然后，器件管芯M4从晶圆138被分割为离散的器件管芯。
接着，参考图15E，拾取器件管芯M1和M2并置放在粘附膜44上方，该粘附膜44位于载具46(例如，玻璃载具)上方。对应的步骤被示例说明为在图19示出的工艺流程300中的步骤310。器件管芯M1置放在器件管芯M2的左侧，且进一步器件管芯M1中的通孔124位于器件管芯M1的左侧。进一步，器件管芯M2中的通孔124位于器件管芯M2的右侧。器件管芯M1和M2互相分隔开距离D1。
接着，如图15F所示，器件管芯M3和M4被拾取并置放，并且通过DAF22各自粘附到器件管芯M1和M2的前侧。对应的步骤被示例说明为在图19示出的工艺流程300中的步骤312。根据本发明的一些实施例，器件管芯M3与各自下方的器件管芯M1的右边部分重叠，并且可以与器件管芯M1的中心重叠或者不与器件管芯M1的中心重叠。而且，器件管芯M3的通孔134在各自的器件管芯M2的左侧上。器件管芯M4与各自下方的器件管芯M2的左边部分重叠，并且可以与器件管芯M2的中心重叠或者不与器件管芯M2的中心重叠。而且，器件管芯M4的通孔134在各自的器件管芯M4的右侧。
根据本发明的一些实施例，器件管芯M3具有延伸超过器件管芯M1的右边缘的右边部分。器件管芯M3的右边部分悬垂。根据本发明的可选实施例，器件管芯M3的整个与器件管芯M1重叠，并且没有悬垂。器件管芯M3和M4具有距离D2，距离D2可以小于、等于或者大于器件管芯M1和M2之间的距离D1。
接着，参考图15G，拾取器件管芯S1并置放在器件管芯M3和M4上方，并且通过DAF22粘附到两个器件管芯M3和M4的前表面。对应的步骤被示例说明为在图19示出的工艺流程300中的步骤314。器件管芯S1的一部分还与器件管芯M3和M4之间的间隙重叠。根据本发明的一些实施例，如图14所示，器件管芯S1包括导电部件114和表面介电层116，它们表示图13A、13B或者13C示出的部件。根据一些实施例，通孔124和134的顶面高于或者低于器件管芯S1的顶面，或者与器件管芯S1的顶面齐平。
图15H示出了器件管芯M1、M2、M3、M4、S1和通孔124和134在封装材料30的封装，接着进行机械抛光、CMP和/或它们的组合以暴露导电部件114和通孔124和134。对应的步骤示例说明为在图19示出的工艺流程300中的步骤316。因为器件管芯M1、M2、M3、M4、S1和通孔124和134通过单个封装工艺进行封装，因而封装材料30中没有可辨识的界面(例如水平界面)。例如，因为对封装材料30的顶面实施单个平坦化工艺，并因而无需对封装材料30的下部分实施研磨，所以封装材料30中的填充物(该填充物可包括球形颗粒(诸如Al2O3颗粒)将保持为球形。然而，在封装材料30的平坦化工艺中是地面(be ground)的球形颗粒将具有在研磨工艺期间被去除的上部分和保持为具有平坦顶面和圆底面的底部部分。
如图15H所示，器件管芯M3、M4和S1中每一个可包括分别与各自下方的管芯M1/M2，和M3/M4重叠的第一部分，以及与封装材料30重叠的第二部分。第二部分可能没有直接位于第二部分下方的任何器件管芯。由于堆叠，器件管芯M3和M4的通孔的高度小于器件管芯M1和M2的通孔的高度。
在后续的步骤中，形成介电层32和RDL 34，并且RDL 34电连接到导电部件114和通孔124和134，如图15I所示。对应的步骤示被例说明为在图19示出的工艺流程300中的步骤318。接着，器件管芯C1可以通过例如倒装接合、混合接合或者表面安装可选地接合到RDL34(图15J)。器件管芯C1可以是集成的无源器件(IPD)、存储管芯、专用集成电路(ASIC)管芯等。器件管芯C1可包括穿透器件管芯C1中的半导体衬底的通孔(有时称为硅穿孔或者衬底贯穿通孔)。根据一些实施例，IPD还可接合到RDL 34。接着，参考图15K，电连接器36形成为与RDL 34连接。对应的步骤被示例说明为在图19示出的工艺流程300中的步骤320。
然后，载具46从上方的结构剥离，并且最后的结构示出在图15K中。在后续的步骤中，散热盖54例如通过TIM 56粘附于最后的封装件。对应的步骤被示例说明为在图19示出的工艺流程300中的步骤322。散热盖54可由具有好的热传导系数的材料形成。根据一些示范性实施例，散热盖54包括诸如铝、铜、铝/铜合金、不锈钢等的金属。因此形成封装件40。
图16A和16B分别示出了根据一些实施例的多层扇出型封装件40的横截面图和顶视图。这些实施例与图15K在的实施例相似，除了器件管芯M3和M4被布局为与图15K中的不同之外。图16A和16B示出的封装件40的形成工艺与图15A到15K示出的基本相同，并因此在此不再重复。
参考图16B，与器件管芯M1和M2的中心互连的第一直线140在X方向上。与器件管芯M3和M4的中心互连的第二直线142在Y方向上。因此，器件管芯M1和M2的对准方向与器件管芯M3和M4的对准方向垂直。这个布局的有利特征是器件管芯M3和M4的较少部分与器件管芯M1和M2重叠，这提供器件管芯M1和M2的更多表面面积以用于形成通孔124。同样，这种配置可导致对称封装布局以实现较好的翘曲控制和机械可靠性/稳定性。图16A示出了封装件40的横截面视图，其中该横截面视图是沿图16B中含16A-16A的线获得的。
作为比较，在图15A示出的实施例中，在图15K示出的封装件40的顶视图(未示出)中，与器件管芯M1和M2的中心互连的第一直线(未示出)可平行于与器件管芯M1和M2的中心互连的第二直线(未示出)。
图17A和17B分别示出了根据一些实施例的多层扇出型封装件40的横截面视图和顶视图。这些实施例与图16A和16B中的实施例相类似，除了另外的器件管芯S2和/或S3被置放为分别与器件管芯M3和M4重叠。图17A和17B中示出的封装件40的形成工艺基本与图15A到15K中示出的相似，并因而在此不再重复。器件管芯S2和S3中的每一个可以是逻辑管芯、存储管芯、IPD等。而且，器件管芯S2和S3的顶部导电部件可选自图13A、13B和13C中示出的结构中的任何一种。
图18A、18B和18C示出了根据一些实施例的扇出型封装件40。这些实施例与图1I中示出的实施例相类似，除了图1I中的器件管芯20被图18A、18B和18C中的器件立方体替代之外。在图18A中，通孔14被分布在器件立方体144的相对侧。在图18B中，通孔14被分布在器件立方体144的一侧(例如示出的右侧)，而不是相对侧。而且，如图18A和18B所示，整个器件立方体144与器件管芯S1重叠。在图18C中，通孔14被分布在器件立方体144的一侧(例如示出的右侧)而不是相对侧。而且，如图18C所示，器件立方体144延伸超过器件管芯S1的左边缘以重叠封装材料30，因而提供更多空间以用于形成金属焊盘12和通孔14。
在图18A、18B和18C中，器件立方体144中的每一个包括多个器件管芯MC1，其可以是根据一些实施例的器件管芯。器件管芯MC1可具有相同或不同的结构，并且通孔(未示出)穿透在其中的半导体衬底。存储器立方体144的顶部导电部件还可采用图13A、13B和13C示出的任何结构。器件立方体144可包括堆叠的多芯片，例如2个芯片到9个芯片。在每个堆叠结构中，所有堆叠的芯片可以是诸如存储器功能芯片的同质功能芯片和/或诸如逻辑功能控制器芯片的异质功能芯片和多个同质存储器芯片(未示出)。堆叠的芯片可具有取决于设计需要的硅穿孔(TSV)，并可形成例如高带宽存储器(HBM)立方体。
本发明的实施例具有一些有利的特征。通过在低层管芯的金属焊盘上直接形成通孔，而不使用封装衬底，因而所得到的封装件是薄的。通过使用ADF的逻辑管芯和存储管芯的热脱离阻止了存储管芯由于逻辑管芯中产生的热量造成的性能下降。封装件的顶视图区域被最小化。高层管芯和底层管芯可通过同一封装工艺封装，并因此降低封装件的成本和翘曲。
根据本发明的一些实施例，一种方法包括从第一器件管芯的第一导电焊盘形成第一通孔，以及从第二器件管芯的第二导电焊盘形成第二通孔。第一导电焊盘和第二导电焊盘分别在第一器件管芯和第二器件管芯的顶面处。第一和第二导电焊盘被用作晶种层。第二器件管芯粘附到第一器件管芯的顶面。该方法还包括将第一器件管芯和第二器件管芯以及第一和第二通孔封装在封装材料中，并且在同一封装工艺中封装第一和第二器件管芯以及第一和第二通孔。对封装材料平坦化以显露第一和第二通孔。形成再分布线以电连接至第一和第二通孔。
根据本发明的一些实施例，一种方法包括在第一器件管芯的第一导电焊盘上形成第一通孔，在第二器件管芯的第二导电焊盘上形成第二通孔，将第一器件管芯和第二器件管芯置放在载具上方，在第三器件管芯的第三导电焊盘上形成第三通孔，以及在第四器件管芯的第四导电焊盘上形成第四通孔。该方法还包括将第三器件管芯和第四器件管芯分别粘附到第一器件管芯和第二器件管芯的顶面，并且将第一、第二、第三和第四器件管芯以及第一、第二、第三和第四通孔同时封装在封装材料中。平坦化封装材料以显露第一、第二、第三和第四通孔。在第一、第二、第三和第四通孔上方形成再分布线并且该再分布线电连接至第一、第二、第三和第四通孔。
根据本发明的一些实施例，一种方法包括在载具上方置放第一器件管芯和第二器件管芯，其中第一器件管芯包括第一通孔，以及第二器件管芯包括第二通孔。第三器件管芯被置放在第一器件管芯上方。第三器件管芯包括与第一器件管芯和第二器件管芯之间的间隙重叠的第一部分，与第一器件管芯的部分重叠的第二部分，以及高于第三器件管芯的第一部分的第三通孔。在同一封装工艺中，第一、第二和第三器件管芯以及第一、第二和第三通孔被封装在封装材料中。对封装材料平坦化以显露第一通孔、第二通孔和第三通孔。再分布线形成在第一通孔、第二通孔和第三通孔上方并且与第一通孔、第二通孔和第三通孔电连接。
根据本发明的一些实施例，一种封装件包括第一器件管芯、第一通孔、第二器件管芯以及第二通孔，其中第一通孔具有与第一器件管芯的第一导电焊盘的顶面接触的第一底面，第二器件管芯的部分与第一器件管芯的部分重叠。第二通孔包括与第一器件管芯在同一层级的下部分，以及与第二器件管芯在同一层级的上部分。下部分具有与第二器件管芯的第二导电焊盘的顶面接触的第二底面。上部分的顶面与第一通孔的顶面共面，以及下部分连续地连接到上部分，并且没有可辨识的界面在上部分和下部分之间。封装件还包括封装第一器件管芯、第二器件管芯、第一通孔和第二通孔在其中的封装材料，以及再分布线位于第一通孔和第二通孔上方并且电连接至第一通孔和第二通孔。
根据本发明的一个实施例，提供了一种制造扇出型封装件的方法，包括：从第一器件管芯的第一导电焊盘形成第一通孔，其中，所述第一导电焊盘位于所述第一器件管芯的顶面处；从第二器件管芯的第二导电焊盘形成第二通孔，其中，所述第二导电焊盘位于所述第二器件管芯的顶面处；将所述第二器件管芯粘附到所述第一器件管芯的所述顶面；将所述第一器件管芯和所述第二器件管芯以及所述第一通孔和所述第二通孔封装在封装材料中，其中，在相同的封装工艺中封装所述第一器件管芯和所述第二器件管芯以及所述第一通孔和所述第二通孔；平坦化所述封装材料以显露所述第一通孔和所述第二通孔；以及形成位于所述第一通孔和所述第二通孔上方并且电连接至所述第一通孔和所述第二通孔的再分布线。
在上述方法中，形成在所述第一器件管芯上的所有通孔偏移至所述第一器件管芯的一侧。
在上述方法中，还包括将第三器件管芯粘附到所述第二器件管芯的所述顶面，其中，通过所述相同的封装工艺以及在所述封装材料中封装在所述第三器件管芯。
在上述方法中，所述第二器件管芯包括与所述第一器件管芯的部分重叠的第一部分以及与所述封装材料的部分重叠的第二部分。
在上述方法中，所述第三器件管芯包括与所述第二器件管芯的部分重叠的第一部分以及与所述封装材料的额外的部分重叠的第二部分。
在上述方法中，所述第三器件管芯包括在平坦化所述封装材料之后显露的导电部件，以及所述导电部件是金属桩或金属焊盘。
在上述方法中，所述第三器件管芯包括在平坦化所述封装材料之后显露的导电部件，以及所述导电部件的顶面与所述第一通孔的顶面和所述第二通孔的顶面共面。
在上述方法中，所述第一通孔具有从所述第一通孔的顶面连续延伸到底面的笔直边缘。
在上述方法中，还包括将散热盖附接到所述第一器件管芯的底部和所述第二器件管芯的底部。
根据本发明的另一实施例，还提供了一种制造扇出型封装件的方法，包括：在第一器件管芯的第一导电焊盘上形成第一通孔；在第二器件管芯的第二导电焊盘上形成第二通孔；将所述第一器件管芯和所述第二器件管芯置放在载具上方；在第三器件管芯的第三导电焊盘上形成第三通孔；以及在第四器件管芯的第四导电焊盘上形成第四通孔；将所述第三器件管芯和所述第四器件管芯分别粘附到所述第一器件管芯的顶面和所述第二器件管芯的顶面；将所述第一器件管芯、所述第二器件管芯、所述第三器件管芯和所述第四器件管芯以及所述第一通孔、所述第二通孔、所述第三通孔和所述第四通孔同时封装在封装材料中；平坦化所述封装材料以显露所述第一通孔、所述第二通孔、所述第三通孔和所述第四通孔；以及形成位于所述第一通孔、所述第二通孔、所述第三通孔和所述第四通孔上方并且电连接至所述第一通孔、所述第二通孔、所述第三通孔和所述第四通孔的再分布线。
在上述方法中，所述第一器件管芯和所述第二器件管芯彼此分隔开第一间隙，以及所述第三器件管芯和所述第四器件管芯彼此分隔开比所述第一间隙小的第二间隙。
在上述方法中，所述第三器件管芯的部分与位于所述第一器件管芯和所述第二器件管芯之间的间隙重叠。
在上述方法中，还包括：将第五器件管芯粘附到所述第三器件管芯的顶面和所述第四器件管芯的顶面，其中，通过所述封装材料封装所述第五器件管芯。
在上述方法中，所述第五器件管芯与位于所述第三器件管芯和所述第四器件管芯之间的间隙重叠。
在上述方法中，在所述第三器件管芯和所述第四器件管芯的顶视图中，互连所述第三器件管芯的中心和所述第四器件管芯的中心的第一直线垂直于互连所述第一器件管芯的中心和所述第二器件管芯的中心的第二直线。
根据本发明的又一实施例，还提供了一种封装件，包括：第一器件管芯；第一通孔，具有与所述第一器件管芯的第一导电焊盘的顶面接触的第一底面；第二器件管芯，包括与所述第一器件管芯的部分重叠的第一部分；第二通孔，包括：与所述第一器件管芯在同一层级的下部分，其中，所述下部分具有与所述第二器件管芯的第二导电焊盘的顶面接触的第二底面；以及与所述第二器件管芯在同一层级的上部分，其中，所述下部分连续地连接到所述上部分并且在所述上部分和所述下部分之间没有可辨识的界面；封装材料，将所述第一器件管芯、所述第二器件管芯、所述第一通孔和所述第二通孔封装在所述封装材料中；再分布线，位于所述第一通孔和所述第二通孔上方并且电连接至所述第一通孔和所述第二通孔。
在上述封装件中，所述第二器件管芯还包括第二部分，并且所述第二部分的底面与所述封装材料的部分的顶面接触。
在上述封装件中，还包括与所述第二器件管芯的部分重叠的第三器件管芯，其中，所述第三器件管芯的顶面与所述第二通孔的所述上部分的所述顶面共面。
在上述封装件中，所述第二通孔的所述上部分具有与所述第一通孔的顶面共面的顶面，以及其中，所述封装材料从顶层级连续延伸至底层级，并且所述顶层级与所述第一通孔的所述顶面共面，以及所述底层级与所述第一器件管芯的底面共面。
在上述封装件中，还包括接合到所述再分布线的集成的无源器件。
上面概述了几个实施例的特征使得本领域技术人员可较好地理解本发明的方面。本领域技术人员应当理解他们可容易地使用本发明作为基础以设计或修改其他工艺和结构以实行相同目的和/或实现在此介绍的实施例的相同优点。本领域技术人员也应意识到这种等同构造没有脱离本发明的精神和范围内，并且他们在没有脱离本发明的精神和范围情况下可以做各种改变、代替和更改。

Claims (25)

1.一种制造扇出型封装件的方法，包括：
从第一器件管芯的第一导电焊盘形成第一通孔，其中，所述第一导电焊盘位于所述第一器件管芯的顶面处；
从第二器件管芯的第二导电焊盘形成第二通孔，其中，所述第二导电焊盘位于所述第二器件管芯的顶面处；
从第三器件管芯的第三导电焊盘形成第三通孔，其中，所述第三导电焊盘位于所述第三器件管芯的顶面处；
从第四器件管芯的第四导电焊盘形成第四通孔，其中，所述第四导电焊盘位于所述第四器件管芯的顶面处；
将所述第二器件管芯和所述第四器件管芯分别粘附到所述第一器件管芯和所述第三器件管芯的顶面；
将所述第一器件管芯、所述第二器件管芯、所述第三器件管芯和所述第四器件管芯以及所述第一通孔、所述第二通孔、所述第三通孔和所述第四通孔封装在封装材料中，其中，在相同的封装工艺中封装所述第一器件管芯、所述第二器件管芯、所述第三器件管芯和所述第四器件管芯以及所述第一通孔、所述第二通孔、所述第三通孔和所述第四通孔；
平坦化所述封装材料以显露所述第一通孔和所述第二通孔；以及
形成位于所述第一通孔和所述第二通孔上方并且电连接至所述第一通孔和所述第二通孔的再分布线，
其中，在所述第二器件管芯和所述第四器件管芯的顶视图中，互连所述第二器件管芯的中心和所述第四器件管芯的中心的第一直线垂直于互连所述第一器件管芯的中心和所述第三器件管芯的中心的第二直线。
2.根据权利要求1所述的方法，其中，形成在所述第一器件管芯上的所有通孔偏移至所述第一器件管芯的一侧。
3.根据权利要求1所述的方法，还包括将第五器件管芯粘附到所述第二器件管芯的所述顶面，其中，通过所述相同的封装工艺以及在所述封装材料中封装在所述第五器件管芯。
4.根据权利要求3所述的方法，其中，所述第二器件管芯包括与所述第一器件管芯的部分重叠的第一部分以及与所述封装材料的部分重叠的第二部分。
5.根据权利要求4所述的方法，其中，所述第五器件管芯包括与所述第二器件管芯的部分重叠的第一部分以及与所述封装材料的额外的部分重叠的第二部分。
6.根据权利要求3所述的方法，其中，所述第五器件管芯包括在平坦化所述封装材料之后显露的导电部件，以及所述导电部件是金属桩或金属焊盘。
7.根据权利要求3所述的方法，其中，所述第五器件管芯包括在平坦化所述封装材料之后显露的导电部件，以及所述导电部件的顶面与所述第一通孔的顶面和所述第二通孔的顶面共面。
8.根据权利要求1所述的方法，其中，所述第一通孔具有从所述第一通孔的顶面连续延伸到底面的笔直边缘。
9.根据权利要求1所述的方法，还包括将散热盖附接到所述第一器件管芯的底部。
10.一种制造扇出型封装件的方法，包括：
在第一器件管芯的第一导电焊盘上形成第一通孔；
在第二器件管芯的第二导电焊盘上形成第二通孔；
将所述第一器件管芯和所述第二器件管芯置放在载具上方；
在第三器件管芯的第三导电焊盘上形成第三通孔；以及
在第四器件管芯的第四导电焊盘上形成第四通孔；
将所述第三器件管芯和所述第四器件管芯分别粘附到所述第一器件管芯的顶面和所述第二器件管芯的顶面；
将所述第一器件管芯、所述第二器件管芯、所述第三器件管芯和所述第四器件管芯以及所述第一通孔、所述第二通孔、所述第三通孔和所述第四通孔同时封装在封装材料中；
平坦化所述封装材料以显露所述第一通孔、所述第二通孔、所述第三通孔和所述第四通孔；以及
形成位于所述第一通孔、所述第二通孔、所述第三通孔和所述第四通孔上方并且电连接至所述第一通孔、所述第二通孔、所述第三通孔和所述第四通孔的再分布线，
其中，在所述第三器件管芯和所述第四器件管芯的顶视图中，互连所述第三器件管芯的中心和所述第四器件管芯的中心的第一直线垂直于互连所述第一器件管芯的中心和所述第二器件管芯的中心的第二直线。
11.根据权利要求10所述的方法，其中，所述第一器件管芯和所述第二器件管芯彼此分隔开第一间隙，以及所述第三器件管芯和所述第四器件管芯彼此分隔开比所述第一间隙小的第二间隙。
12.根据权利要求10所述的方法，其中，所述第三器件管芯的部分与位于所述第一器件管芯和所述第二器件管芯之间的间隙重叠。
13.根据权利要求10所述的方法，还包括：
将第五器件管芯粘附到所述第三器件管芯的顶面和所述第四器件管芯的顶面，其中，通过所述封装材料封装所述第五器件管芯。
14.根据权利要求13所述的方法，其中，所述第五器件管芯与位于所述第三器件管芯和所述第四器件管芯之间的间隙重叠。
15.根据权利要求10所述的方法，其中，所述第一通孔具有从所述第一通孔的顶面连续延伸到底面的笔直边缘。
16.一种封装件，包括：
第一器件管芯；
第一通孔，具有与所述第一器件管芯的第一导电焊盘的顶面接触的第一底面；
第二器件管芯，包括与所述第一器件管芯的部分重叠的第一部分；
其中，所述第一通孔包括：
与所述第二器件管芯在同一层级的下部分，其中，所述第一通孔的下部分具有与所述第一器件管芯的第一导电焊盘的顶面接触的所述第一底面；以及
高于所述第二器件管芯的上部分，其中，所述第一通孔的下部分连续地连接到所述第一通孔的上部分并且在所述第一通孔的上部分和所述第一通孔的下部分之间没有可辨识的界面；
第三器件管芯，与所述第一器件管芯处于同一层级；
第三通孔，具有与所述第三器件管芯的第三导电焊盘的顶面接触的第三底面；
第四器件管芯，包括与所述第三器件管芯的部分重叠的第一部分；
其中，所述第三通孔包括：
与所述第四器件管芯在同一层级的下部分，其中，所述第三通孔的下部分具有与所述第三器件管芯的第三导电焊盘的顶面接触的所述第三底面；以及
高于所述第四器件管芯的上部分，其中，所述第三通孔的下部分连续地连接到所述第三通孔的上部分并且在所述第三通孔的上部分和所述第三通孔的下部分之间没有可辨识的界面；
封装材料，将所述第一器件管芯、所述第二器件管芯、所述第一通孔和所述第三通孔封装在所述封装材料中；
再分布线，位于所述第一通孔和所述第三通孔上方并且电连接至所述第一通孔和所述第三通孔，
其中，在所述第二器件管芯和所述第四器件管芯的顶视图中，互连所述第二器件管芯的中心和所述第四器件管芯的中心的第一直线垂直于互连所述第一器件管芯的中心和所述第三器件管芯的中心的第二直线。
17.根据权利要求16所述的封装件，其中，所述第二器件管芯还包括第二部分，并且所述第二部分的底面与所述封装材料的部分的顶面接触。
18.根据权利要求16所述的封装件，还包括与所述第二器件管芯的部分重叠的第五器件管芯，其中，所述第五器件管芯的顶面与所述第一通孔的所述上部分的所述顶面共面。
19.根据权利要求16所述的封装件，其中，所述第一通孔的所述上部分具有与所述第二器件管芯的第二通孔的顶面共面的顶面，以及其中，所述封装材料从顶层级连续延伸至底层级，并且所述顶层级与所述第一通孔的所述顶面共面，以及所述底层级与所述第一器件管芯的底面共面。
20.根据权利要求16所述的封装件，还包括接合到所述再分布线的集成的无源器件。
21.一种制造半导体器件的方法，包括：
将第一器件管芯和第二器件管芯置放在载具上方，其中所述第一器件管芯包括第一通孔，并且所述第二器件管芯包括第二通孔；
将第三器件管芯放在所述第一器件管芯上方，其中所述第三器件管芯包括：
与所述第一器件管芯和所述第二器件管芯之间的间隙重叠的第一部分；
与所述第一器件管芯的一部分重叠的第二部分；以及
高于所述第三器件管芯的第一部分的第三通孔；
在相同的封装工艺中，封装所述第一器件管芯、所述第二器件管芯和所述第三器件管芯以及所述第一通孔、所述第二通孔和所述第三通孔于封装材料中；
将第四器件管芯放在所述第一器件管芯和所述第二器件管芯上方；
平坦化所述封装材料以显露所述第一通孔、所述第二通孔和所述第三通孔；以及
形成位于所述第一通孔、所述第二通孔和所述第三通孔上方并且电连接至所述第一通孔、所述第二通孔和所述第三通孔的再分布线，
其中，在所述第三器件管芯和所述第四器件管芯的顶视图中，互连所述第三器件管芯的中心和所述第四器件管芯的中心的第一直线垂直于互连所述第一器件管芯的中心和所述第二器件管芯的中心的第二直线。
22.根据权利要求21所述的方法，还包括形成所述第一通孔包括：
在所述第一器件管芯上方形成光刻胶；
图案化所述光刻胶以形成开口，并且所述第一器件管芯的导电焊盘的一部分暴露于所述开口；
在所述开口中镀导电材料以形成所述第一通孔；以及
移除所述光刻胶。
23.根据权利要求21所述的方法，还包括接合集成的无源器件到所述再分布线。
24.根据权利要求21所述的方法，其中，所述封装材料与所述第一通孔、所述第二通孔和所述第三通孔的边缘接触。
25.根据权利要求21所述的方法，其中，所述封装材料包括模塑料。
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