CN106298969B - The processing method and super barrier diode of super barrier diode - Google Patents
The processing method and super barrier diode of super barrier diode Download PDFInfo
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- CN106298969B CN106298969B CN201510363885.6A CN201510363885A CN106298969B CN 106298969 B CN106298969 B CN 106298969B CN 201510363885 A CN201510363885 A CN 201510363885A CN 106298969 B CN106298969 B CN 106298969B
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- 230000004888 barrier function Effects 0.000 title claims abstract description 79
- 238000003672 processing method Methods 0.000 title claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 88
- 229920005591 polysilicon Polymers 0.000 claims abstract description 88
- 238000005530 etching Methods 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 9
- 238000000407 epitaxy Methods 0.000 claims abstract description 7
- 230000000873 masking effect Effects 0.000 claims abstract description 7
- 238000005516 engineering process Methods 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 25
- 238000005468 ion implantation Methods 0.000 claims description 22
- 238000002513 implantation Methods 0.000 claims description 20
- 230000008569 process Effects 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 2
- 239000000243 solution Substances 0.000 description 16
- 238000002360 preparation method Methods 0.000 description 8
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- 230000003628 erosive effect Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010891 electric arc Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8618—Diodes with bulk potential barrier, e.g. Camel diodes, Planar Doped Barrier diodes, Graded bandgap diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
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Abstract
The present invention provides a kind of processing method of super barrier diode and super barrier diode, the processing method includes: that N-type epitaxy layer, field oxide, polysilicon layer and insulating layer are sequentially formed in N-type substrate；After Patterned masking layer is formed on the insulating layer, isotropic etching is carried out to insulating layer, to form insulating layer mask structure；Using the insulating layer mask structure of formation as exposure mask, anisotropic etching successively is carried out to polysilicon layer and field oxide, to expose the specified region of the epitaxial layer for making body area；The area PXing Ti is formed in the specified region of epitaxial layer；P-type region is formed in the epitaxial layer below the edge of the field layer through over etching, the corresponding polysilicon layer in top in P-type region forms p-type polysilicon structure；In the area PXing Ti for forming p-type polysilicon structure, formed and the N+ type region of P-type region disconnecting and electrode.According to the technical solution of the present invention, the reliability of super barrier diode is improved.
Description
Technical field
The present invention relates to semiconductor chip manufacturing technology fields, in particular to a kind of processing of super barrier diode
Method and a kind of super barrier diode.
Background technique
Currently, in the related art, power diode is the critical component of circuit system, it is widely used in high-frequency inversion
The various advanced weaponry controls such as the products for civilian use such as device, digital product, generator, television set and satellite receiver, guided missile and aircraft
The military scenario of system processed and instrumentation devices.Power diode is expanded towards two important directions: (1) to several ten million or even
Up to ten thousand amperes of development, can be applied to the occasions such as high-temperature electric arc wind-tunnel, resistance welder；(2) reverse recovery time is shorter and shorter, presents
Develop to ultrafast, ultra-soft, super durable direction, makes itself to be applied not only to rectification occasion, there are different works in various switching circuits
With.
Therefore, the processing method for how designing a kind of super barrier diode, so that the conducting of the super barrier diode of preparation
Pressure drop is low and leakage current is small becomes technical problem urgently to be resolved.
Summary of the invention
The present invention is based at least one above-mentioned technical problem, proposes a kind of processing method of super barrier diode
Scheme, so that the super barrier diode conduction voltage drop of preparation is less than the diode of traditional structure, level of drain current will be far below biography
System device, and manufacturing process can be simplified, reduce manufacturing cost.
It realizes above-mentioned purpose, according to the embodiment of the first aspect of the invention, provides a kind of adding for super barrier diode
Work method, comprising: N-type epitaxy layer, field oxide, polysilicon layer and insulating layer are sequentially formed in N-type substrate；In the insulation
After forming Patterned masking layer on layer, isotropic etching is carried out to the insulating layer, to form insulating layer mask structure；With shape
At the insulating layer mask structure be exposure mask, is successively carried out to the polysilicon layer and the field oxide anisotropy quarter
Erosion, to expose the specified region of the epitaxial layer for making body area；P-type body is formed in the specified region of the epitaxial layer
Area；P-type region is formed in the epitaxial layer below the edge of the field oxide through over etching, meanwhile, in the P-
The corresponding polysilicon layer in the top in type region forms p-type polysilicon structure；It is being formed described in the p-type polysilicon structure
In the area PXing Ti, N+ type region and electrode of the formation with the P-type region disconnecting, to complete the system of the super barrier diode
Make.
In the technical scheme, by forming P-type region and p-type polysilicon knot after forming insulating layer mask structure
Structure, and by forming N+ type region and electrode, it avoids use and is directly injected into P-type region caused by mode and N+ type region
The problem for getting too close to and causing leakage current larger, namely effectively control P-type region and N+ type region forming region and from
Sub- concentration improves super barrier so that the super barrier diode of preparation has been provided simultaneously with the characteristic of low conducting voltage and Low dark curient
The reliability of diode.
In the above-mentioned technical solutions, it is preferable that after being formed on the insulating layer Patterned masking layer, to the insulating layer
Isotropic etching is carried out, to form insulating layer mask structure, comprising the following specific steps being formed on the insulating layer figure
After changing the mask layer, the insulating layer handled using wet etching, and/or using isotropic etch gas to institute
It states insulating layer and carries out dry etching processing, to form the insulating layer mask structure.
In the technical scheme, by using wet corrosion technique and/or isotropism dry corrosion process to insulating layer
Perform etching so that insulating layer formed groove structure, and then to below insulating layer polysilicon layer and field oxide perform etching
When, still using photoresist as exposure mask, the epitaxial layer below the groove structure of insulating layer corresponds to super barrier diode to be prepared
P-type region, namely using polysilicon layer and field oxide as the exposure mask in preparation P-type region, may further ensure that P-type region
The reliability in domain.
In the above-mentioned technical solutions, it is preferable that form the area PXing Ti, including following tool in the specified region of the epitaxial layer
Body step: the area PXing Ti is formed in the specified region of the epitaxial layer using the first ion implantation technology.
In the technical scheme, the area PXing Ti is formed in the specified region of epitaxial layer by using the first ion implantation technology,
Form the channel region of super barrier diode.
In the above-mentioned technical solutions, it is preferable that the extension below the edge of the field oxide through over etching
P-type region is formed in layer, meanwhile, the corresponding polysilicon layer in top in the P-type region forms p-type polysilicon knot
Structure, comprising the following specific steps using the second ion implantation technology below the edge of the field oxide through over etching
The P-type region formed in the epitaxial layer, meanwhile, the corresponding polysilicon layer shape in top in the P-type region
At p-type polysilicon structure.
In the technical scheme, p-type polysilicon structure and P-type region are formed by the second ion implanting, forms superpotential
The anode ion region of diode is built, to ensure that the reliability and stability of device, forms P- by exposure mask of field oxide
Type region efficiently controls the junction depth and ion concentration in P-type region, avoid P-type region and N+ type region is got too close to and
Lead to the problem that leakage current is excessive, while ensure that the characteristic of the low conducting voltage of super barrier diode.
In the above-mentioned technical solutions, it is preferable that the Implantation Energy of first ion implantation technology be greater than described second from
The Implantation Energy of sub- injection technology.
In the technical scheme, it is greater than the second ion implantation technology by setting the Implantation Energy of the first ion implantation technology
Implantation Energy, form high reliablity the area PXing Ti and P-type region namely super barrier diode channel region and anode from
Sub-district.
In the above-mentioned technical solutions, it is preferable that the implantation dosage of first ion implantation technology be greater than described second from
The implantation dosage of sub- injection technology.
In the technical scheme, it is greater than the second ion implantation technology by setting the implantation dosage of the first ion implantation technology
Implantation dosage, further ensure that the high reliablity in the area PXing Ti and P-type region to be formed, ensure that Low dark curient, low lead
Logical characteristic, to improve the reliability of super barrier diode.
In the above-mentioned technical solutions, it is preferable that in the area PXing Ti for forming the p-type polysilicon structure, formed with
The N+ type region of the P-type region disconnecting and electrode, comprising the following specific steps after forming the p-type polysilicon structure,
N+ type polysilicon layer is formed in the N-type substrate.
In the technical scheme, by forming N+ type polysilicon layer, to be formed in the area PXing Ti by N+ type polysilicon layer
N+ type region namely the cathode ion area of super barrier diode, have efficiently controlled the junction depth and ion concentration in cathode ion area,
And then Low dark curient, low on state characteristic are further ensured, to improve the reliability of super barrier diode.
In the above-mentioned technical solutions, it is preferable that in the area PXing Ti for forming the p-type polysilicon structure, formed with
The N+ type region of the P-type region disconnecting and electrode, also include the following specific steps: carrying out to the N+ type polysilicon layer each
Anisotropy etching, to remove the N+ type polysilicon layer above the insulating layer mask structure with the area PXing Ti, to be formed simultaneously
With the N+ type polysilicon side wall of the EDGE CONTACT of the polysilicon layer, the field oxide and the area PXing Ti；Described in formation
N+ type polysilicon side wall is made annealing treatment, to form the N with the P-type region disconnecting at the edge in the area PXing Ti
+ type region.
In the technical scheme, by forming N+ type polysilicon side wall, and it is made annealing treatment, so that N+ type polycrystalline
Ion in silicon side wall is spread in the area PXing Ti, to form the cathode ion area in N+ type region namely super barrier diode, and
The junction depth and ion concentration in N+ type region have been efficiently controlled, got too close to so as to avoid N+ type region and P-type region and has been led
The problem for causing leakage current excessively high, effectively improves the reliability of super barrier diode.
In the above-mentioned technical solutions, it is preferable that in the area PXing Ti for forming the p-type polysilicon structure, formed with
The N+ type region of the P-type region disconnecting and electrode, also include the following specific steps: after forming N+ type region, using
Any combination of one of metal sputtering processes, electroplating technology and evaporation process technique or kinds of processes, in the N-type substrate
The metal layer that upper formation is contacted with the insulating layer exposure mask, N+ type region, the area PXing Ti simultaneously, the metal layer is institute
State the electrode of super barrier diode.
In the technical scheme, by forming the electrode of super barrier diode, Low dark curient, the low electric conduction of preparation be ensure that
The super barrier diode of pressure can integrate in application-level circuitry, namely by bonding technology, electrode and application layer can be realized
Concatenation between circuit, process are simple.
According to the second aspect of the invention, it is also proposed that a kind of super barrier diode, using such as any of the above-described technical side
The processing method of super barrier diode described in case is fabricated.
By above technical scheme, so that the conduction voltage drop of manufactured super barrier diode is less than the super barrier of traditional structure
Diode, level of drain current will be far below traditional super barrier diode, and it is simple to simplify manufacturing process, reduces superpotential
Build the manufacturing cost of diode.
Detailed description of the invention
Fig. 1 shows the schematic flow diagram of the processing method of the super barrier diode of embodiment according to the present invention；
Fig. 2 to Figure 10 shows the section signal of the process of the super barrier diode of embodiment according to the present invention
Figure.
Specific embodiment
To better understand the objects, features and advantages of the present invention, with reference to the accompanying drawing and specific real
Applying mode, the present invention is further described in detail.It should be noted that in the absence of conflict, the implementation of the application
Feature in example and embodiment can be combined with each other.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, still, the present invention may be used also
To be implemented using other than the one described here other modes, therefore, protection scope of the present invention is not by described below
Specific embodiment limitation.
Fig. 1 shows the schematic flow diagram of the processing method of the super barrier diode of embodiment according to the present invention.
As shown in Figure 1, the processing method of the super barrier diode of embodiment according to the present invention, comprising: step S1, in N
N-type epitaxy layer, field oxide, polysilicon layer and insulating layer are sequentially formed on type substrate；Step S2, is formed on the insulating layer
After Patterned masking layer, isotropic etching is carried out to the insulating layer, to form insulating layer mask structure；Step S3, with shape
At the insulating layer mask structure be exposure mask, is successively carried out to the polysilicon layer and the field oxide anisotropy quarter
Erosion, to expose the specified region of the epitaxial layer for making body area；Step S4, in the specified region shape of the epitaxial layer
At the area PXing Ti；Step S5 forms P-type region in the epitaxial layer below the edge of the field oxide through over etching
Domain, meanwhile, the corresponding polysilicon layer in top in the P-type region forms p-type polysilicon structure；Step S6 is being formed
In the area PXing Ti of the p-type polysilicon structure, N+ type region and electrode of the formation with the P-type region disconnecting, with complete
At the production of the super barrier diode.
In the technical scheme, by forming P-type region and p-type polysilicon knot after forming insulating layer mask structure
Structure, and by forming N+ type region and electrode, it avoids use and is directly injected into P-type region caused by mode and N+ type region
The problem for getting too close to and causing leakage current larger, namely effectively control P-type region and N+ type region forming region and from
Sub- concentration improves super barrier so that the super barrier diode of preparation has been provided simultaneously with the characteristic of low conducting voltage and Low dark curient
The reliability of diode.
In the above-mentioned technical solutions, it is preferable that after being formed on the insulating layer Patterned masking layer, to the insulating layer
Isotropic etching is carried out, to form insulating layer mask structure, comprising the following specific steps step S21, on the insulating layer
After forming the graphical mask layer, the insulating layer handled using wet etching, and/or use isotropic etch
Gas carries out dry etching processing to the insulating layer, to form the insulating layer mask structure.
In the technical scheme, by using wet corrosion technique and/or isotropism dry corrosion process to insulating layer
Perform etching so that insulating layer formed groove structure, and then to below insulating layer polysilicon layer and field oxide perform etching
When, still using photoresist as exposure mask, the epitaxial layer below the groove structure of insulating layer corresponds to super barrier diode to be prepared
P-type region, namely using polysilicon layer and field oxide as the exposure mask in preparation P-type region, may further ensure that P-type region
The reliability in domain.
In the above-mentioned technical solutions, it is preferable that form the area PXing Ti, including following tool in the specified region of the epitaxial layer
Body step: step S41 forms the area PXing Ti in the specified region of the epitaxial layer using the first ion implantation technology.
In the technical scheme, the area PXing Ti is formed in the specified region of epitaxial layer by using the first ion implantation technology,
Form the channel region of super barrier diode.
In the above-mentioned technical solutions, it is preferable that the extension below the edge of the field oxide through over etching
P-type region is formed in layer, meanwhile, the corresponding polysilicon layer in top in the P-type region forms p-type polysilicon knot
Structure, comprising the following specific steps step S51, using the second ion implantation technology on the side of the field oxide through over etching
The P-type region formed in the epitaxial layer below edge, meanwhile, the top in the P-type region is corresponding described more
Crystal silicon layer forms p-type polysilicon structure.
In the technical scheme, p-type polysilicon structure and P-type region are formed by the second ion implanting, forms superpotential
The anode ion region of diode is built, to ensure that the reliability and stability of device, forms P- by exposure mask of field oxide
Type region efficiently controls the junction depth and ion concentration in P-type region, avoid P-type region and N+ type region is got too close to and
Lead to the problem that leakage current is excessive, while ensure that the characteristic of the low conducting voltage of super barrier diode.
In the above-mentioned technical solutions, it is preferable that the Implantation Energy of first ion implantation technology be greater than described second from
The Implantation Energy of sub- injection technology.
In the technical scheme, it is greater than the second ion implantation technology by setting the Implantation Energy of the first ion implantation technology
Implantation Energy, form high reliablity the area PXing Ti and P-type region namely super barrier diode channel region and anode from
Sub-district.
In the above-mentioned technical solutions, it is preferable that the implantation dosage of first ion implantation technology be greater than described second from
The implantation dosage of sub- injection technology.
In the technical scheme, it is greater than the second ion implantation technology by setting the implantation dosage of the first ion implantation technology
Implantation dosage, further ensure that the high reliablity in the area PXing Ti and P-type region to be formed, ensure that Low dark curient, low lead
Logical characteristic, to improve the reliability of super barrier diode.
In the above-mentioned technical solutions, it is preferable that in the area PXing Ti for forming the p-type polysilicon structure, formed with
The N+ type region of the P-type region disconnecting and electrode, comprising the following specific steps after forming the p-type polysilicon structure,
N+ type polysilicon layer is formed in the N-type substrate.
In the technical scheme, by forming N+ type polysilicon layer, to be formed in the area PXing Ti by N+ type polysilicon layer
N+ type region namely the cathode ion area of super barrier diode, have efficiently controlled the junction depth and ion concentration in cathode ion area,
And then Low dark curient, low on state characteristic are further ensured, to improve the reliability of super barrier diode.
In the above-mentioned technical solutions, it is preferable that in the area PXing Ti for forming the p-type polysilicon structure, formed with
The N+ type region of the P-type region disconnecting and electrode, also include the following specific steps: step S61, to the N+ type polysilicon
Layer carries out anisotropic etching, to remove the N+ type polysilicon layer above the insulating layer mask structure with the area PXing Ti, with
Form the N+ type polysilicon side wall simultaneously with the EDGE CONTACT of the polysilicon layer, the field oxide and the area PXing Ti；Step
Rapid S62 makes annealing treatment to the N+ type polysilicon side wall is formed, to be formed and the P- at the edge in the area PXing Ti
The N+ type region of type region disconnecting.
In the technical scheme, by forming N+ type polysilicon side wall, and it is made annealing treatment, so that N+ type polycrystalline
Ion in silicon side wall is spread in the area PXing Ti, to form the cathode ion area in N+ type region namely super barrier diode, and
The junction depth and ion concentration in N+ type region have been efficiently controlled, got too close to so as to avoid N+ type region and P-type region and has been led
The problem for causing leakage current excessively high, effectively improves the reliability of super barrier diode.
In the above-mentioned technical solutions, it is preferable that in the area PXing Ti for forming the p-type polysilicon structure, formed with
The N+ type region of the P-type region disconnecting and electrode, also include the following specific steps: step S63, are forming N+ type area
Behind domain, using one of metal sputtering processes, electroplating technology and evaporation process technique or any combination of kinds of processes, in institute
State the metal layer for being formed in N-type substrate while being contacted with the insulating layer exposure mask, N+ type region, the area PXing Ti, the metal
Layer is the electrode of the super barrier diode.
In the technical scheme, by forming the electrode of super barrier diode, Low dark curient, the low electric conduction of preparation be ensure that
The super barrier diode of pressure can integrate in application-level circuitry, namely by bonding technology, electrode and application layer can be realized
Concatenation between circuit, process are simple.
It is carried out below with reference to process of the Fig. 2 to Figure 10 to the super barrier diode of embodiment according to the present invention specific
Explanation, wherein appended drawing reference and structure of the Fig. 2 into Figure 10 are entitled: 101N type substrate, 102N type epitaxial layer, 103 field oxidations
Layer, 104 polysilicon layers, 105 insulating layers, the area 106P Xing Ti, P-type region 107,108P type polysilicon, 109N+ type polysilicon layer,
110N+ type polysilicon side wall, 111N+ type region, 112 electrodes.
As shown in Fig. 2, successively forming field oxygen in N-type epitaxy layer after forming N-type epitaxy layer 102 in N-type substrate 101
Change layer 103, polysilicon layer 104 and insulating layer 105.
As shown in figure 3, after forming graphical photoresist (structure shown in PR in figure) on insulating layer 105, to insulating layer
105 carry out isotropic etching, wherein and the liquid or gas respectively used into etching technics does not corrode polysilicon substantially,
The etching process of insulating layer is controlled, according to preset etch period or triggering etching point to guarantee the isotropism of insulating layer
The accuracy of etching.
As shown in figure 4, continuing to carry out isotropic etching to polysilicon layer 104 and field oxide 103, this step quarter is completed
After erosion, the edge of insulating layer 105 forms groove structure, and above-mentioned groove structure is used to retain the fringe region of polysilicon layer 104.
As shown in figure 5, with graphical photoresist (structure shown in PR in figure) be exposure mask, to N-type epitaxy layer 102 carry out from
Son injection, to form the area PXing Ti 106, so as to form the channel region of super barrier diode.
As shown in fig. 6, carrying out ion to polysilicon layer 104 after removing graphical photoresist (structure shown in PR in figure)
Injection processing, forms p-type polysilicon 108, meanwhile, it is corresponded in the area PXing Ti 106 in the lower section of p-type polysilicon 108 and forms P-
Type region 107, namely form the anode ion area of super barrier diode.
As shown in fig. 7, forming the N+ type polysilicon layer 109 of flood.
As shown in figure 8, N+ type polysilicon layer 109 carries out anisotropic etch processes, to form N+ type polysilicon side wall
110。
As shown in figure 9, being made annealing treatment to the active area for forming N+ type polysilicon side wall 110, so that N+ type polysilicon
Ion in side wall 110 diffuses into the specified region in the area PXing Ti 106 directly contacted, to form N+ type region 111, namely
Form the cathode ion area of super barrier diode.
As shown in Figure 10, the electrode 112 of super barrier diode is formed, to complete the processing of super barrier diode, Ye Ji
While guaranteeing the low on state characteristic of super barrier diode, realizes and N+ type region 111 and the accurate of P-type region 108 are added
Work, to reduce leakage current, ensure that super barrier diode to realize the separation in cathode ion area and anode ion area
Reliability.
The technical scheme of the present invention has been explained in detail above with reference to the attached drawings, and the invention proposes a kind of super barrier diodes
Processing method and a kind of super barrier diode, so that the conduction voltage drop of manufactured super barrier diode is less than the superpotential of traditional structure
Diode is built, level of drain current will be far below traditional super barrier diode, and can simplify manufacturing process, reduces super barrier two
The manufacturing cost of pole pipe.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of processing method of super barrier diode characterized by comprising
N-type epitaxy layer, field oxide, polysilicon layer and insulating layer are sequentially formed in N-type substrate；
After being formed on the insulating layer Patterned masking layer, isotropic etching is carried out to the insulating layer, to form insulation
Layer mask structure；
Using the insulating layer mask structure of formation as exposure mask, successively to the polysilicon layer and the field oxide carry out it is each to
Anisotropic etch, to expose the specified region of the epitaxial layer for making body area；
The area PXing Ti is formed in the specified region of the epitaxial layer；
P-type region is formed in the epitaxial layer below the edge of the field oxide through over etching, meanwhile, described
The corresponding polysilicon layer in the top in P-type region forms p-type polysilicon structure；
In the area PXing Ti for forming the p-type polysilicon structure, formed with the N+ type region of the P-type region disconnecting and
Electrode, to complete the production of the super barrier diode.
2. the processing method of super barrier diode according to claim 1, which is characterized in that be formed on the insulating layer
After Patterned masking layer, isotropic etching is carried out to the insulating layer, to form insulating layer mask structure, including in detail below
Step:
After being formed on the insulating layer the graphical mask layer, the insulating layer handled using wet etching, and/
Or dry etching processing is carried out to the insulating layer using isotropic etch gas, to form the insulating layer mask structure.
3. the processing method of super barrier diode according to claim 1, which is characterized in that in the specified of the epitaxial layer
Region forms the area PXing Ti, comprising the following specific steps
The area PXing Ti is formed in the specified region of the epitaxial layer using the first ion implantation technology.
4. the processing method of super barrier diode according to claim 3, which is characterized in that in the field through over etching
P-type region is formed in the epitaxial layer below the edge of oxide layer, meanwhile, the corresponding institute in top in the P-type region
It states polysilicon layer and forms p-type polysilicon structure, comprising the following specific steps
It is formed in the epitaxial layer below the edge of the field oxide through over etching using the second ion implantation technology
The P-type region, meanwhile, the corresponding polysilicon layer in top in the P-type region forms p-type polysilicon structure.
5. the processing method of super barrier diode according to claim 4, which is characterized in that the first ion implanting work
The Implantation Energy of skill is greater than the Implantation Energy of second ion implantation technology.
6. the processing method of super barrier diode according to claim 4, which is characterized in that the first ion implanting work
The implantation dosage of skill is greater than the implantation dosage of second ion implantation technology.
7. the processing method of super barrier diode according to claim 1, which is characterized in that forming the p-type polycrystalline
In the area PXing Ti of silicon structure, N+ type region and electrode of the formation with the P-type region disconnecting, including walk in detail below
It is rapid:
After forming the p-type polysilicon structure, N+ type polysilicon layer is formed in the N-type substrate.
8. the processing method of super barrier diode according to claim 7, which is characterized in that forming the p-type polycrystalline
In the area PXing Ti of silicon structure, N+ type region and electrode of the formation with the P-type region disconnecting, further include walking in detail below
It is rapid:
Anisotropic etching is carried out to the N+ type polysilicon layer, to remove the insulating layer mask structure top and the p-type
The N+ type polysilicon layer in body area, to be formed while be connect with the edge of the polysilicon layer, the field oxide and the area PXing Ti
The N+ type polysilicon side wall of touching；
It is made annealing treatment to the N+ type polysilicon side wall is formed, to be formed and the P-type at the edge in the area PXing Ti
The N+ type region of region disconnecting.
9. the processing method of super barrier diode according to claim 8, which is characterized in that forming the p-type polycrystalline
In the area PXing Ti of silicon structure, N+ type region and electrode of the formation with the P-type region disconnecting, further include walking in detail below
It is rapid:
After forming N+ type region, using one of metal sputtering processes, electroplating technology and evaporation process technique or more
Any combination of kind of technique, formed in the N-type substrate simultaneously with the insulating layer exposure mask, N+ type region, the area PXing Ti
The metal layer of contact, the metal layer are the electrode of the super barrier diode.
10. a kind of super barrier diode, which is characterized in that using the super barrier two as described in any one of claims 1 to 9
The processing method of pole pipe is made.
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