CN106098561A - The manufacture method of a kind of MOSFET element and device thereof - Google Patents
The manufacture method of a kind of MOSFET element and device thereof Download PDFInfo
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- CN106098561A CN106098561A CN201610590007.2A CN201610590007A CN106098561A CN 106098561 A CN106098561 A CN 106098561A CN 201610590007 A CN201610590007 A CN 201610590007A CN 106098561 A CN106098561 A CN 106098561A
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- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 239000010410 layer Substances 0.000 claims abstract description 106
- 238000005530 etching Methods 0.000 claims abstract description 54
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 238000001259 photo etching Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims abstract description 19
- 239000011159 matrix material Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- 239000011241 protective layer Substances 0.000 claims abstract description 14
- 238000000137 annealing Methods 0.000 claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000009413 insulation Methods 0.000 claims description 2
- 238000000407 epitaxy Methods 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 238000001657 homoepitaxy Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 16
- 230000005684 electric field Effects 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910017109 AlON Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The present invention relates to technical field of semiconductors, particularly relate to manufacture method and the device thereof of a kind of MOSFET element.Wherein, method utilizes epitaxy technology, and by heavily doped N-type semiconductor material with wide forbidden band as substrate, homoepitaxy goes out pressure drift region, PXing Ti district epitaxial layer and N+ source region epitaxial layer successively, forms matrix；Utilize photoetching and lithographic technique, matrix is offered grid region groove and schottky trench；In grid region, trench wall forms gate oxide through thermal oxide, at the inwall of gate oxide, forms gate electrode by deposit, photoetching, etching；It is passivated layer deposit at gate electrode outer surface, forms grid electrode insulating protective layer through photoetching, etching；Carry out Schottky barrier metal deposit, annealing on the surface of schottky trench, form Schottky diode；Finally give MOSFET element.The manufacture method of the MOSFET element that the present invention provides and device thereof, eliminate impurity doping and diffusion technique, enhance the reliability of gate oxide.
Description
Technical field
The present invention relates to technical field of semiconductor device, particularly relate to manufacture method and the device thereof of a kind of MOSFET element
Part.
Background technology
Wide bandgap semiconductor MOSFET (metal-oxide semiconductor (MOS) audion) device, especially silicon carbide MOSFET device
And gallium nitride MOSFET element is the device for power switching got most of the attention at present, its drive circuit is very simple, and with existing
The compatibility of power device drive circuit good.
But, there are two technical problem underlying in wide bandgap semiconductor MOSFET element design aspect: channel electrons migrates
Rate is low, and then causes the problem that the channel resistance of MOSFET is big；Two is not enough the asking of grid oxygen reliability under high temperature, high electric field
Topic.
Currently for the problem that channel electron mobility is low, settling mode mainly has two kinds:
One is to select suitable crystal orientation, because the electron mobility of different crystal orientations is different, mobility maximum can differ 5
Times, so selecting to be formed on the crystal face of high electron mobility raceway groove；Owing to the crystal orientation of carborundum is relatively random, so high electron mobility
The bad selection of crystal face.
Two is by special annealing process, improves channel interface state, improves channel electron mobility；This special
Annealing process operation inconvenience.
For the problem of trench gate oxygen reliability, settling mode mainly uses special grid oxygen material, such as AlN, AlON
Deng material；And the problem that only can not solve trench gate oxygen reliability well by special grid oxygen material.
It addition, the process aspect in wide bandgap semiconductor MOSFET element still suffers from difficult point, this difficult point essentially consists in PN
The form of knot, PN junction needs suitable impurity concentration and concentration distribution, and the mode solved at present is to use high temperature high energy ion
Repeatedly inject, then carry out high annealing；Repeatedly inject high temperature high energy ion and can damage the lattice of semiconductor material with wide forbidden band, and
And, needing producer to buy new equipment or new material, so can cause a large amount of inputs of fixed fund, cost increases.
To sum up, for prior art, the drawbacks described above how overcoming wide bandgap semiconductor MOSFET element is ability
The technical problem that field technique personnel are urgently to be resolved hurrily.
Summary of the invention
It is an object of the invention to provide manufacture method and the structure thereof of a kind of MOSFET element, to solve the problems referred to above.
In order to achieve the above object, the technical scheme is that and be achieved in that:
The invention provides the manufacture method of a kind of MOSFET element, comprise the steps:
Using one piece of heavily doped N-type semiconductor material with wide forbidden band as substrate, i.e. N+ substrate, surface carries out homogeneity thereon
N-type is epitaxially formed pressure drift region, then carries out p-type on the basis of described pressure drift region again and is epitaxially formed outside PXing Ti district
Prolong layer, finally on the basis of described PXing Ti district epitaxial layer, carry out N-type heavy doping again and be epitaxially formed N+ source region epitaxial layer；By institute
State pressure drift region, described PXing Ti district epitaxial layer and described N+ source region epitaxial layer and form matrix.
Upper surface at described N+ source region epitaxial layer deposits etching groove and shelters film, forms the first mask layer；And described
The surface of the first mask layer carries out photoetching, etching processing, and then in the middle position formation grid region of described N+ source region epitaxial layer
Etching groove window；In the position of described grid region etching groove window, described matrix is performed etching, etch into described pressure drift
Move the inside in district, form grid region groove.
At the inwall of described grid region groove, carry out thermal oxide or deposit, form gate oxide；In described gate oxide
Side, then be deposited, and form gate electrode by photoetching, etching；It is passivated layer deposit on the surface of described gate electrode, passes through
Photoetching, etching form grid electrode insulating protective layer.
Upper surface at described N+ source region epitaxial layer deposits etching groove and shelters film, forms the second mask layer；And described
The surface of the second mask layer carries out photoetching, etching processing, and then is formed in the position, both sides of the edge of described N+ source region epitaxial layer
Schottky trench etching window；In the position of described schottky trench etching window, described matrix is performed etching, etch into institute
State the inside of pressure drift region, form schottky trench, and the degree of depth of described schottky trench is greater than described grid region groove
The degree of depth, ultimately forms groove MOSFET.
Carry out Schottky barrier metal deposit, annealing on the surface of described schottky trench, form Schottky diode；Institute
State groove MOSFET and share metal electrode with described Schottky diode.
Preferably, as a kind of embodiment, the thickness of described PXing Ti district epitaxial layer is between 0.1 μm-1 μm.
Preferably, as a kind of embodiment, carrying out the later stage of homogeneity N-type extension on described N+ substrate, increase is mixed
Miscellaneous concentration, forms N1 dense doped epitaxial layer；In the position of described grid region etching groove window, when described matrix is performed etching,
Etch into the inside of described N1 dense doped epitaxial layer, form described grid region groove.
Preferably, as a kind of embodiment, when forming described gate oxide, the bottom of described gate oxide is increased
Thickness.
Accordingly, present invention also offers a kind of MOSFET element, including Schottky diode and groove MOSFET；
Wherein, described groove MOSFET includes N+ substrate, pressure drift region, PXing Ti district epitaxial layer and N the most successively
All it is in close contact between+source region epitaxial layer, and every adjacent two layers；The centre position, upper end of described groove MOSFET offers grid region
Groove；The upper end-face edge position of described groove MOSFET offers schottky trench；Described grid region groove and described Schottky ditch
The bottom surface of groove is respectively positioned on the inside of described pressure drift region；The degree of depth of described schottky trench is deep more than described grid region groove
Degree.
Described groove MOSFET also includes gate electrode；Described gate electrode is fixedly installed in the groove of described grid region；Described grid
Gate oxide is there is between district's groove and described gate electrode；Described gate electrode exceeds the peripheral setting of the part of described grid region groove
There is grid electrode insulating protective layer；
The lower end of described Schottky diode is coordinated by the upper end of described schottky trench with described groove MOSFET；Institute
The source electrode stating Schottky diode and described groove MOSFET shares metal electrode.
Preferably, as a kind of embodiment, described Schottky diode includes central authorities' groove and exterior protrusion；Described
Schottky trench coordinates with described exterior protrusion, and described central authorities groove coordinates with described grid electrode insulating protective layer.
Preferably, as a kind of embodiment, the thickness of described PXing Ti district epitaxial layer is between 0.1 μm-1 μm.
Preferably, as a kind of embodiment, the end face of described pressure drift region is additionally provided with the dense doped epitaxial of N1
Layer；Described N1 dense doped epitaxial floor is between described pressure drift region and described PXing Ti district epitaxial layer.
Preferably, as a kind of embodiment, the bottom surface of described grid region groove is positioned in described N1 dense doped epitaxial layer.
Preferably, as a kind of embodiment, the bottom thickness of described gate oxide is more than the side of described gate oxide
Face thickness.
Compared with prior art, this have the advantage that:
The manufacture method of a kind of MOSFET element that the present invention provides and structure thereof, use wide bandgap semiconductor as material
Material, using heavily doped N-type semiconductor material with wide forbidden band as substrate；Epitaxy technology is utilized to carry out successively from the upper surface of substrate same
Matter N-type extension, p-type extension and N-type heavy doping extension, from bottom to top sequentially form pressure drift region, PXing Ti district epitaxial layer and N+
Source region epitaxial layer, this makes the doped region of wide bandgap semiconductor MOSFET element, all carries out during extension sheet epitaxy,
Overcome the impurity doping of semiconductor material with wide forbidden band, the problem of diffusion difficulty, and this manufacture method can be at existing silicon
Produce on the production line of material power MOSFET device, be not required to buy new equipment, thus saved the biggest cost.
In carrying out the etching process of grid region groove and schottky trench, deposit ditch needing the matrix surface performed etching
Groove etched shelter film, ensure when matrix is performed etching as far as possible, do not damage matrix integrity degree elsewhere；Use light afterwards
Carve, lithographic technique sequentially forms grid region groove and schottky trench；Wherein, the bottom position of grid region groove will be in pressure drift region
In, so, the architecture quality of guarantee raceway groove and electric field shielding effect.
After grid region groove is formed, within it on wall, carry out thermal oxide or deposit, form gate oxide；Afterwards, at gate oxidation
The inner side of layer is deposited, and carries out photoetching, etching formation gate electrode in the structure that deposit is formed；Then, at gate electrode
Surface is passivated layer deposit, and passivation layer carries out photoetching, etching formation grid electrode insulating protective layer, and grid electrode insulating is protected
Gate electrode is surrounded completely by layer in the part on groove top, grid region so that gate electrode insulate with external structure, obtains final ditch
Groove MOSFET.In schottky trench, finally carry out Schottky barrier metal deposit and annealing, form Schottky diode, Xiao Te
Based diode forms a blind zone to the subregion being enclosed in internal pressure drift region.
It will be apparent that the degree of depth of schottky trench is more than the degree of depth of grid region groove so that at wide bandgap semiconductor MOSFET device
The when of part carrying voltage, schottky junction forms electric field shielding to the bottom of grid region groove, and then reduces grid region channel bottom
The electric field of gate oxide, improves the reliability of gate oxide.
It addition, Schottky diode and the source electrode metal electrode to be shared of groove MOSFET.
Accompanying drawing explanation
In order to be illustrated more clearly that the specific embodiment of the invention or technical scheme of the prior art, below will be to specifically
In embodiment or description of the prior art, the required accompanying drawing used is briefly described, it should be apparent that, in describing below
Accompanying drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not paying creative work
Put, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
The MOSFET element that in the manufacture method of the MOSFET element that Fig. 1 provides for the embodiment of the present invention, step one is formed
Sectional structure schematic diagram；
The MOSFET element that in the manufacture method of the MOSFET element that Fig. 2 provides for the embodiment of the present invention, step 2 is formed
Sectional structure schematic diagram；
The MOSFET element that in the manufacture method of the MOSFET element that Fig. 3 provides for the embodiment of the present invention, step 3 is formed
Sectional structure schematic diagram；
The MOSFET element that in the manufacture method of the MOSFET element that Fig. 4 provides for the embodiment of the present invention, step 4 is formed
Sectional structure schematic diagram；
The MOSFET element that in the manufacture method of the MOSFET element that Fig. 5 provides for the embodiment of the present invention, step 5 is formed
Sectional structure schematic diagram；
The manufacture method of the MOSFET element that Fig. 6 provides for the embodiment of the present invention increases the situation of N1 dense doped epitaxial layer
Under, the sectional structure schematic diagram of the MOSFET element that step one is formed；
The manufacture method of the MOSFET element that Fig. 7 provides for the embodiment of the present invention increases the situation of N1 dense doped epitaxial layer
Under, the sectional structure schematic diagram of the MOSFET element that step 2 is formed；
The manufacture method of the MOSFET element that Fig. 8 provides for the embodiment of the present invention increases the situation of N1 dense doped epitaxial layer
Under, the sectional structure schematic diagram of the MOSFET element that step 3 is formed；
The manufacture method of the MOSFET element that Fig. 9 provides for the embodiment of the present invention increases the situation of N1 dense doped epitaxial layer
Under, the sectional structure schematic diagram of the MOSFET element that step 4 is formed；
The manufacture method of the MOSFET element that Figure 10 provides for the embodiment of the present invention increases the feelings of N1 dense doped epitaxial layer
Under condition, the sectional structure schematic diagram of the MOSFET element that step 5 is formed；
The manufacture method of the MOSFET element that Figure 11 provides for the embodiment of the present invention increases in step 3 gate oxide
Bottom thickness in the case of, the sectional structure schematic diagram of the MOSFET element of formation；
The manufacture method of the MOSFET element that Figure 12 provides for the embodiment of the present invention increases the bottom thickness of gate oxide
In the case of, the sectional structure schematic diagram of the MOSFET element that step 4 is formed；
The manufacture method of the MOSFET element that Figure 13 provides for the embodiment of the present invention increases the bottom thickness of gate oxide
In the case of, the sectional structure schematic diagram of the MOSFET element that step 5 is formed；
The manufacture method of the MOSFET element that Figure 14 provides for the embodiment of the present invention increases the feelings of N1 dense doped epitaxial layer
Under condition, in step 3, increase again the sectional structure schematic diagram of the MOSFET element of the bottom thickness formation of gate oxide；
The manufacture method of the MOSFET element that Figure 15 provides for the embodiment of the present invention increases N1 dense doped epitaxial layer and increasing
In the case of adding the bottom thickness of gate oxide, the sectional structure schematic diagram of the MOSFET element that step 4 is formed；
The manufacture method of the MOSFET element that Figure 16 provides for the embodiment of the present invention increases N1 dense doped epitaxial layer and increasing
In the case of adding the bottom thickness of gate oxide, the sectional structure schematic diagram of the MOSFET element that step 5 is formed.
Description of reference numerals:
Schottky diode 1；Groove MOSFET 2；
Exterior protrusion 11；
N+ substrate 21；Pressure drift region 22；PXing Ti district epitaxial layer 23；
N+ source region epitaxial layer 24；Grid region groove 25；Schottky trench 26；
Gate electrode 27；Gate oxide 28；Grid electrode insulating protective layer 29；
N1 dense doped epitaxial layer 221；Blind zone 222.
Detailed description of the invention
Below in conjunction with accompanying drawing, technical scheme is clearly and completely described, it is clear that described enforcement
Example is a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention, ordinary skill
The every other embodiment that personnel are obtained under not making creative work premise, broadly falls into the scope of protection of the invention.
In describing the invention, it should be noted that term " " center ", " on ", D score, "left", "right", " interior ",
Orientation or the position relationship of the instruction such as " outward " are based on orientation shown in the drawings or position relationship, are for only for ease of and describe this
Bright and simplification describes rather than indicates or imply that the device of indication or element must have specific orientation, with specific orientation
Structure and operation, be therefore not considered as limiting the invention.Additionally, term " first ", " second " are only used for describing purpose,
And it is not intended that indicate or hint relative importance.
In describing the invention, it should be noted that unless otherwise clearly defined and limited, term " is connected ", " even
Connect " should be interpreted broadly, connect for example, it may be fixing, it is also possible to be to removably connect, or be integrally connected；It can be machine
Tool connects, it is also possible to be electrical connection；Can be to be joined directly together, it is also possible to be indirectly connected to by intermediary, can be two units
Connection within part.For the ordinary skill in the art, above-mentioned term can be understood in the present invention with concrete condition
Concrete meaning.
Below by specific embodiment and combine accompanying drawing the present invention is described in further detail.
See Fig. 1-Fig. 5, embodiments provide the manufacture method of a kind of MOSFET element, comprise the steps；
Step one, by one piece of heavily doped N-type wide bandgap semiconductor (preferably manufacturing silicon carbide semiconductor or gallium nitride semiconductor)
Material is as substrate, i.e. N+ substrate, surface carries out homogeneity N-type and is epitaxially formed pressure drift region 22, then in pressure drift thereon
Carry out p-type again on the basis of moving district 22 and be epitaxially formed PXing Ti district epitaxial layer 23, finally on the basis of PXing Ti district epitaxial layer 23
Carry out N-type heavy doping again and be epitaxially formed N+ source region epitaxial layer 24；By above-mentioned pressure drift region 22, PXing Ti district epitaxial layer 23 and N+
Source region epitaxial layer 24 forms matrix (referring specifically to Fig. 1).
Step 2, the upper surface at N+ source region epitaxial layer 24 deposits etching groove and shelters film, forms the first mask layer (in figure
Not shown)；And carry out photoetching, etching processing on the surface of the first mask layer, and then in the centre position of N+ source region epitaxial layer 24
Place forms grid region etching groove window (not shown)；
In the position of grid region etching groove window, matrix is performed etching, etch into the inside of pressure drift region 22, formed
Grid region groove 25 (referring specifically to Fig. 2).
Step 3, at the inwall of grid region groove 25, carries out thermal oxide or deposit, forms gate oxide 28；
In the inner side of gate oxide 28, then it is deposited, and forms gate electrode 27 by photoetching, etching；
It is passivated layer deposit on the surface of gate electrode 27, forms grid electrode insulating protective layer 29 (tool by photoetching, etching
Body sees Fig. 3).
Step 4, the upper surface at N+ source region epitaxial layer 24 deposits etching groove and shelters film, forms the second mask layer (in figure
Not shown)；And carry out photoetching, etching processing on the surface of the second mask layer, and then in the both sides of the edge of N+ source region epitaxial layer 24
Position forms schottky trench etching window (not shown)；
In the position of schottky trench etching window, described matrix is performed etching, etch into the interior of pressure drift region 22
Portion, forms schottky trench 26；And the degree of depth of schottky trench 26 is greater than the degree of depth of grid region groove 25；Ultimately form groove
MOSFET2 (referring specifically to Fig. 4).
Step 5, carries out Schottky barrier metal deposit, annealing on the surface of schottky trench 26, forms Schottky two pole
Pipe 1；Groove MOSFET 2 and Schottky diode 1 share metal electrode (referring specifically to Fig. 5).
In the manufacture method of above-mentioned MOSFET element, use wide bandgap semiconductor (preferably manufacturing silicon carbide semiconductor or nitridation
Gallium quasiconductor) as material, using heavily doped N-type semiconductor material with wide forbidden band as substrate；Utilize epitaxy technology from substrate
Upper surface carries out homogeneity N-type extension, p-type extension and N-type heavy doping extension successively, from bottom to top sequentially forms pressure drift region
22, PXing Ti district epitaxial layer 23 and N+ source region epitaxial layer 24, this makes the doped region of wide bandgap semiconductor MOSFET element, all
Carry out during extension sheet epitaxy, overcome the impurity doping of semiconductor material with wide forbidden band, the problem of diffusion difficulty；With
Time, this manufacture method can produce on the production line of existing silicon materials power MOSFET device, is not required to buy newly
Equipment, thus saved the biggest cost.
In the etching process carrying out grid region groove 25 and schottky trench 26, form sediment needing the matrix surface performed etching
Long-pending etching groove shelters film, ensures when performing etching matrix as far as possible, does not damage matrix integrity degree elsewhere；Adopt afterwards
Grid region groove 25 and schottky trench 26 is sequentially formed with photoetching, lithographic technique；Wherein, the bottom position of grid region groove 25 will be
In pressure drift region 22, so, the architecture quality of guarantee raceway groove and electric field shielding effect.
After grid region groove 25 is formed, within it on wall, carry out thermal oxide or deposit, form gate oxide 28；Afterwards, exist
The inner side of gate oxide 28 is deposited, and carries out photoetching, etching formation gate electrode 27 in the structure that deposit is formed；Then,
It is passivated layer deposit on the surface of gate electrode 27, and passivation layer is carried out photoetching, etching formation grid electrode insulating protective layer 29,
Gate electrode 27 is surrounded completely by grid electrode insulating protective layer 29 in the part on the top of grid region groove 25 so that gate electrode 27 is with outer
Portion's structural insulation, obtains final groove MOSFET 2.Last carry out in schottky trench 26 Schottky barrier metal deposit and
Annealing, forms Schottky diode 1, the subregion shape of the Schottky diode 1 pressure drift region 22 to surrounding therein
Become a blind zone 222.
It will be apparent that the degree of depth of schottky trench 26 is more than the degree of depth of grid region groove 25 so that at wide bandgap semiconductor
The when of MOSFET element carrying voltage, schottky junction forms electric field shielding to the bottom of grid region groove 25, and then reduces grid
The electric field of the gate oxide 28 of the bottom of district's groove 25, improves the reliability of gate oxide 28.
It addition, Schottky diode 1 and the source electrode metal electrode to be shared of groove MOSFET 2.
It should be noted that N+ i.e. represents heavily doped N-type semiconductor.
Especially, in order to increase the mobility of the channel electrons of wide bandgap semiconductor MOSFET element further, reduce ditch
Road resistance, during extension, the PXing Ti district epitaxial layer 23 of groove MOSFET 2 uses ultra-thin p-type extension, and thickness is at 0.1 μ
Between m-1 μm, and on the premise of there is not tunnel breakdown, it is thin that PXing Ti district epitaxial layer 23 should be tried one's best, so that MOSFET
Channel length is the shortest, and then reduces the purpose of channel resistance.
In order to further enhance the practicality of the manufacture method of the MOSFET element that the embodiment of the present invention provides, it is also possible to real
The following three kinds of improved procedures of row.
See Fig. 6, Fig. 7, Fig. 8, Fig. 9 or Figure 10, the situation of increase N1 dense doped epitaxial layer 221:
In view of the Schottky diode 1 blind zone 222 to groove MOSFET 2, there is the loss of conducting resistance, so,
Time delay outside, for reducing loss, it is preferred that the epitaxial layer in this region is increased doping content, i.e. carries out on N+ substrate 21
In the later stage of homogeneity N-type extension, increase doping content, form N1 dense doped epitaxial layer 221, reduce the resistance of blind zone 222.
For adapting to above-mentioned preferred version, the bottom surface of grid region groove 25 should be positioned in N1 dense doped epitaxial layer 221, and this just requires
When etching grid region groove 25, the bottom position of grid region groove 25 should be got hold of, N1 to be etched into dense doped epitaxial layer 221
Internal.
See Figure 11, Figure 12 or Figure 13, the situation of the bottom thickness of increase gate oxide 28:
In view of increasing the bottom voltage endurance capability of grid region groove 25 in groove MOSFET 2 so that wide bandgap semiconductor
The performance of MOSFET element increases, so, when forming gate oxide 28, it is preferable that increase the bottom of gate oxide 28
Thickness.
See Figure 14, Figure 15 or Figure 16, increase N1 dense doped epitaxial layer 221 and the bottom thickness increasing gate oxide 28
Assembled scheme, both can reduce the resistance of blind zone 222, can improve again the performance of wide bandgap semiconductor MOSFET element.
Accordingly, present invention also offers a kind of MOSFET element, see Fig. 1-Fig. 5, it is according to above-mentioned MOSFET device
The manufacture method of part manufactures, including Schottky diode 1 and groove MOSFET 2.
Wherein, groove MOSFET 2 includes N+ substrate 21, pressure drift region 22, PXing Ti district epitaxial layer 23 the most successively
All it is in close contact with between N+ source region epitaxial layer 24, and every adjacent two layers；The centre position, upper end of groove MOSFET 2 offers grid
District's groove 25；The upper end-face edge position of groove MOSFET 2 offers schottky trench 26；Grid region groove 25 and schottky trench 26
Bottom surface be respectively positioned on the inside of pressure drift region 22；The degree of depth of schottky trench 26 is more than the degree of depth of grid region groove 25.
Groove MOSFET 2 also includes gate electrode 27；Gate electrode 27 is fixedly installed in grid region groove 25；Grid region groove 25 with
Gate oxide 28 is there is between gate electrode 27；The periphery of the part that gate electrode 27 exceeds grid region groove 25 is provided with grid electrode insulating
Protective layer 29.
The lower end of Schottky diode 1 is coordinated with the upper end of groove MOSFET 2 by schottky trench 26；Schottky two pole
Pipe 1 shares metal electrode with the source electrode of groove MOSFET 2.
It should be noted that the MOSFET element that the present invention provides, it is not necessary to use special grid oxygen material just to overcome ditch
The problem that road reliability of the gate oxide is not enough so that the manufacturing process of wide bandgap semiconductor MOSFET element is more convenient, saves
Cost.
In the concrete structure of the MOSFET element of present invention offer, Schottky diode 1 includes central authorities' groove (in figure not
Illustrate) and exterior protrusion 11；Exterior protrusion 11 is used for coordinating with the schottky trench 26 on groove MOSFET 2, and central authorities' groove is used
Coordinate with the grid electrode insulating protective layer 29 of groove MOSFET 2 upper end.
Especially, the thickness of PXing Ti district epitaxial layer 23 should be arranged between 0.1 μm-1 μm, to increase wide bandgap semiconductor
Channel electron mobility in MOSFET element, reduces channel resistance.
According to three kinds of improved procedures of the manufacture method of above-mentioned MOSFET element, following three kinds of structures can be formed:
See Fig. 6-Figure 10, the situation of increase N1 dense doped epitaxial layer 221:
On device architecture, N1 dense doped epitaxial layer 221 is arranged on the end face of pressure drift region 22, i.e. outside the dense doping of N1
Prolong floor 221 between the district's epitaxial layer 23 of pressure drift region 22 and PXing Ti；It addition, N1 dense doped epitaxial layer 221 is positioned at blind zone
In 222, the bottom surface of grid region groove 25 is positioned in N1 dense doped epitaxial layer 221, to arrive purpose as above.
See Figure 11-Figure 13, the situation of the bottom thickness of increase gate oxide 28:
On device architecture, the bottom thickness of gate oxide 28 is greater than its lateral thickness, and then broad stopband is partly led
The performance of body MOSFET element increases.
See Figure 14-Figure 16, increase the combination side of N1 dense doped epitaxial layer 221 and the bottom thickness increasing gate oxide 28
Case, both can reduce the resistance of blind zone 222, can improve again the performance of wide bandgap semiconductor MOSFET element.
Concrete, schottky trench 26 is annular structural part, and utilizes this structure by the top half of groove MOSFET 2
It is surrounded, and in pressure drift region 22, forms blind zone 222.
Especially, the N+ substrate 21 structure to being disposed thereon, serve supporting role, so the thickness of N+ substrate 21 is not
Can be the thinnest, otherwise it is susceptible to deformation, thickness can be arranged between 5 μm-500 μm.
It addition, N+ source region epitaxial layer should be the thinnest, thickness should be less than 1 μm；Optimum, thickness elects 0.5 μm as.
In sum, the embodiment of the present invention provides the manufacture method of MOSFET element and device thereof, it is possible to overcome wide taboo
The impurity doping of carrying semiconductor material, the problem of diffusion difficulty, and can give birth on existing silicon power MOSFET production line
Produce, meanwhile, it is capable to reduce channel resistance, strengthen the reliability of gate oxide；Make the property of wide bandgap semiconductor MOSFET element
Can be improved, manufacturing cost is minimized.So, the manufacture method of the MOSFET element that the embodiment of the present invention provides and device thereof
Part, will bring good market prospect.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, it is not intended to limit；To the greatest extent
The present invention has been described in detail by pipe with reference to foregoing embodiments, it will be understood by those within the art that: it depends on
So the technical scheme described in foregoing embodiments can be modified, or the most some or all of technical characteristic is entered
Row equivalent；And these amendments or replacement, do not make the essence of appropriate technical solution depart from various embodiments of the present invention technology
The scope of scheme.
Claims (10)
1. the manufacture method of a MOSFET element, it is characterised in that comprise the steps:
Using one piece of heavily doped N-type semiconductor material with wide forbidden band as substrate, i.e. N+ substrate, surface carries out homogeneity N-type thereon
It is epitaxially formed pressure drift region, on the basis of described pressure drift region, then carries out p-type be again epitaxially formed PXing Ti district extension
Layer, finally carries out N-type heavy doping again on the basis of described PXing Ti district epitaxial layer and is epitaxially formed N+ source region epitaxial layer；By described
Pressure drift region, described PXing Ti district epitaxial layer and described N+ source region epitaxial layer form matrix；
Upper surface at described N+ source region epitaxial layer deposits etching groove and shelters film, forms the first mask layer；And described first
The surface of mask layer carries out photoetching, etching processing, and then at the middle position formation grid region groove of described N+ source region epitaxial layer
Etching window；
In the position of described grid region etching groove window, described matrix is performed etching, etch into the interior of described pressure drift region
Portion, forms grid region groove；
At the inwall of described grid region groove, carry out thermal oxide or deposit, form gate oxide；
In the inner side of described gate oxide, then it is deposited, and forms gate electrode by photoetching, etching；
It is passivated layer deposit on the surface of described gate electrode, forms grid electrode insulating protective layer by photoetching, etching；
Upper surface at described N+ source region epitaxial layer deposits etching groove and shelters film, forms the second mask layer；And described second
The surface of mask layer carries out photoetching, etching processing, and then forms Xiao Te in the position, both sides of the edge of described N+ source region epitaxial layer
Base etching groove window；
In the position of described schottky trench etching window, described matrix is performed etching, etch into described pressure drift region
Inside, forms schottky trench, and the degree of depth of described schottky trench is greater than the degree of depth of described grid region groove, ultimately forms ditch
Groove MOSFET；
Carry out Schottky barrier metal deposit, annealing on the surface of described schottky trench, form Schottky diode；Described ditch
Groove MOSFET and described Schottky diode share metal electrode.
2. the manufacture method of MOSFET element as claimed in claim 1, it is characterised in that
The thickness of described PXing Ti district epitaxial layer is between 0.1 μm-1 μm.
3. the manufacture method of MOSFET element as claimed in claim 1, it is characterised in that
Described N+ substrate is carried out the later stage of homogeneity N-type extension, increase doping content, form N1 dense doped epitaxial layer；Described
The position of grid region etching groove window, when performing etching described matrix, etches into the inside of described N1 dense doped epitaxial layer, shape
Become described grid region groove.
4. the manufacture method of the MOSFET element as described in any one of claim 1-3, it is characterised in that
When forming described gate oxide, increase the bottom thickness of described gate oxide.
5. a MOSFET element, it is characterised in that include Schottky diode and groove MOSFET；
Wherein, described groove MOSFET includes N+ substrate, pressure drift region, PXing Ti district epitaxial layer and N+ source the most successively
All it is in close contact between district's epitaxial layer, and every adjacent two layers；The centre position, upper end of described groove MOSFET offers grid region ditch
Groove；The upper end-face edge position of described groove MOSFET offers schottky trench；Described grid region groove and described schottky trench
Bottom surface be respectively positioned on the inside of described pressure drift region；The degree of depth of described schottky trench is more than the degree of depth of described grid region groove；
Described groove MOSFET also includes gate electrode；Described gate electrode is fixedly installed in the groove of described grid region；Described grid region ditch
Gate oxide is there is between groove and described gate electrode；The periphery of the part that described gate electrode exceeds described grid region groove is provided with grid
Electrode insulation protective layer；
The lower end of described Schottky diode is coordinated by the upper end of described schottky trench with described groove MOSFET；
Described Schottky diode shares metal electrode with the source electrode of described groove MOSFET.
6. MOSFET element as claimed in claim 5, it is characterised in that
Described Schottky diode includes central authorities' groove and exterior protrusion；Described schottky trench coordinates with described exterior protrusion,
Described central authorities groove coordinates with described grid electrode insulating protective layer.
7. MOSFET element as claimed in claim 5, it is characterised in that
The thickness of described PXing Ti district epitaxial layer is between 0.1 μm-1 μm.
8. MOSFET element as claimed in claim 5, it is characterised in that
N1 dense doped epitaxial layer it is additionally provided with on the end face of described pressure drift region；Described N1 dense doped epitaxial layer is positioned at described resistance to
Between pressure drift region and described PXing Ti district epitaxial layer.
9. MOSFET element as claimed in claim 8, it is characterised in that
The bottom surface of described grid region groove is positioned in described N1 dense doped epitaxial layer.
10. the MOSFET element as described in any one of claim 5-9, it is characterised in that
The bottom thickness of described gate oxide is more than the lateral thickness of described gate oxide.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107706230A (en) * | 2017-09-28 | 2018-02-16 | 中国电子科技集团公司第五十五研究所 | A kind of power trench MOS type device and preparation method |
| CN112086507A (en) * | 2020-10-22 | 2020-12-15 | 电子科技大学 | SiC MOSFET device cell and manufacturing method thereof |
| CN114400184A (en) * | 2022-03-24 | 2022-04-26 | 北京芯可鉴科技有限公司 | LDMOSFET (Metal-oxide-semiconductor field Effect transistor) and manufacturing method thereof |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08204179A (en) * | 1995-01-26 | 1996-08-09 | Fuji Electric Co Ltd | Silicon carbide trench mosfet |
| JP2002314078A (en) * | 2001-04-17 | 2002-10-25 | Rohm Co Ltd | Semiconductor device and its manufacturing method |
| US20090283776A1 (en) * | 2008-04-17 | 2009-11-19 | Fuji Electric Device Technology Co., Ltd. | Wide band gap semiconductor device and method for producing the same |
| US20100224886A1 (en) * | 2009-03-04 | 2010-09-09 | Fuji Electric Systems Co. Ltd. | P-channel silicon carbide mosfet |
| US20100271852A1 (en) * | 2009-04-28 | 2010-10-28 | Fuji Electric Systems Co., Ltd. | Power conversion circuit |
| CN101882583A (en) * | 2005-04-06 | 2010-11-10 | 飞兆半导体公司 | Trenched-gate field effect transistors and forming method thereof |
| JP2012238769A (en) * | 2011-05-12 | 2012-12-06 | Shindengen Electric Mfg Co Ltd | Semiconductor element |
| JP2012243985A (en) * | 2011-05-20 | 2012-12-10 | Shindengen Electric Mfg Co Ltd | Semiconductor device and method for manufacturing the same |
| CN102859689A (en) * | 2010-04-28 | 2013-01-02 | 日产自动车株式会社 | Semiconductor device |
| JP2015233146A (en) * | 2015-07-15 | 2015-12-24 | 三菱電機株式会社 | Semiconductor device and manufacturing method of the same |
| CN105431949A (en) * | 2014-07-11 | 2016-03-23 | 新电元工业株式会社 | Semiconductor device and method for producing semiconductor device |
| CN205845957U (en) * | 2016-07-25 | 2016-12-28 | 吉林华微电子股份有限公司 | A kind of MOSFET element |
-
2016
- 2016-07-25 CN CN201610590007.2A patent/CN106098561A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08204179A (en) * | 1995-01-26 | 1996-08-09 | Fuji Electric Co Ltd | Silicon carbide trench mosfet |
| JP2002314078A (en) * | 2001-04-17 | 2002-10-25 | Rohm Co Ltd | Semiconductor device and its manufacturing method |
| CN101882583A (en) * | 2005-04-06 | 2010-11-10 | 飞兆半导体公司 | Trenched-gate field effect transistors and forming method thereof |
| US20090283776A1 (en) * | 2008-04-17 | 2009-11-19 | Fuji Electric Device Technology Co., Ltd. | Wide band gap semiconductor device and method for producing the same |
| US20100224886A1 (en) * | 2009-03-04 | 2010-09-09 | Fuji Electric Systems Co. Ltd. | P-channel silicon carbide mosfet |
| US20100271852A1 (en) * | 2009-04-28 | 2010-10-28 | Fuji Electric Systems Co., Ltd. | Power conversion circuit |
| CN102859689A (en) * | 2010-04-28 | 2013-01-02 | 日产自动车株式会社 | Semiconductor device |
| JP2012238769A (en) * | 2011-05-12 | 2012-12-06 | Shindengen Electric Mfg Co Ltd | Semiconductor element |
| JP2012243985A (en) * | 2011-05-20 | 2012-12-10 | Shindengen Electric Mfg Co Ltd | Semiconductor device and method for manufacturing the same |
| CN105431949A (en) * | 2014-07-11 | 2016-03-23 | 新电元工业株式会社 | Semiconductor device and method for producing semiconductor device |
| JP2015233146A (en) * | 2015-07-15 | 2015-12-24 | 三菱電機株式会社 | Semiconductor device and manufacturing method of the same |
| CN205845957U (en) * | 2016-07-25 | 2016-12-28 | 吉林华微电子股份有限公司 | A kind of MOSFET element |
Non-Patent Citations (1)
| Title |
|---|
| 杨铁军主编: "电子材料科研开发、生产加工技术与质量检测标准实用手册 第1卷", 金版电子出版公司, pages: 150 - 152 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107706230A (en) * | 2017-09-28 | 2018-02-16 | 中国电子科技集团公司第五十五研究所 | A kind of power trench MOS type device and preparation method |
| CN107706230B (en) * | 2017-09-28 | 2020-06-16 | 中国电子科技集团公司第五十五研究所 | Power groove gate MOS device and preparation method thereof |
| CN112086507A (en) * | 2020-10-22 | 2020-12-15 | 电子科技大学 | SiC MOSFET device cell and manufacturing method thereof |
| CN114400184A (en) * | 2022-03-24 | 2022-04-26 | 北京芯可鉴科技有限公司 | LDMOSFET (Metal-oxide-semiconductor field Effect transistor) and manufacturing method thereof |
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