CN103199107A - Semiconductor device and manufacturing method - Google Patents
Semiconductor device and manufacturing method Download PDFInfo
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- CN103199107A CN103199107A CN2012100041074A CN201210004107A CN103199107A CN 103199107 A CN103199107 A CN 103199107A CN 2012100041074 A CN2012100041074 A CN 2012100041074A CN 201210004107 A CN201210004107 A CN 201210004107A CN 103199107 A CN103199107 A CN 103199107A
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Abstract
The invention discloses a semiconductor device. A graded region is arranged in a drift region of the semiconductor device, the doping concentration of the graded region increases slowly, the graded region is located on one side of the back face of a silicon wafer, and the doping concentration of the graded region is larger than the doping concentration of a uniform region. The highly doping graded region can ensure lower on resistance obtained by the semiconductor device, and at the same time, the velocity of increase of the doping concentration of the graded region is controlled well, the defect that a built-in electric field in a filed blocking layer is large in an existing filed blocking-type semiconductor device is overcome, accordingly a current dropping speed of the semiconductor device can be effectively controlled when the semiconductor device is cut off, and reliability of the device can be improved. The invention further discloses a manufacturing method of the semiconductor device.
Description
Technical field
The present invention relates to semiconductor integrated circuit and make the field, particularly relate to a kind of semiconductor device; The invention still further relates to a kind of manufacture method of semiconductor device.
Background technology
In semiconductor high-voltage device, no matter be igbt (IGBT), fast recovery diode (FRD), or MOSFET, break-over of device when the grid of device adds positive bias-voltage, all wish the power consumption minimum under the conducting state this moment, and the conducting state pressure drop of also namely wishing device is that on-state voltage drop is little, utilizes thinner silicon chip can directly reduce the on-state voltage drop of device, but the decline of thickness of detector can reduce the voltage endurance capability of device under the reverse breakdown situation, and both are a pair of contradiction.In order to solve above-mentioned contradiction, a barrier layer is referred in the semiconductor high-voltage device, forms semiconductor device; Be that the IGBT that N-type is mixed is that N-type IGBT is example with the drift region, as shown in Figure 1, structural representation for a kind of existing blocking-up type IGBT, have a blocking-up type IGBT now and do not have the difference of the IGBT of a barrier layer to be, the field barrier layer 3 that comprises a N-type at N- type silicon chip 1 and 4 at P type emitter, the carrier concentration of described barrier layer 3 is greater than the carrier concentration of described silicon chip 1, and the described silicon chip 1 between P trap 7 and described field barrier layer 3 is formed the N-type drift region of device.Other structure of existing blocking-up type IGBT is identical with the structure of the IGBT of other non-blocking-up type, comprise: in described silicon chip 1, be formed with P trap 7, in P trap 7, be formed with N+ source 8, grid oxygen 5, polysilicon gate 6, the described P trap 7 in described polysilicon 6 cover parts also forms channel region in covering place, and channel region connects described N+ source 8 and described silicon chip 1; The P+ contact injects 11, is connected with described P trap 7 and is used for drawing described P trap 7, contact hole 10, and surface metal 12 and back metal 14.As shown in Figure 1, wherein section A is the formation zone of described P trap 7 to the zone between the B of cross section, section A is to the drift region that comprises also between the B of cross section that part is formed by the N-type doped region of described silicon chip 1, the cross section B drift region that to be another part to the zone between the C of cross section formed by the N-type doped region of described silicon chip 1.Cross section C is described barrier layer 3 to the zone between the D of cross section.Cross section D is P type emitter 4 to the zone between the E of cross section.
As shown in Figure 2, for having a distribution schematic diagram of the impurity concentration from described P trap 7 to 4 at described P type emitter of blocking-up type IGBT now; Fig. 3 is operated in reverse blocking state Electric Field Distribution of following time schematic diagram corresponding to the device among Fig. 2.As shown in Figure 2, cross section C arrives the impurity concentration of the field barrier layer between the D of cross section greater than the impurity concentration of cross section B to the N-type drift region between the C of cross section, and the impurity in the zone of the P correspondence among Fig. 2 is p type impurity.As shown in Figure 3, be a trapezium structure when field penetration is crossed described N-type drift region during device work, this trapezoidal area is the voltage endurance capability of described N-type drift region; If there be not described barrier layer 3, can be a triangular structure when field penetration is crossed described N-type drift region during device work, voltage endurance capability at this moment is the corresponding area of triangle BHD; The voltage endurance capability of device can be improved when barrier layer was obviously arranged.
Existing blocking-up type manufacturing method of semiconductor device is that the ion that carries out N-type impurity such as phosphorus or arsenic after the positive technology of device is finished overleaf injects, and activates by annealing afterwards, and this annealing comprises common high-temperature thermal annealing and laser annealing.Because the device front has been formed with metal materials such as AL before the annealing, annealing temperature generally can not be higher than 500 degrees centigrade when adopting common thermal annealing technology, and the efficient that the field barrier layer ion of injection is activated is not high, can't reach the effect of diffusion simultaneously.And adopt laser annealing to raise the efficiency greatly, the degree of depth that laser annealing can reach is limited, and technology cost height, therefore also can not activate for a long time, impurity is effectively spread, and the ion distribution of the field barrier layer that obtains so all is comparison drastic change.The drastic change of this carrier concentration, be varied in the process of off state by conducting state at device, because the internal electric field in the barrier layer on the scene is bigger, electron stream when having accelerated on-state in the drift region is through the speed of N-type field barrier layer, thereby the rapid decline that causes electric current descends the flexibility of switch, is easy to produce a high crest voltage and makes component failure under inductive load; On the other hand, the P+N barrier layer is to be easy to cause local electronics and the larger difference in hole in the PN junction of P type emitter 4 and a barrier layer 3 overleaf in the short time, and very high electric field of formation also is easy to make component failure near this knot.
Summary of the invention
Technical problem to be solved by this invention provides a kind of semiconductor device, when having lower conducting resistance, the electric current decrease speed of device when turn-offing is effectively controlled, thereby can improves the reliability of device.The present invention also provides a kind of manufacture method of semiconductor device.
For solving the problems of the technologies described above, semiconductor device provided by the invention comprises: one is formed at first p type island region in the front of silicon chip.One is formed at second p type island region of described silicon chip back, is formed with backplate at the back side of described second p type island region.One N-type district, this N-type district are positioned between described first p type island region and described second p type island region, and described N-type district is the drift region of described semiconductor device; Described N-type district comprises the first N-type district and the second N-type district, and the impurity concentration in the described first N-type district is even, and the impurity concentration in the described second N-type district is a gradual structure; The described second N-type district is positioned between the described first N-type district and described second p type island region, the impurity concentration in the described first N-type district is first impurity concentration, and the impurity concentration in the described second N-type district increases on the basis of described first impurity concentration and the impurity concentration in the described second N-type district comprises a peak value at least; In the zone that the impurity concentration of each described peak region in the described second N-type district of the described first N-type district on the direction of described second p type island region increases, in the described second N-type district from impurity concentration be the position of described first impurity concentration to impurity concentration be the impurity concentration in the described second N-type district 10 times the position of described first impurity concentration with the maximum of advancing the speed of position less than the 10C1/ micron, C1 represents the value of described first impurity concentration; In the described second N-type district from impurity concentration be the position of 10 times described first impurity concentration to impurity concentration be the impurity concentration in the described second N-type district 50 times the position of described first impurity concentration with the maximum of advancing the speed of position less than the 300C1/ micron.
Further improve and be, the maximum of the impurity concentration in described N-type district is that 2 orders of magnitude of impurity concentration of described first p type island region are following and be 2 of the impurity concentration of described second p type island region below the order of magnitude.
Further improve and be, between each described peak in the described second N-type district or at the described peak of close described second p type island region in the described second N-type district between described second p type island region, the impurity concentration in the described second N-type district remains the impurity concentration at each described peak place or is reduced to described first impurity concentration gradually from the impurity concentration of each described peak.
For solving the problems of the technologies described above, the manufacture method of first kind of semiconductor device provided by the invention adopts following steps to form described N-type district:
Step 2, carry out the first N-type foreign ion from described silicon chip back and inject; The described first N-type foreign ion injection zone forms the described second N-type district, and the described second N-type district forms the described first N-type district to the zone between described first p type island region; The described first N-type district and the described second N-type district form described N-type district.
For solving the problems of the technologies described above, the manufacture method of second kind of semiconductor device provided by the invention adopts following steps to form described N-type district:
Step 2, carry out attenuate from the back side to described silicon chip.
For solving the problems of the technologies described above, the manufacture method of the third semiconductor device provided by the invention adopts following steps to form described N-type district:
Step 2, carry out attenuate from the back side to described silicon chip.
For solving the problems of the technologies described above, the manufacture method of the 4th kind of semiconductor device provided by the invention adopts following steps to form described N-type district:
Step 2, carry out the N-type outer layer growth from described silicon chip back and form the described second N-type district, the described second N-type district forms the described first N-type district to the zone between described first p type island region; The described first N-type district and the described second N-type district form described N-type district.
For solving the problems of the technologies described above, the manufacture method of the 5th kind of semiconductor device provided by the invention adopts following steps to form described N-type district:
Step 2, carry out the 3rd N-type foreign ion from described silicon chip back and inject; Described the 3rd N-type foreign ion injection zone forms the first in the described second N-type district.
Device of the present invention is the gradual district that slowly increases by increase by a doping content in the drift region, gradual district is positioned at the doping content in silicon chip back one side and gradual district greater than the doping content of homogeneity range, highly doped gradual district can guarantee that device obtains lower conducting resistance, makes the size of conducting resistance consistent with the conducting resistance of existing blocking-up type semiconductor device.Simultaneously, advancing the speed of the doping content in gradual district obtained good control, be a kind of gradual structure, device of the present invention like this can be eliminated the bigger defective of internal electric field in the field barrier layer that exists in existing the blocking-up type semiconductor device, thereby the electric current decrease speed of device when turn-offing is effectively controlled, making this cut-off current no longer is a kind of electric current of rapid decline, but a kind of soft electric current of slow decline, so just can improve the reliability of device.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the structural representation of existing blocking-up type IGBT;
Fig. 2 is the distribution schematic diagram from the P trap to the impurity concentration P type emitter of existing blocking-up type IGBT;
Fig. 3 is operated in reverse blocking state Electric Field Distribution of following time schematic diagram corresponding to the device among Fig. 2;
Fig. 4 is the structural representation of embodiment of the invention semiconductor device;
Fig. 5 A is the distribution schematic diagram of impurity concentration of the drift region of the device that forms of the manufacture method of embodiment of the invention semiconductor device;
Fig. 5 B is the distribution schematic diagram of impurity concentration of the drift region of the device that forms of the manufacture method of the embodiment of the invention two semiconductor device;
Fig. 5 C is the distribution schematic diagram of impurity concentration of the drift region of the device that forms of the manufacture method of the embodiment of the invention three semiconductor device;
Fig. 5 D is the distribution schematic diagram of impurity concentration of the drift region of the device that forms of the manufacture method of the embodiment of the invention four semiconductor device;
Fig. 6 is the structural representation of the embodiment of the invention five semiconductor device.
Embodiment
As shown in Figure 4, be the structural representation of embodiment of the invention semiconductor device; The invention process semiconductor device is to be that 3300V and drift region are that the IGBT device of N-type is that example describes with the reverse breakdown voltage, and the doping content of the N-type impurity of described silicon chip 1 is the first impurity concentration C1=1E13CM
-3, resistivity is 180 ohm. centimetre.Embodiment of the invention semiconductor device comprises:
One is formed at first p type island region 7 in the front of silicon chip.The positive technology of embodiment of the invention semiconductor device also comprises: the grid oxygen 5 and the polysilicon electrode 6 that are positioned at described silicon chip 1 upper end; Coat the inter-level dielectric film 9 of described polysilicon electrode 6; Be formed at the N+ source 8 in described first p type island region 7; Contact hole 10 is used for drawing described N+ source 8; P+ contacts implanted layer 11, is formed at described contact hole 10 and enters into described first p type island region 7, is used for described first p type island region 7 is drawn; Front metal 12 is for the source electrode of drawing device.Described first p type island region 7 is covered described first p type island region 7 in positions by described polysilicon electrode 6 and forms channel regions between section A and cross section B and as the tagma of IGBT device; Between section A and cross section B and and described first p type island region 7 laterally the part that does not form described first p type island region 7 of contiguous described silicon chip 1 form the part of drift region of the drain terminal of device.
One is formed at second p type island region 4 at the back side of described silicon chip 1, is formed with backplate 14 at the back side of described second p type island region 4.In embodiment of the invention semiconductor device, described second p type island region 4 is as the P type emitter of device.
One N-type district, this N-type district are positioned between described first p type island region 7 and described second p type island region 4, and described N-type district is the drift region of described semiconductor device.Described N-type district comprises the first N-type district 1a and the second N-type district 1b, and the impurity concentration of the described first N-type district 1a is even, and the impurity concentration of the described second N-type district 1b is a gradual structure; The described second N-type district 1b is between the described first N-type district 1a and described second p type island region 4, the impurity concentration of the described first N-type district 1a is first impurity concentration, and the impurity concentration of the described second N-type district 1b increases on the basis of described first impurity concentration and the impurity concentration of the described second N-type district 1b comprises a peak value at least.In the zone that the impurity concentration of each described peak region of the described second N-type district 1b of the described first N-type district 1a on the direction of described second p type island region 4 increases, among the described second N-type district 1b from impurity concentration be the position of described first impurity concentration to impurity concentration be the impurity concentration of the described second N- type district 1b 10 times the position of described first impurity concentration with the maximum of advancing the speed of position less than the 10C1/ micron, C1 represents the value of described first impurity concentration; Among the described second N-type district 1b from impurity concentration be the position of 10 times described first impurity concentration to impurity concentration be the impurity concentration of the described second N-type district 1b 50 times the position of described first impurity concentration with the maximum of advancing the speed of position less than the 300C1/ micron.The maximum of the impurity concentration in described N-type district is that 2 orders of magnitude of impurity concentration of described first p type island region 7 are following and be 2 of the impurity concentration of described second p type island region 4 below the order of magnitude.Between each described peak of the described second N-type district 1b or at the described peak of close described second p type island region 4 of the described second N-type district 1b between described second p type island region 4, the impurity concentration of the described second N-type district 1b remains the impurity concentration at each described peak place or is reduced to described first impurity concentration gradually from the impurity concentration of each described peak.
The manufacture method device architecture of embodiment of the invention semiconductor device please refer to Fig. 4, and the manufacture method of embodiment of the invention semiconductor device adopts following steps to form described N-type district:
The formation technology of first p type island region 7 belongs to positive technology, and described first p type island region 7 forms after attenuate at formation or described first p type island region 7 before the attenuate.Positive technology in the embodiment of the invention one all is placed into after described silicon chip 1 attenuate, and is to be placed into after first heat treatment of subsequent step three.
Reduction process comprises step: in the front of described silicon chip 1 be the oxide-film of section A growth 5000 dusts～20000 dusts, and the front protecting of described silicon chip 1 is good; Carry out attenuate from the back side to described silicon chip 1; Polishing is carried out at the back side of described silicon chip 1, defective or the cut at the back side are removed; Carry out the pre-treatment of the back process of described silicon chip 1, as utilize HF that DHF namely dilutes etc. with as described in the natural oxide film at silicon chip 1 back side except removing.
Step 2, carry out the first N-type foreign ion from the back side of described silicon chip 1 and inject; The described first N-type foreign ion injection zone forms the described second N-type district 1b, and the described second N-type district 1b forms the described first N-type district 1a to the zone between described first p type island region 7; The described first N-type district 1a and the described second N-type district 1b form described N-type district.The first N-type foreign ion injects and adopts the repeatedly injection of once injecting or adopt different-energy, and injecting energy range is 5KEV～5M EV, and implantation dosage is E11CM
-2～E13CM
-2
Shown in Fig. 5 A, the impurity concentration of the described second N-type district 1b comprises a peak value, and the peak value of the described second N-type district 1b is between described second p type island region 4, and the impurity concentration of the described second N-type district 1b remains the impurity concentration at described peak place.In the zone that the impurity concentration of the described peak region of the described second N-type district 1b of the described first N-type district 1a on the direction of described second p type island region 4 increases, being changed to of the impurity concentration of the described second N-type district 1b: among the described second N-type district 1b from impurity concentration be the position b0 of described first impurity concentration to impurity concentration be 10 times the position b1 of described first impurity concentration alternate position spike greater than 5 microns.Among the described second N-type district 1b is that the position b 1 of 10 times described first impurity concentration is that alternate position spike 50 times the position of described first impurity concentration is greater than 5 microns to impurity concentration from impurity concentration.
After step 4, the described first thermal anneal process technology are finished, then form the positive technology of embodiment of the invention semiconductor device, because embodiment of the invention semiconductor device is an IGBT device, so its positive technology can utilize the technological process of having known that is similar to VDMOS to finish, as shown in Figure 4, comprise: be positioned at the grid oxygen 5 of described silicon chip 1 upper end and the formation of polysilicon electrode 6, P trap 7 is the formation in described first p type island region 7, N+ source 8, coat the inter-level dielectric film 9 of described polysilicon electrode 6, the formation of contact hole 10, the formation of P+ contact implanted layer 11; The front metal deposit adopts chemical wet etching technology that described front metal is carried out graphically, forms the metal electrode (not shown) of source metal electrode 12 and described polysilicon electrode 6.
The manufacture method device architecture of the embodiment of the invention two semiconductor device please refer to Fig. 4, and the manufacture method of the embodiment of the invention two semiconductor device adopts following steps to form described N-type district:
Step 2, the front protecting that will form the described silicon chip 1 after the positive technology are good, are thinned to 500 microns～550 microns of the thickness that need from the back side to described silicon chip 1.
The manufacture method device architecture of the embodiment of the invention three semiconductor device please refer to Fig. 4, the difference of the manufacture method of the embodiment of the invention three semiconductor device and the manufacture method of embodiment of the invention semiconductor device is, the described first N-type foreign ion of the step 2 in the manufacture method of embodiment of the invention semiconductor device injects the technology that described first thermal annealing that adds step 3 forms the described second N-type district 1b and replaces with in the embodiment of the invention three methods: carry out the N-type outer layer growth from the back side of described silicon chip 1 and form the described second N-type district 1b, the described second N-type district 1b forms the described first N-type district 1a to the zone between described first p type island region 7; The described first N-type district 1a and the described second N-type district 1b form described N-type district.Doping content during the N-type outer layer growth also is gradual, and being changed to of impurity concentration that forms the described second N-type district 1b at last please refer to shown in Fig. 5 C.Shown in Fig. 5 C, the impurity concentration of the described second N-type district 1b increases from first impurity concentration is linear, be increased to and described second p type island region 4 contacted positions, the peak of the impurity concentration of the described second N-type district 1b is positioned at and described second p type island region 4 contacted positions always.
The manufacture method device architecture of the embodiment of the invention four semiconductor device please refer to Fig. 4, the difference of the manufacture method of the embodiment of the invention four semiconductor device and the manufacture method of embodiment of the invention semiconductor device is, the step 1 that step 1 to the step 4 of embodiment of the invention four directions method adopts the embodiment of the invention one method is to step 4, and step 2 and step 3 form the first of the described second N-type district 1b; After the positive technology of step 4, embodiment of the invention four directions method also comprises the steps:
More than each embodiment be the IGBT device be that example describes, by changing positive technology, the inventive method is applicable to other devices that utilize the P/N thin layer to bear reverse voltage too, comprises at least among the devices such as IGBT, diode, MOSFET.As shown in Figure 6, be the structural representation of the embodiment of the invention five semiconductor device, just adopted the gradual drift region identical with Fig. 4, the i.e. first N-type district 1a and second a N-type district 1b in the silicon substrate 1 of the embodiment of the invention five semiconductor device.Described silicon substrate 1 back side with the described second N-type district 1b be a N+ district 15, draw by backplate 14 in the N+ district.Described silicon substrate 1 front with the described first N-type district 1a be first p type island region 7.
More than by specific embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (8)
1. semiconductor device is characterized in that semiconductor device comprises:
One is formed at first p type island region in the front of silicon chip;
One is formed at second p type island region of described silicon chip back, is formed with backplate at the back side of described second p type island region;
One N-type district, this N-type district are positioned between described first p type island region and described second p type island region, and described N-type district is the drift region of described semiconductor device; Described N-type district comprises the first N-type district and the second N-type district, and the impurity concentration in the described first N-type district is even, and the impurity concentration in the described second N-type district is a gradual structure; The described second N-type district is positioned between the described first N-type district and described second p type island region, the impurity concentration in the described first N-type district is first impurity concentration, and the impurity concentration in the described second N-type district increases on the basis of described first impurity concentration and the impurity concentration in the described second N-type district comprises a peak value at least; In the zone that the impurity concentration of each described peak region in the described second N-type district of the described first N-type district on the direction of described second p type island region increases, the position that from impurity concentration is described first impurity concentration to impurity concentration be the impurity concentration in the described second N-type district 10 times the position of described first impurity concentration with the maximum of advancing the speed of position less than the 10C1/ micron, C1 represents the value of described first impurity concentration; In the described second N-type district from impurity concentration be the position of 10 times described first impurity concentration to impurity concentration be the impurity concentration in the described second N-type district 50 times the position of described first impurity concentration with the maximum of advancing the speed of position less than the 300C1/ micron.
2. semiconductor device as claimed in claim 1 is characterized in that: the maximum of the impurity concentration in described N-type district is that 2 orders of magnitude of impurity concentration of described first p type island region are following and be 2 of the impurity concentration of described second p type island region below the order of magnitude.
3. semiconductor device as claimed in claim 1, it is characterized in that: between each described peak in the described second N-type district or at the described peak of close described second p type island region in the described second N-type district between described second p type island region, the impurity concentration in the described second N-type district remains the impurity concentration at each described peak place or is reduced to described first impurity concentration gradually from the impurity concentration of each described peak.
4. the manufacture method of a semiconductor device as claimed in claim 1 is characterized in that, adopts following steps to form described N-type district:
Step 1, an impurity concentration is provided is the silicon chip that the N-type of first impurity concentration is mixed, and before the front metal deposit is finished in the front of described silicon chip, carries out attenuate from the back side to described silicon chip; The formation technology of described first p type island region belongs to positive technology, and described first p type island region forms after attenuate at formation or described first p type island region before the attenuate;
Step 2, carry out the first N-type foreign ion from described silicon chip back and inject; The described first N-type foreign ion injection zone forms the described second N-type district, and the described second N-type district forms the described first N-type district to the zone between described first p type island region; The described first N-type district and the described second N-type district form described N-type district;
Step 3, described silicon chip is carried out first thermal anneal process, the temperature of described first thermal annealing is 800 ℃～1250 ℃, and the time is 60 minutes～1200 minutes.
5. the manufacture method of a semiconductor device as claimed in claim 1 is characterized in that, adopts following steps to form described N-type district:
Step 1, an impurity concentration is provided is the silicon chip that the N-type of first impurity concentration is mixed, finish the positive technology of described semiconductor device in the front of described silicon chip, described positive technology comprises technology, front metal deposit and the graphical technology that forms described first p type island region;
Step 2, carry out attenuate from the back side to described silicon chip;
Step 3, carry out the second N-type foreign ion from described silicon chip back and inject; The described second N-type foreign ion injects the injection that comprises repeatedly different-energy; The described second N-type foreign ion injection zone forms the described second N-type district, and the described second N-type district forms the described first N-type district to the zone between described first p type island region; The described first N-type district and the described second N-type district form described N-type district;
Step 4, from described silicon chip back described silicon chip is carried out laser annealing and handle, the temperature in the processed zone of described silicon chip is higher than 800 ℃ during laser annealing.
6. the manufacture method of a semiconductor device as claimed in claim 1 is characterized in that, adopts following steps to form described N-type district:
Step 1, an impurity concentration is provided is the silicon chip that the N-type of first impurity concentration is mixed, finish the positive technology of described semiconductor device in the front of described silicon chip, described positive technology comprises technology, front metal deposit and the graphical technology that forms described first p type island region;
Step 2, carry out attenuate from the back side to described silicon chip;
Step 3, carry out the first hydrogen foreign ion from described silicon chip back and inject; The described first hydrogen foreign ion injects the injection that comprises repeatedly different-energy; The described first hydrogen foreign ion injection zone forms the described second N-type district, and the described second N-type district forms the described first N-type district to the zone between described first p type island region; The described first N-type district and the described second N-type district form described N-type district;
Step 4, described silicon chip is carried out second thermal anneal process, the temperature of described second thermal annealing is 200 ℃～420 ℃, and the time is 20 minutes～200 minutes.
7. the manufacture method of a semiconductor device as claimed in claim 1 is characterized in that, adopts following steps to form described N-type district:
Step 1, an impurity concentration is provided is the silicon chip that the N-type of first impurity concentration is mixed, and before the front metal deposit is finished in the front of described silicon chip, carries out attenuate from the back side to described silicon chip; The formation technology of described first p type island region belongs to positive technology, and described first p type island region forms after attenuate at formation or described first p type island region before the attenuate;
Step 2, carry out the N-type outer layer growth from described silicon chip back and form the described second N-type district, the described second N-type district forms the described first N-type district to the zone between described first p type island region; The described first N-type district and the described second N-type district form described N-type district.
8. the manufacture method of a semiconductor device as claimed in claim 1 is characterized in that, adopts following steps to form described N-type district:
Step 1, an impurity concentration is provided is the silicon chip that the N-type of first impurity concentration is mixed, and before the front metal deposit is finished in the front of described silicon chip, carries out attenuate from the back side to described silicon chip; The formation technology of described first p type island region belongs to positive technology, and described first p type island region forms after attenuate at formation or described first p type island region before the attenuate;
Step 2, carry out the 3rd N-type foreign ion from described silicon chip back and inject; Described the 3rd N-type foreign ion injection zone forms the first in the described second N-type district;
Step 3, described silicon chip is carried out the 3rd thermal anneal process, the temperature of described the 3rd thermal annealing is higher than 700 ℃, and the time was greater than 5 hours;
Step 4, finish the positive technology of described semiconductor device in the front of described silicon chip, described positive technology comprises technology, front metal deposit and the graphical technology that forms described first p type island region;
Step 5, carry out the second hydrogen foreign ion from described silicon chip back and inject; The described second hydrogen foreign ion injects the injection that comprises repeatedly different-energy; The described second hydrogen foreign ion injection zone forms the second portion in the described second N-type district, forms the described second N-type district by described first and described second portion; Distance between the peak of the impurity concentration of described second portion and the described silicon chip back surface is greater than the position of the minimum of the impurity concentration of described first and the distance between the described silicon chip back surface; The described second N-type district forms the described first N-type district to the zone between described first p type island region; The described first N-type district and the described second N-type district form described N-type district;
Step 5, described silicon chip is carried out the 4th thermal anneal process, the temperature of described the 4th thermal annealing is 200 ℃～420 ℃, and the time is 20 minutes～200 minutes.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN104637994A (en) * | 2013-11-13 | 2015-05-20 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and manufacturing method |
| CN104637994B (en) * | 2013-11-13 | 2018-02-06 | 上海华虹宏力半导体制造有限公司 | Semiconductor devices and manufacture method |
| CN109860283A (en) * | 2019-01-16 | 2019-06-07 | 全球能源互联网研究院有限公司 | A kind of production method and device at the back side IGBT, IGBT |
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