CN106298969A - The processing method of super barrier diode and super barrier diode - Google Patents
The processing method of super barrier diode and super barrier diode Download PDFInfo
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- 230000004888 barrier function Effects 0.000 title claims abstract description 139
- 238000003672 processing method Methods 0.000 title claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 94
- 229920005591 polysilicon Polymers 0.000 claims abstract description 90
- 238000005530 etching Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000000873 masking effect Effects 0.000 claims abstract description 7
- 238000000407 epitaxy Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 42
- 238000005516 engineering process Methods 0.000 claims description 31
- 238000005468 ion implantation Methods 0.000 claims description 23
- 238000002513 implantation Methods 0.000 claims description 18
- 230000008569 process Effects 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 4
- 238000005260 corrosion Methods 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 2
- 230000003628 erosive effect Effects 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010891 electric arc Methods 0.000 description 1
- 239000000686 essence Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8618—Diodes with bulk potential barrier, e.g. Camel diodes, Planar Doped Barrier diodes, Graded bandgap diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
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Abstract
The invention provides processing method and the super barrier diode of a kind of super barrier diode, described processing method includes: sequentially form N-type epitaxy layer, field oxide, polysilicon layer and insulating barrier in N-type substrate；After forming Patterned masking layer on the insulating layer, insulating barrier is carried out isotropic etching, to form insulating barrier mask structure；With formed insulating barrier mask structure as mask, successively polysilicon layer and field oxide are carried out anisotropic etching, to expose the appointment region of the epitaxial layer for making body district；PXing Ti district is formed in the appointment region of epitaxial layer；Forming P-type region in epitaxial layer below the edge through the field layer of over etching, polysilicon layer corresponding above P-type region forms p-type polysilicon structure；In the PXing Ti district forming p-type polysilicon structure, form the N+ type region with P-type region disconnecting and electrode.By technical scheme, improve the reliability of super barrier diode.
Description
Technical field
The present invention relates to semiconductor chip manufacturing technology field, in particular to a kind of super barrier two
The processing method of pole pipe and a kind of super barrier diode.
Background technology
At present, in the related, power diode is the critical component of Circuits System, generally applicable
In filling at the products for civilian use such as high-frequency inverter, digital product, electromotor, television set and satellite reception
Put, various advanced weaponry control systems and the military scenario of instrumentation devices such as guided missile and aircraft.Merit
Rate diode is expanded towards two important directions: (1), can to several ten million or even up to ten thousand amperes of development
It is applied to the occasions such as high-temperature electric arc wind-tunnel, resistance welder；(2) reverse recovery time is shorter and shorter,
Present and develop to ultrafast, ultra-soft, super durable direction, make self to be applied not only to rectification occasion, various
On-off circuit has not same-action.
Therefore, the processing method how designing a kind of super barrier diode so that the super barrier two of preparation
The conduction voltage drop of pole pipe is low and leakage current is little becomes technical problem urgently to be resolved hurrily.
Summary of the invention
The present invention is based at least one above-mentioned technical problem, it is proposed that a kind of super barrier diode
The scheme of processing method so that the super barrier N of preparation is less than two poles of traditional structure
Pipe, level of drain current traditional devices to be far below, and manufacturing process can be simplified, reduction is manufactured into
This.
Realize above-mentioned purpose, embodiment according to the first aspect of the invention, it is provided that a kind of super barrier
The processing method of diode, including: in N-type substrate, sequentially form N-type epitaxy layer, field oxidation
Layer, polysilicon layer and insulating barrier；Described insulating barrier is formed after Patterned masking layer, to described absolutely
Edge layer carries out isotropic etching, to form insulating barrier mask structure；Cover with the described insulating barrier formed
Membrane structure is mask, successively described polysilicon layer and described field oxide is carried out anisotropic etching,
To expose the appointment region of the described epitaxial layer for making body district；Appointment district at described epitaxial layer
Territory forms PXing Ti district；Shape in described epitaxial layer below the edge through the described field layer of over etching
Becoming P-type region, meanwhile, described polysilicon layer corresponding above described P-type region forms P
Type polysilicon structure；In the described PXing Ti district forming described p-type polysilicon structure, formed and institute
State N+ type region and the electrode of P-type region disconnecting, to complete the making of described super barrier diode.
In this technical scheme, by after forming insulating barrier mask structure, form P-type region and P
Type polysilicon structure, and by forming N+ type region and electrode, it is to avoid use the side of being directly injected into
P-type region and N+ type region that formula causes get too close to and cause the problem that leakage current is bigger, namely
Effectively control P-type region and the formation region in N+ type region and ion concentration so that surpassing of preparation
Barrier diode has been provided simultaneously with the characteristic of low conducting voltage and Low dark curient, improves super barrier diode
Reliability.
In technique scheme, it is preferable that after forming Patterned masking layer on described insulating barrier,
Described insulating barrier is carried out isotropic etching, to form insulating barrier mask structure, including in detail below
Step: after forming graphical described mask layer on described insulating barrier, described insulating barrier is used
Wet etching processes, and/or uses isotropic etch gas that described insulating barrier is carried out dry etching
Process, to form described insulating barrier mask structure.
In this technical scheme, by using wet corrosion technique and/or isotropism dry etching work
Insulating barrier is performed etching by skill so that insulating barrier forms groove structure, and then to many below insulating barrier
When crystal silicon layer and field oxide perform etching, still using photoresist as mask, the groove structure of insulating barrier
The epitaxial layer of lower section corresponding to the P-type region of super barrier diode to be prepared, namely with polysilicon layer and
Field oxide, as the mask in preparation P-type region, may further ensure that the reliable of P-type region
Property.
In technique scheme, it is preferable that form p-type body in the appointment region of described epitaxial layer
District, including step in detail below: use the first ion implantation technology in the appointment region of described epitaxial layer
Form described PXing Ti district.
In this technical scheme, by using the first ion implantation technology in the appointment region shape of epitaxial layer
ChengPXing Ti district, defines the channel region of super barrier diode.
In technique scheme, it is preferable that below the edge through the described field layer of over etching
Described epitaxial layer forms P-type region, meanwhile, above described P-type region described in correspondence
Polysilicon layer forms p-type polysilicon structure, including step in detail below: use the second ion implanting work
The described P-type region formed in the skill described epitaxial layer below the edge through the described field layer of over etching
Territory, meanwhile, described polysilicon layer corresponding above described P-type region forms p-type polysilicon knot
Structure.
In this technical scheme, form p-type polysilicon structure and P-type region by the second ion implanting
Territory, defines the anode ion region of super barrier diode, thus ensure that the reliability of device is with steady
Qualitative, with field oxide for mask formed P-type region, efficiently control P-type region junction depth and
Ion concentration, it is to avoid P-type region and N+ type region get too close to and cause excessive the asking of leakage current
Topic, ensure that the characteristic of the low conducting voltage of super barrier diode simultaneously.
In technique scheme, it is preferable that the Implantation Energy of described first ion implantation technology is more than
The Implantation Energy of described second ion implantation technology.
In this technical scheme, by set the Implantation Energy of the first ion implantation technology more than second from
The Implantation Energy of sub-injection technology, defines reliability GaoPXing Ti district and P-type region, Ye Jichao
The channel region of barrier diode and anode ion district.
In technique scheme, it is preferable that the implantation dosage of described first ion implantation technology is more than
The implantation dosage of described second ion implantation technology.
In this technical scheme, by set the implantation dosage of the first ion implantation technology more than second from
The implantation dosage of sub-injection technology, ensure that the PXing Ti district of formation and P-type region further can
High by property, it is ensured that Low dark curient, low on state characteristic, thus improve the reliable of super barrier diode
Property.
In technique scheme, it is preferable that in the described p-type forming described p-type polysilicon structure
In body district, form the N+ type region with described P-type region disconnecting and electrode, including walking in detail below
Rapid: after forming described p-type polysilicon structure, described N-type substrate is formed N+ type polysilicon
Layer.
In this technical scheme, by forming N+ type polysilicon layer, with by N+ type polysilicon layer shape
N+ type region in ChengPXing Ti district, namely the cathode ion district of super barrier diode, control effectively
Make junction depth and the ion concentration in cathode ion district, and then further ensure Low dark curient, low conducting spy
Property, thus improve the reliability of super barrier diode.
In technique scheme, it is preferable that in the described p-type forming described p-type polysilicon structure
In body district, form the N+ type region with described P-type region disconnecting and electrode, also include in detail below
Step: described N+ type polysilicon layer is carried out anisotropic etching, to remove described insulating barrier mask
The N+ type polysilicon layer in superstructure and described PXing Ti district, with described polysilicon while of to be formed
The N+ type polysilicon side wall of the EDGE CONTACT in floor, described field oxide and described PXing Ti district；To shape
Become described N+ type polysilicon side wall to make annealing treatment, with described PXing Ti district edge formed with
The described N+ type region of described P-type region disconnecting.
In this technical scheme, by forming N+ type polysilicon side wall, and it is carried out annealing treatment
Reason so that the ion in N+ type polysilicon side wall is spread in PXing Ti district, to form N+ type district
Territory, namely the cathode ion district of super barrier diode, and efficiently controlled the junction depth in N+ type region
And ion concentration, thus avoid N+ type region and P-type region and get too close to and cause electric leakage to be flow through
High problem, is effectively improved the reliability of super barrier diode.
In technique scheme, it is preferable that in the described p-type forming described p-type polysilicon structure
In body district, form the N+ type region with described P-type region disconnecting and electrode, also include in detail below
Step: after forming described N+ type region, uses metal sputtering processes, electroplating technology and evaporation work
A kind of technique in skill or the combination in any of kinds of processes, with institute in described N-type substrate while of formation
State insulating barrier mask, described N-type polycrystalline silicon floor, the metal level of PXing Ti district contact, described metal level
It is the electrode of described super barrier diode.
In this technical scheme, by forming the electrode of super barrier diode, it is ensured that the low drain of preparation
The super barrier diode of conducting voltage electric, low can be integrated in application-level circuitry, namely by bonding
Technique, can realize the concatenation between electrode and application-level circuitry, and process is simple.
According to the second aspect of the invention, it is also proposed that a kind of super barrier diode, use such as above-mentioned
The processing method of the super barrier diode described in one technical scheme is fabricated by.
By above technical scheme so that the conduction voltage drop of the super barrier diode made is less than conventional junction
The super barrier diode of structure, level of drain current to be far below tradition super barrier diode, and can letter
Change manufacturing process simple, reduce the manufacturing cost of super barrier diode.
Accompanying drawing explanation
Fig. 1 shows the signal stream of the processing method of super barrier diode according to an embodiment of the invention
Cheng Tu；
Fig. 2 to Figure 10 shows the course of processing of super barrier diode according to an embodiment of the invention
Generalized section.
Detailed description of the invention
In order to be more clearly understood that the above-mentioned purpose of the present invention, feature and advantage, below in conjunction with attached
The present invention is further described in detail by figure and detailed description of the invention.It should be noted that not
In the case of conflict, the feature in embodiments herein and embodiment can be mutually combined.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but,
The present invention can implement to use other to be different from other modes described here, therefore, and the present invention
Protection domain do not limited by following public specific embodiment.
Fig. 1 shows the signal stream of the processing method of super barrier diode according to an embodiment of the invention
Cheng Tu.
As it is shown in figure 1, the processing method of super barrier diode according to an embodiment of the invention, bag
Include: step S1, N-type substrate sequentially forms N-type epitaxy layer, field oxide, polysilicon layer
And insulating barrier；Step S2, after forming Patterned masking layer on described insulating barrier, to described insulation
Layer carries out isotropic etching, to form insulating barrier mask structure；Step S3, described in being formed
Insulating barrier mask structure is mask, carries out described polysilicon layer and described field oxide each to different successively
Property etching, to expose the appointment region of the described epitaxial layer for making body district；Step S4,
The appointment region of described epitaxial layer forms PXing Ti district；Step S5, in the described field through over etching
Described epitaxial layer below the edge of layer forms P-type region, meanwhile, in described P-type region
The described polysilicon layer formation p-type polysilicon structure that top is corresponding；Step S6, is forming described P
In the described PXing Ti district of type polysilicon structure, form the N+ type region with described P-type region disconnecting
And electrode, to complete the making of described super barrier diode.
In this technical scheme, by after forming insulating barrier mask structure, form P-type region and P
Type polysilicon structure, and by forming N+ type region and electrode, it is to avoid use the side of being directly injected into
P-type region and N+ type region that formula causes get too close to and cause the problem that leakage current is bigger, namely
Effectively control P-type region and the formation region in N+ type region and ion concentration so that surpassing of preparation
Barrier diode has been provided simultaneously with the characteristic of low conducting voltage and Low dark curient, improves super barrier diode
Reliability.
In technique scheme, it is preferable that after forming Patterned masking layer on described insulating barrier,
Described insulating barrier is carried out isotropic etching, to form insulating barrier mask structure, including in detail below
Step: step S21, after forming graphical described mask layer on described insulating barrier, to described insulation
Layer carries out using wet etching to process, and/or uses isotropic etch gas to enter described insulating barrier
Row dry etching processes, to form described insulating barrier mask structure.
In this technical scheme, by using wet corrosion technique and/or isotropism dry etching work
Insulating barrier is performed etching by skill so that insulating barrier forms groove structure, and then to many below insulating barrier
When crystal silicon layer and field oxide perform etching, still using photoresist as mask, the groove structure of insulating barrier
The epitaxial layer of lower section corresponding to the P-type region of super barrier diode to be prepared, namely with polysilicon layer and
Field oxide, as the mask in preparation P-type region, may further ensure that the reliable of P-type region
Property.
In technique scheme, it is preferable that form p-type body in the appointment region of described epitaxial layer
District, including step in detail below: step S41, uses the first ion implantation technology at described epitaxial layer
Appointment region form described PXing Ti district.
In this technical scheme, by using the first ion implantation technology in the appointment region shape of epitaxial layer
ChengPXing Ti district, defines the channel region of super barrier diode.
In technique scheme, it is preferable that below the edge through the described field layer of over etching
Described epitaxial layer forms P-type region, meanwhile, above described P-type region described in correspondence
Polysilicon layer forms p-type polysilicon structure, including step in detail below: step S51, uses second
The ion implantation technology described epitaxial layer below the edge through the described field layer of over etching is formed
Described P-type region, meanwhile, described polysilicon layer corresponding above described P-type region forms P
Type polysilicon structure.
In this technical scheme, form p-type polysilicon structure and P-type region by the second ion implanting
Territory, defines the anode ion region of super barrier diode, thus ensure that the reliability of device is with steady
Qualitative, with field oxide for mask formed P-type region, efficiently control P-type region junction depth and
Ion concentration, it is to avoid P-type region and N+ type region get too close to and cause excessive the asking of leakage current
Topic, ensure that the characteristic of the low conducting voltage of super barrier diode simultaneously.
In technique scheme, it is preferable that the Implantation Energy of described first ion implantation technology is more than
The Implantation Energy of described second ion implantation technology.
In this technical scheme, by set the Implantation Energy of the first ion implantation technology more than second from
The Implantation Energy of sub-injection technology, defines reliability GaoPXing Ti district and P-type region, Ye Jichao
The channel region of barrier diode and anode ion district.
In technique scheme, it is preferable that the implantation dosage of described first ion implantation technology is more than
The implantation dosage of described second ion implantation technology.
In this technical scheme, by set the implantation dosage of the first ion implantation technology more than second from
The implantation dosage of sub-injection technology, ensure that the PXing Ti district of formation and P-type region further can
High by property, it is ensured that Low dark curient, low on state characteristic, thus improve the reliable of super barrier diode
Property.
In technique scheme, it is preferable that in the described p-type forming described p-type polysilicon structure
In body district, form the N+ type region with described P-type region disconnecting and electrode, including walking in detail below
Rapid: after forming described p-type polysilicon structure, described N-type substrate is formed N+ type polysilicon
Layer.
In this technical scheme, by forming N+ type polysilicon layer, with by N+ type polysilicon layer shape
N+ type region in ChengPXing Ti district, namely the cathode ion district of super barrier diode, control effectively
Make junction depth and the ion concentration in cathode ion district, and then further ensure Low dark curient, low conducting spy
Property, thus improve the reliability of super barrier diode.
In technique scheme, it is preferable that in the described p-type forming described p-type polysilicon structure
In body district, form the N+ type region with described P-type region disconnecting and electrode, also include in detail below
Step: step S61, carries out anisotropic etching to described N+ type polysilicon layer, described to remove
The N+ type polysilicon layer in above insulating barrier mask structure and described PXing Ti district, with institute while of to be formed
State the N+ type polysilicon side of the EDGE CONTACT in polysilicon layer, described field oxide and described PXing Ti district
Wall；Step S62, makes annealing treatment forming described N+ type polysilicon side wall, with at described P
The edge in Xing Ti district forms the described N+ type region with described P-type region disconnecting.
In this technical scheme, by forming N+ type polysilicon side wall, and it is carried out annealing treatment
Reason so that the ion in N+ type polysilicon side wall is spread in PXing Ti district, to form N+ type district
Territory, namely the cathode ion district of super barrier diode, and efficiently controlled the junction depth in N+ type region
And ion concentration, thus avoid N+ type region and P-type region and get too close to and cause electric leakage to be flow through
High problem, is effectively improved the reliability of super barrier diode.
In technique scheme, it is preferable that in the described p-type forming described p-type polysilicon structure
In body district, form the N+ type region with described P-type region disconnecting and electrode, also include in detail below
Step: step S63, after forming described N+ type region, uses metal sputtering processes, galvanizer
A kind of technique in skill and evaporation process or the combination in any of kinds of processes, shape in described N-type substrate
Become the metal level simultaneously contacted with described insulating barrier mask, described N-type polycrystalline silicon floor, PXing Ti district,
Described metal level is the electrode of described super barrier diode.
In this technical scheme, by forming the electrode of super barrier diode, it is ensured that the low drain of preparation
The super barrier diode of conducting voltage electric, low can be integrated in application-level circuitry, namely by bonding
Technique, can realize the concatenation between electrode and application-level circuitry, and process is simple.
Below in conjunction with the Fig. 2 to Figure 10 processing to super barrier diode according to an embodiment of the invention
Process is specifically described, and wherein, reference and structure name in Fig. 2 to Figure 10 are referred to as:
101N type substrate, 102N type epitaxial layer, 103 field oxides, 104 polysilicon layers, 105 insulation
Layer, 106P Xing Ti district, P-type region 107,108P type polysilicon, 109N+ type polysilicon layer,
110N+ type polysilicon side wall, 111N+ type region, 112 electrodes.
As in figure 2 it is shown, after forming N-type epitaxy layer 102 in N-type substrate 101, successively at N
Field oxide 103, polysilicon layer 104 and insulating barrier 105 is formed on type epitaxial layer.
As it is shown on figure 3, form the graphical photoresist (knot shown in PR in figure on insulating barrier 105
Structure) after, insulating barrier 105 is carried out isotropic etching, wherein, respectively uses in etching technics
Polysilicon is not corroded by liquid or gas, according to default etch period or triggering etching point
Control the etching process of insulating barrier, to ensure the accuracy of the isotropic etching of insulating barrier.
As shown in Figure 4, continue polysilicon layer 104 and field oxide 103 carried out isotropism quarter
Erosion, after completing this step etching, the edge of insulating barrier 105 defines groove structure, and above-mentioned groove is tied
Structure is for retaining the marginal area of polysilicon layer 104.
As it is shown in figure 5, graphically changing photoresist (structure shown in PR in figure) is mask, to N
Type epitaxial layer 102 carries out ion implanting, to form PXing Ti district 106, thus defines super barrier two
The channel region of pole pipe.
As shown in Figure 6, after removing graphical photoresist (structure shown in PR in figure), to polycrystalline
Silicon layer 104 carries out ion implanting process, defines p-type polysilicon 108, meanwhile, at p-type polycrystalline
The correspondence PXing Ti district, lower section 106 of silicon 108 defines P-type region 107, namely defines superpotential
Build the anode ion district of diode.
As it is shown in fig. 7, form the N+ type polysilicon layer 109 of flood.
As shown in Figure 8, N+ type polysilicon layer 109 carries out anisotropic etch processes, to form N+
Type polysilicon side wall 110.
As it is shown in figure 9, the active area forming N+ type polysilicon side wall 110 is made annealing treatment,
The ion in N+ type polysilicon side wall 110 is made to diffuse into the direct PXing Ti district 106 contacted
Specify region, to form N+ type region 111, namely define the cathode ion of super barrier diode
District.
As shown in Figure 10, the electrode 112 of super barrier diode is formed, to complete super barrier diode
Processing, namely ensure super barrier diode low on state characteristic while, it is achieved that to N+ type
Region 111 and the accurate machining in P-type region 108, it is achieved thereby that cathode ion district and anode ion
The separation in district, thus reduce leakage current, it is ensured that the reliability of super barrier diode.
Technical scheme being described in detail above in association with accompanying drawing, the present invention proposes a kind of superpotential
Build the processing method of diode and a kind of super barrier diode so that leading of the super barrier diode made
Logical pressure drop is less than the super barrier diode of traditional structure, and level of drain current will be far below tradition super barrier two
Pole is managed, and can simplify manufacturing process, reduces the manufacturing cost of super barrier diode.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for
For those skilled in the art, the present invention can have various modifications and variations.All essences in the present invention
Within god and principle, any modification, equivalent substitution and improvement etc. made, should be included in the present invention
Protection domain within.
Claims (10)
1. the processing method of a super barrier diode, it is characterised in that including:
N-type substrate sequentially forms N-type epitaxy layer, field oxide, polysilicon layer and insulation
Layer；
Described insulating barrier is formed after Patterned masking layer, described insulating barrier is carried out isotropism quarter
Erosion, to form insulating barrier mask structure；
With formed described insulating barrier mask structure as mask, successively to described polysilicon layer and described field
Oxide layer carries out anisotropic etching, to expose the appointment district of the described epitaxial layer for making body district
Territory；
PXing Ti district is formed in the appointment region of described epitaxial layer；
Described epitaxial layer below the edge through the described field layer of over etching is formed P-type region,
Meanwhile, corresponding above described P-type region described polysilicon layer forms p-type polysilicon structure；
In the described PXing Ti district forming described p-type polysilicon structure, formed and described P-type region
The N+ type region of territory separation and electrode, to complete the making of described super barrier diode.
The processing method of super barrier diode the most according to claim 1, it is characterised in that
After described insulating barrier forms Patterned masking layer, described insulating barrier is carried out isotropic etching,
To form insulating barrier mask structure, including step in detail below:
After described insulating barrier is formed graphical described mask layer, described insulating barrier is used wet
Method corrosion treatmentCorrosion Science, and/or use isotropic etch gas that described insulating barrier is carried out at dry etching
Reason, to form described insulating barrier mask structure.
The processing method of super barrier diode the most according to claim 1, it is characterised in that
PXing Ti district is formed, including step in detail below in the appointment region of described epitaxial layer:
The first ion implantation technology is used to form described PXing Ti district in the appointment region of described epitaxial layer.
The processing method of super barrier diode the most according to claim 3, it is characterised in that
Described epitaxial layer below the edge through the described field layer of over etching is formed P-type region, with
Time, described polysilicon layer corresponding above described P-type region forms p-type polysilicon structure, bag
Include step in detail below:
Use outside described below the edge through the described field layer of over etching of the second ion implantation technology
Prolong the described P-type region formed in layer, meanwhile, above described P-type region described in correspondence
Polysilicon layer forms p-type polysilicon structure.
The processing method of super barrier diode the most according to claim 4, it is characterised in that
The Implantation Energy of described first ion implantation technology is more than the injection energy of described second ion implantation technology
Amount.
The processing method of super barrier diode the most according to claim 4, it is characterised in that
The implantation dosage of described first ion implantation technology is more than the injectant of described second ion implantation technology
Amount.
The processing method of super barrier diode the most according to claim 1, it is characterised in that
In the described PXing Ti district forming described p-type polysilicon structure, formed and divide with described P-type region
From N+ type region and electrode, including step in detail below:
After forming described p-type polysilicon structure, described N-type substrate forms N+ type polysilicon
Layer.
The processing method of super barrier diode the most according to claim 7, it is characterised in that
In the described PXing Ti district forming described p-type polysilicon structure, formed and divide with described P-type region
From N+ type region and electrode, also include step in detail below:
Described N+ type polysilicon layer is carried out anisotropic etching, to remove described insulating barrier mask knot
Above structure and the N+ type polysilicon layer in described PXing Ti district, with formed simultaneously with described polysilicon layer,
The N+ type polysilicon side wall of the EDGE CONTACT in described field oxide and described PXing Ti district；
Make annealing treatment forming described N+ type polysilicon side wall, with the limit in described PXing Ti district
Edge forms the described N+ type region with described P-type region disconnecting.
The processing method of super barrier diode the most according to claim 8, it is characterised in that
In the described PXing Ti district forming described p-type polysilicon structure, formed and divide with described P-type region
From N+ type region and electrode, also include step in detail below:
After forming described N+ type region, use metal sputtering processes, electroplating technology and evaporation process
In a kind of technique or the combination in any of kinds of processes, described N-type substrate is formed simultaneously with described
Insulating barrier mask, described N-type polycrystalline silicon floor, the metal level of PXing Ti district contact, described metal level is i.e.
Electrode for described super barrier diode.
10. a super barrier diode, it is characterised in that use as appointed in claims 1 to 9
The processing method of one described super barrier diode is made.
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| US20090078962A1 (en) * | 2007-09-26 | 2009-03-26 | Lakota Technologies, Inc. | Adjustable Field Effect Rectifier |
| CN103077960A (en) * | 2013-01-28 | 2013-05-01 | 上海宝芯源功率半导体有限公司 | Groove-power device structure and manufacturing method thereof |
| CN103325839A (en) * | 2013-06-26 | 2013-09-25 | 张家港凯思半导体有限公司 | MOS super barrier rectifier device and manufacturing method thereof |
| WO2015109929A1 (en) * | 2014-01-24 | 2015-07-30 | 无锡华润华晶微电子有限公司 | Super barrier rectifier and manufacturing method therefor |
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2015
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Patent Citations (4)
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| US20090078962A1 (en) * | 2007-09-26 | 2009-03-26 | Lakota Technologies, Inc. | Adjustable Field Effect Rectifier |
| CN103077960A (en) * | 2013-01-28 | 2013-05-01 | 上海宝芯源功率半导体有限公司 | Groove-power device structure and manufacturing method thereof |
| CN103325839A (en) * | 2013-06-26 | 2013-09-25 | 张家港凯思半导体有限公司 | MOS super barrier rectifier device and manufacturing method thereof |
| WO2015109929A1 (en) * | 2014-01-24 | 2015-07-30 | 无锡华润华晶微电子有限公司 | Super barrier rectifier and manufacturing method therefor |
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