CN106206735B - Mosfet及其制造方法 - Google Patents

Mosfet及其制造方法 Download PDF

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CN106206735B
CN106206735B CN201610566545.8A CN201610566545A CN106206735B CN 106206735 B CN106206735 B CN 106206735B CN 201610566545 A CN201610566545 A CN 201610566545A CN 106206735 B CN106206735 B CN 106206735B
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CN106206735A (zh
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陈瑜
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

本发明公开了一种MOSFET，源区和所述漏区具有非对称的结构：漏区的横向结深大于所述源区的横向结深，漏区的纵向结深大于源区的纵向结深；通过增加漏区的横向结深和纵向结深来提高器件的击穿电压，通过减少源区的横向结深和纵向结深来减少器件的横向尺寸；栅介质层具有非对称的结构：栅介质层包括横向连接的第一栅介质段和第二栅介质段；第一栅介质段的厚度大于第二栅介质段的厚度；通过增加第一栅介质段的厚度减少器件的GIDL效应，通过减少第二栅介质段的厚度增加器件的驱动电流。本发明还公开了一种MOSFET的制造方法。本发明能提高器件的击穿电压同时降低器件尺寸，能减小GIDL效应同时提高器件的电流驱动能力。

Description

MOSFET及其制造方法
技术领域
本发明涉及半导体集成电路制造领域，特别是涉及一种MOSFET；本发明还涉及一种MOSFET的制造方法。
背景技术
目前半导体制造技术中常用MOS器件，如图1所示，是现有MOSFET的示意图，以N型器件为例，现有MOSFET包括：
P型的阱区101，形成于半导体衬底的表面区域。
在所述阱区101表面上依次形成有栅介质层如栅氧化层102和多晶硅栅103。
在所述多晶硅栅103的两个侧面形成有侧墙105。
在所述多晶硅栅103的两侧的所述阱区101中形成有轻掺杂的轻掺杂漏区104和重掺杂的源漏注入区106。其中，所述轻掺杂漏区104和所述多晶硅栅103的侧面自对准，所述源漏注入区106和所述多晶硅栅103两侧的所述侧墙105的侧面自对准。由所述多晶硅栅103一侧的所述轻掺杂漏区104和所述源漏注入区106叠加形成源区，由所述多晶硅栅103另一侧的所述轻掺杂漏区104和所述源漏注入区106叠加形成漏区。
由图1所述可知，现有MOSFET的所述源区和所述漏区完全对称，性能上包括击穿电压，寄生电阻，电容也完全一致。
对于现有结构，如果需要提高器件的击穿电压需要增加源漏区杂质浓度分布，需要增加源漏区结深。而为了避免源漏穿通，源漏区的结深增加会引起器件沟道长度增加，所以现有结构在提高器件的击穿电压和降低器件的尺寸之间存在矛盾。对于功率相关的应用需要将器件排列成阵列结构，单个器件的尺寸增大对于整个芯片的面积影响非常大。
同时，现有技术中，还需要增加器件的栅氧化层102的厚度来减少源漏结与多晶硅栅103交界区域的栅感应漏电电流(GIDL)，GIDL是由栅极与漏极间电场引起的漏电即。而栅氧化层102加厚会导致器件驱动电流能力下降；所以现有结构在降低GIDL和提高器件的驱动电流之间存在矛盾。
发明内容
本发明所要解决的技术问题是提供一种MOSFET，能提高器件的击穿电压同时降低器件尺寸，能减小GIDL效应同时提高器件的电流驱动能力。
为解决上述技术问题，本发明提供的MOSFET包括：
第二导电类型的阱区，形成于半导体衬底的表面区域。
在所述阱区表面上依次形成有栅介质层和多晶硅栅。
在所述阱区表面内分别形成有第一导电类型掺杂的源区和第一导电类型掺杂的漏区。
所述漏区和所述多晶硅栅的第一侧自对准，所述源区和所述多晶硅栅的第二侧自对准。
所述源区和所述漏区具有非对称的结构：所述漏区的横向结深大于所述源区的横向结深，所述漏区的纵向结深大于所述源区的纵向结深；通过增加所述漏区的横向结深和纵向结深来提高器件的击穿电压，通过减少所述源区的横向结深和纵向结深来减少器件的横向尺寸。
所述栅介质层具有非对称的结构：所述栅介质层包括横向连接的第一栅介质段和第二栅介质段；所述第一栅介质段的厚度大于所述第二栅介质段的厚度；在横向上所述漏区从所述多晶硅栅的第一侧横向延伸到所述多晶硅栅的底部并形成所述漏区和所述多晶硅栅的交叠区，所述第一栅介质段位于所述漏区和所述多晶硅栅的交叠区内；通过增加所述第一栅介质段的厚度减少器件的GIDL效应，通过减少所述第二栅介质段的厚度增加器件的驱动电流。
进一步的改进是，所述半导体衬底为硅衬底。
进一步的改进是，所述源区由第一导电类型重掺杂的源漏注入区组成，所述漏区由第一导电类型重掺杂的源漏注入区和第一导电类型轻掺杂的轻掺杂漏区叠加形成，所述源区的源漏注入区和所述漏区的源漏注入区工艺相同，通过所述轻掺杂漏区调节所述漏区的结深。
进一步的改进是，所述栅介质层为栅氧化层。
进一步的改进是，所述第二栅介质段为热氧化层或淀积氧化层，所述第一栅介质段在所述第二栅介质段上叠加了局部氧化层。
进一步的改进是，在所述多晶硅栅的侧面形成有侧墙。
进一步的改进是，MOSFET为N型器件，第一导电类型为N型；第二导电类型为P型；或者，所述MOSFET为P型器件，第一导电类型为P型；第二导电类型为N型。
为解决上述技术问题，本发明提供的MOSFET的制造方法包括如下步骤：
步骤一、提供一半导体衬底，进行第二导电类型的阱注入在所述半导体衬底的表面区域形成阱区。
步骤二、采用热氧化或化学气相淀积工艺在所述半导体衬底表面形成第一氧化层。
步骤三、采用化学气相沉积工艺以及光刻工艺在所述第一氧化层表面形成多晶硅栅；所述多晶硅栅通过所述第一氧化层覆盖在所述阱区表面。
步骤四、采用化学气相淀积工艺形成第一介质层，所述第一介质层为氮化硅或氮氧化硅。
步骤五、采用光刻加刻蚀工艺去除漏区形成区域的所述第一介质层，源区形成区域的所述第一介质层保留，所述漏区形成区域位于所述多晶硅栅的第一侧外部，所述源区形成区域位于所述多晶硅栅的第二侧外部，所保留的所述第一介质层还从所述源区形成区域延伸到所述多晶硅栅的顶部，所述第一介质层被去除的区域还从所述漏区形成区域延伸到所述多晶硅栅的顶部。
步骤六、利用所述第一介质层和其顶部的光刻胶为掩模，进行第一导电类型轻掺杂离子注入形成轻掺杂漏区，所述轻掺杂漏区和所述多晶硅栅的第一侧自对准；通过所述轻掺杂漏区的离子注入调节漏区的结深；在横向上所述所述轻掺杂漏区从所述多晶硅栅的第一侧横向延伸到所述多晶硅栅的底部并形成所述漏区和所述多晶硅栅的交叠区。
步骤七、去除所述第一介质层顶部的光刻胶，以所述第一介质层为掩模进行局部热氧化工艺形成局部热氧化层，所述局部热氧化层从所述漏区形成区域延伸到所述多晶硅栅的底部；之后，去除所述第一介质层。
由延伸到所述多晶硅栅底部的所述局部热氧化层和所述第一氧化层叠加形成第一栅介质段，由位于所述多晶硅栅底部且未叠加所述局部热氧化层的所述第一氧化层组成第二栅介质段。
由所述第一栅介质段和所述第二栅介质段横向连接形成栅介质层；所述第一栅介质段位于所述漏区和所述多晶硅栅的交叠区内；通过增加所述第一栅介质段的厚度减少器件的GIDL效应，通过减少所述第二栅介质段的厚度增加器件的驱动电流。
步骤八、进行第一导电类型重掺杂的源漏注入在所述多晶硅栅的两侧形成源漏注入区；所述源漏注入区和所述多晶硅栅两侧自对准，由位于所述多晶硅栅第一侧的所述源漏注入区叠加所述轻掺杂漏区形成漏区，由位于所述多晶硅栅第二侧的所述源漏注入区组成源区。
所述源区和所述漏区呈非对称的结构：所述漏区的横向结深大于所述源区的横向结深，所述漏区的纵向结深大于所述源区的纵向结深；通过增加所述漏区的横向结深和纵向结深来提高器件的击穿电压，通过减少所述源区的横向结深和纵向结深来减少器件的横向尺寸。
进一步的改进是，所述半导体衬底为硅衬底。
进一步的改进是，在步骤八进行所述源漏注入之前还包括采用淀积加刻蚀工艺在所述多晶硅栅的侧面形成侧墙的步骤。
所述源漏注入时以所述多晶硅栅两侧的所述侧墙为自对准边界，所述源漏注入采用带角度的倾斜注入，倾斜注入使形成的所述源漏注入区横向延伸到所述侧墙的底部且所述源漏注入区横向延伸的宽度大于所述侧墙的横向宽度的最大值。
进一步的改进是，所述源漏注入的注入角度与垂直方向的夹角大于10度，注入剂量为5E14cm-2以上。
进一步的改进是，步骤六中的所述轻掺杂离子注入的注入角度与垂直方向的夹角大于10度，注入剂量为5E14cm-2以上。
进一步的改进是，所述第一介质层的厚度为50埃～300埃。
进一步的改进是，所述局部热氧化层的厚度为30埃～300埃。
进一步的改进是，MOSFET为N型器件，第一导电类型为N型；第二导电类型为P型；或者，所述MOSFET为P型器件，第一导电类型为P型；第二导电类型为N型。
本发明通过将源区和漏区设置为非对称的结构，能够通过单独增加漏区的横向结深和纵向结深来提高器件的击穿电压；而本发明由于源区相对于漏区独立设置，利用源区不需要耐高压的特点，将源区的结深设置为小于漏区，这样能够实现通过减少源区的横向结深和纵向结深来减少器件的横向尺寸；也即本发明源区能够采用较浅的结深从而能减少器件的尺寸；所以本发明能提高器件的击穿电压同时降低器件尺寸。
本发明的漏区采用较大的结深，在横向上漏区会从多晶硅栅的第一侧横向延伸到多晶硅栅的底部并形成漏区和多晶硅栅的交叠区，本发明通过对栅介质层进行分段设置，其中第一栅介质段和交叠区相对应且二者的相对位置能够通过自对准实现并使第一栅介质段位于漏区和多晶硅栅的交叠区内；本发明能实现通过增加第一栅介质段的厚度减少器件的GIDL效应，而通过减少第二栅介质段的厚度增加器件的驱动电流；所以，本发明能减小GIDL效应同时提高器件的电流驱动能力。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明：
图1是现有MOSFET的示意图；
图2是本发明实施例MOSFET的示意图；
图3A-图3E是本发明实施例MOSFET的制造方法的各步骤中的器件结构示意图。
具体实施方式
如图3A至图3E所示，是本发明实施例MOSFET的制造方法的各步骤中的器件结构示意图，本发明实施例MOSFET包括：
第二导电类型的阱区1，形成于半导体衬底的表面区域。较佳为，所述半导体衬底为硅衬底。
在所述阱区1表面上依次形成有栅介质层和多晶硅栅3。
在所述阱区1表面内分别形成有第一导电类型掺杂的源区和第一导电类型掺杂的漏区。较佳为，所述源区由第一导电类型重掺杂的源漏注入区7组成，所述漏区由第一导电类型重掺杂的源漏注入区7和第一导电类型轻掺杂的轻掺杂漏区5叠加形成，所述源区的源漏注入区7和所述漏区的源漏注入区7工艺相同，通过所述轻掺杂漏区5调节所述漏区的结深。
在所述多晶硅栅3的侧面形成有侧墙6。所述漏区和所述多晶硅栅3的第一侧自对准，所述源区和所述多晶硅栅3的第二侧自对准。更佳选择为，所述源漏注入区7都和对应侧的所述多晶硅栅3的所述侧墙6自对准，且所述源漏注入区7在横向上都要向对应侧的所述多晶硅栅3的底部延伸，且对应的所述源漏注入区7向对应侧的所述多晶硅栅3的底部横向延伸的宽度大于所述侧墙6的最大宽度。所述轻掺杂漏区5和所述多晶硅栅3的第一侧的侧面自对准，在横向上所述轻掺杂漏区5会从所述多晶硅栅3的第一侧的侧面横向延伸到所述多晶硅栅3的底部并形成所述漏区和所述多晶硅栅3的交叠区，
由图2可知，本发明实施例的所述源区和所述漏区具有非对称的结构：所述漏区的横向结深大于所述源区的横向结深，所述漏区的纵向结深大于所述源区的纵向结深；通过增加所述漏区的横向结深和纵向结深来提高器件的击穿电压，通过减少所述源区的横向结深和纵向结深来减少器件的横向尺寸。
所述栅介质层具有非对称的结构：所述栅介质层包括横向连接的第一栅介质段4和第二栅介质段2；所述第一栅介质段4的厚度大于所述第二栅介质段2的厚度；所述第一栅介质段4位于所述漏区和所述多晶硅栅3的交叠区内；通过增加所述第一栅介质段4的厚度减少器件的GIDL效应，通过减少所述第二栅介质段2的厚度增加器件的驱动电流。较佳为，所述栅介质层为栅氧化层。更佳选择为，所述第二栅介质段2为热氧化层或淀积氧化层，所述第一栅介质段4在所述第二栅介质段2上叠加了局部氧化层。
本发明实施例MOSFET为N型器件，第一导电类型为N型；第二导电类型为P型。在其它实施例中，也能为：MOSFET为P型器件，第一导电类型为P型；第二导电类型为N型。
如图3A至图3E所示，是本发明实施例MOSFET的制造方法的各步骤中的器件结构示意图，本发明实施例MOSFET的制造方法包括如下步骤：
步骤一、如图3A所示，提供一半导体衬底，进行第二导电类型的阱注入在所述半导体衬底的表面区域形成阱区1。较佳为，所述半导体衬底为硅衬底。
步骤二、如图3A所示，采用热氧化或化学气相淀积工艺在所述半导体衬底表面形成第一氧化层2。
步骤三、如图3A所示，采用化学气相沉积工艺以及光刻工艺在所述第一氧化层2表面形成多晶硅栅3。所述多晶硅栅3通过所述第一氧化层2覆盖在所述阱区1表面。
步骤四、如图3B所示，采用化学气相淀积工艺形成第一介质层201，所述第一介质层201为氮化硅或氮氧化硅。较佳为，所述第一介质层201的厚度为50埃～300埃。
步骤五、如图3C所示，采用光刻形成光刻胶202的图形，之后采用刻蚀工艺去除漏区形成区域的所述第一介质层201，源区形成区域的所述第一介质层201保留，所述漏区形成区域位于所述多晶硅栅3的第一侧外部，所述源区形成区域位于所述多晶硅栅3的第二侧外部，所保留的所述第一介质层201还从所述源区形成区域延伸到所述多晶硅栅3的顶部，所述第一介质层201被去除的区域还从所述漏区形成区域延伸到所述多晶硅栅3的顶部。
步骤六、如图3C所示，利用所述第一介质层201和其顶部的光刻胶202为掩模，进行第一导电类型轻掺杂离子注入形成轻掺杂漏区5，所述轻掺杂漏区5和所述多晶硅栅3的第一侧自对准；通过所述轻掺杂漏区5的离子注入调节漏区的结深；在横向上所述所述轻掺杂漏区5从所述多晶硅栅3的第一侧横向延伸到所述多晶硅栅3的底部并形成所述漏区和所述多晶硅栅3的交叠区。较佳为，所述轻掺杂离子注入的注入角度与垂直方向的夹角大于10度，注入剂量为5E14cm-2以上。
步骤七、如图3D所示，去除所述第一介质层201顶部的光刻胶202，以所述第一介质层201为掩模进行局部热氧化工艺形成局部热氧化层4，所述局部热氧化层4从所述漏区形成区域延伸到所述多晶硅栅3的底部；之后，去除所述第一介质层201。较佳为，所述局部热氧化层4的厚度为30埃～300埃。
由延伸到所述多晶硅栅3底部的所述局部热氧化层4和所述第一氧化层2叠加形成第一栅介质段4，由位于所述多晶硅栅3底部且未叠加所述局部热氧化层4的所述第一氧化层2组成第二栅介质段2；
由所述第一栅介质段4和所述第二栅介质段2横向连接形成栅介质层；所述第一栅介质段4位于所述漏区和所述多晶硅栅3的交叠区内；通过增加所述第一栅介质段4的厚度减少器件的GIDL效应，通过减少所述第二栅介质段2的厚度增加器件的驱动电流。
步骤八、如图3E所示，所述源漏注入之前还包括采用淀积加刻蚀工艺在所述多晶硅栅3的侧面形成侧墙6。
如图2所示，进行第一导电类型重掺杂的源漏注入在所述多晶硅栅3的两侧形成源漏注入区7；所述源漏注入时以所述多晶硅栅3两侧的所述侧墙6为自对准边界，所述源漏注入采用带角度的倾斜注入，倾斜注入使形成的所述源漏注入区7横向延伸到所述侧墙6的底部且所述源漏注入区7横向延伸的宽度大于所述侧墙6的横向宽度的最大值。较佳为，所述源漏注入的注入角度与垂直方向的夹角大于10度，注入剂量为5E14cm-2以上。
由位于所述多晶硅栅3第一侧的所述源漏注入区7叠加所述轻掺杂漏区5形成漏区，由位于所述多晶硅栅3第二侧的所述源漏注入区7组成源区。
所述源区和所述漏区呈非对称的结构：所述漏区的横向结深大于所述源区的横向结深，所述漏区的纵向结深大于所述源区的纵向结深；通过增加所述漏区的横向结深和纵向结深来提高器件的击穿电压，通过减少所述源区的横向结深和纵向结深来减少器件的横向尺寸。
本发明实施例方法中，MOSFET为N型器件，第一导电类型为N型；第二导电类型为P型。在其它实施例方法中，也能为：MOSFET为P型器件，第一导电类型为P型；第二导电类型为N型。
以上通过具体实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (8)

1.一种MOSFET的制造方法，其特征在于，包括如下步骤：
步骤一、提供一半导体衬底，进行第二导电类型的阱注入在所述半导体衬底的表面区域形成阱区；
步骤二、采用热氧化或化学气相淀积工艺在所述半导体衬底表面形成第一氧化层；
步骤三、采用化学气相沉积工艺以及光刻工艺在所述第一氧化层表面形成多晶硅栅；所述多晶硅栅通过所述第一氧化层覆盖在所述阱区表面；
步骤四、采用化学气相淀积工艺形成第一介质层，所述第一介质层为氮化硅或氮氧化硅；
步骤五、采用光刻加刻蚀工艺去除漏区形成区域的所述第一介质层，源区形成区域的所述第一介质层保留，所述漏区形成区域位于所述多晶硅栅的第一侧外部，所述源区形成区域位于所述多晶硅栅的第二侧外部，所保留的所述第一介质层还从所述源区形成区域延伸到所述多晶硅栅的顶部，所述第一介质层被去除的区域还从所述漏区形成区域延伸到所述多晶硅栅的顶部；
步骤六、利用所述第一介质层和其顶部的光刻胶为掩模，进行第一导电类型轻掺杂离子注入形成轻掺杂漏区，所述轻掺杂漏区和所述多晶硅栅的第一侧自对准；通过所述轻掺杂漏区的离子注入调节漏区的结深；在横向上所述轻掺杂漏区从所述多晶硅栅的第一侧横向延伸到所述多晶硅栅的底部并形成所述漏区和所述多晶硅栅的交叠区；
步骤七、去除所述第一介质层顶部的光刻胶，以所述第一介质层为掩模进行局部热氧化工艺形成局部热氧化层，所述局部热氧化层从所述漏区形成区域延伸到所述多晶硅栅的底部；之后，去除所述第一介质层；
由延伸到所述多晶硅栅底部的所述局部热氧化层和所述第一氧化层叠加形成第一栅介质段，由位于所述多晶硅栅底部且未叠加所述局部热氧化层的所述第一氧化层组成第二栅介质段；
由所述第一栅介质段和所述第二栅介质段横向连接形成栅介质层；所述第一栅介质段位于所述漏区和所述多晶硅栅的交叠区内；通过增加所述第一栅介质段的厚度减少器件的GIDL效应，通过减少所述第二栅介质段的厚度增加器件的驱动电流；
步骤八、进行第一导电类型重掺杂的源漏注入在所述多晶硅栅的两侧形成源漏注入区；所述源漏注入区和所述多晶硅栅两侧自对准，由位于所述多晶硅栅第一侧的所述源漏注入区叠加所述轻掺杂漏区形成漏区，由位于所述多晶硅栅第二侧的所述源漏注入区组成源区；
所述源区和所述漏区呈非对称的结构：所述漏区的横向结深大于所述源区的横向结深，所述漏区的纵向结深大于所述源区的纵向结深；通过增加所述漏区的横向结深和纵向结深来提高器件的击穿电压，通过减少所述源区的横向结深和纵向结深来减少器件的横向尺寸。
2.如权利要求1所述的MOSFET的制造方法，其特征在于：所述半导体衬底为硅衬底。
3.如权利要求1所述的MOSFET的制造方法，其特征在于：在步骤八进行所述源漏注入之前还包括采用淀积加刻蚀工艺在所述多晶硅栅的侧面形成侧墙的步骤；
所述源漏注入时以所述多晶硅栅两侧的所述侧墙为自对准边界，所述源漏注入采用带角度的倾斜注入，倾斜注入使形成的所述源漏注入区横向延伸到所述侧墙的底部且所述源漏注入区横向延伸的宽度大于所述侧墙的横向宽度的最大值。
4.如权利要求3所述的MOSFET的制造方法，其特征在于：所述源漏注入的注入角度与垂直方向的夹角大于10度，注入剂量为5E14cm-2以上。
5.如权利要求1所述的MOSFET的制造方法，其特征在于：步骤六中的所述轻掺杂离子注入的注入角度与垂直方向的夹角大于10度，注入剂量为5E14cm-2以上。
6.如权利要求1所述的MOSFET的制造方法，其特征在于：所述第一介质层的厚度为50埃～300埃。
7.如权利要求1所述的MOSFET的制造方法，其特征在于：所述局部热氧化层的厚度为30埃～300埃。
8.如权利要求1-7中任一权利要求所述的MOSFET的制造方法，其特征在于：MOSFET为N型器件，第一导电类型为N型；第二导电类型为P型；或者，所述MOSFET为P型器件，第一导电类型为P型；第二导电类型为N型。
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