CN106158978A - 薄膜晶体管、阵列基板及其制备方法 - Google Patents

薄膜晶体管、阵列基板及其制备方法 Download PDF

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CN106158978A
CN106158978A CN201610538743.3A CN201610538743A CN106158978A CN 106158978 A CN106158978 A CN 106158978A CN 201610538743 A CN201610538743 A CN 201610538743A CN 106158978 A CN106158978 A CN 106158978A
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film transistor
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CN106158978B (zh
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秦芳
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Abstract

本发明公开了一种薄膜晶体管，包括形成于衬底上的有源层，其中，所述有源层包括叠层设置的第一半导体层和第二半导体层；所述第一半导体层的材料是原子比In/(Ga+Zn)为50％以下的铟镓锌氧化物，所述第二半导体层的材料是原子比In/(Ga+Zn)为55％以上的铟镓锌氧化物。本发明还公开了包含如上所述薄膜晶体管的阵列基板及其制备方法，该阵列基板可应用于液晶显示装置(LCD)或有机电致发光显示装置(OLED)中。如上所提供的薄膜晶体管，采用两层IGZO半导体材料作为有源层半导体，在满足薄膜晶体管的特性要求的同时，进一步提高IGZO有源层半导体的载流子迁移率。

Description

薄膜晶体管、阵列基板及其制备方法
技术领域
本发明涉及显示器技术领域,尤其涉及一种薄膜晶体管，包含该薄膜晶体管的阵列基板及其制备方法。
背景技术
平板显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平板显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)及有机电致发光显示装置(Organic Light Emitting Display，OLED)。薄膜晶体管(Thin Film Transistor，TFT)是平板显示装置的重要组成部分，可形成在玻璃基板或塑料基板上，通常作为开光装置和驱动装置用在诸如LCD、OLED。
在显示面板工业中，随着目前显示行业中大尺寸化，高解析度的需求越来越强烈，对有源层半导体器件充放电提出了更高的要求。IGZO(indium gallium zinc oxide，铟镓锌氧化物)是一种含有铟、镓和锌的非晶氧化物，其具有高迁移率，载流子迁移率是非晶硅的20～30倍，可以大大提高TFT对像素电极的充放电速率，具有高开态电流、低关态电流可以迅速开关，提高像素的响应速度，实现更快的刷新率，同时更快的响应也大大提高了像素的行扫描速率，使得超高分辨率在显示面板中成为可能。
在IGZO半导体材料中，增加In原子的含量可以提高其载流子迁移率。然而，将IGZO半导体材料作为薄膜晶体管中的有源层半导体，较大地增加In原子的含量时，有可能使得半导体变为导体，不能满足薄膜晶体管的特性要求。因此，如何在满足薄膜晶体管的特性要求的同时，进一步提高IGZO有源层半导体的载流子迁移率是目前需要解决的问题。
发明内容
有鉴于此，本发明提供了一种薄膜晶体管，其中采用IGZO半导体材料作为有源层半导体，在满足薄膜晶体管的特性要求的同时，进一步提高IGZO有源层半导体的载流子迁移率。
为了实现上述目的，本发明采用了如下的技术方案：
一种薄膜晶体管，包括形成于衬底上的有源层，其中，所述有源层包括叠层设置的第一半导体层和第二半导体层；所述第一半导体层的材料是原子比In/(Ga+Zn)为50％以下的铟镓锌氧化物，所述第二半导体层的材料是原子比In/(Ga+Zn)为55％以上的铟镓锌氧化物。
具体地，所述第一半导体层的材料是原子比In/(Ga+Zn)为40％～50％的铟镓锌氧化物。
具体地，所述第二半导体层的材料是原子比In/(Ga+Zn)为55％～60％的铟镓锌氧化物。
具体地，所述第二半导体层上还覆设有一氧保护层。
具体地，所述薄膜晶体管还包括栅电极、源电极和漏电极；其中，所述衬底上形成有一缓冲层，所述有源层的第一半导体层和第二半导体层依次形成于所述缓冲层上，所述氧保护层上依次形成有栅绝缘层和所述栅电极，所述栅电极上设置有绝缘介质层并且所述绝缘介质层覆盖所述衬底；所述源电极和漏电极形成于所述绝缘介质层上，所述源电极和漏电极分别通过设置于所述绝缘介质层中的过孔与所述有源层连接。
具体地，所述氧保护层覆盖所述有源层的中间区域，所述氧保护层的两侧裸露出所述有源层；应用离子注入工艺或等离子轰击工艺，将裸露出的有源层的第一半导体层和第二半导体层转化为导体，在所述有源层的一端形成源极连接部，另一端形成漏极连接部；所述源电极通过设置于所述绝缘介质层中的过孔连接到所述源极连接部，所述漏电极通过设置于所述绝缘介质层中的过孔连接到所述漏极连接部。
本发明还提供了一种薄膜晶体管阵列基板，包括玻璃基板以及阵列设置于玻璃基板上的薄膜晶体管，其中，所述薄膜晶体管为如上所述的薄膜晶体管。
本发明还提供了如上所述的薄膜晶体管阵列基板的制备方法，其包括步骤：S1、提供一玻璃基板，在该玻璃基板上形成缓冲层；S2、在所述缓冲层依次制备第一半导体薄膜层和第二半导体薄膜层；S3、通过第一道光罩工艺将所述第一半导体薄膜和第二半导体薄膜刻蚀形成图案化的有源层，所述有源层包括叠层设置的第一半导体层和第二半导体层；S4、在具有有源层的玻璃基板上依次制备栅绝缘薄膜层和栅电极薄膜层；S5、通过第二道光罩工艺将所述栅绝缘薄膜层和栅电极薄膜层刻蚀形成图案化的栅绝缘层和栅电极；S6、在所述栅电极上制备绝缘介质层，并且所述绝缘介质层覆盖所述玻璃基板；S7、通过第三道光罩工艺在所述绝缘介质层中制备过孔；S8、在所述绝缘介质层上制备一金属导电薄膜层；S9、通过第四道光罩工艺将所述金属导电薄膜层刻蚀形成图案化的源电极和漏电极；所述源电极和漏电极分别通过所述绝缘介质层中的过孔与所述有源层连接。
进一步地，步骤S2中，在所述第二半导体薄膜层上还制备形成氧保护薄膜层。
进一步地，步骤S5具体包括：S51、应用顶栅自对准工艺刻蚀形成所述栅绝缘层和栅电极；S52、应用离子注入工艺或等离子轰击工艺，将所述第一半导体层和第二半导体层的两端转化为导体，其中的一端形成源极连接部，另一端形成漏极连接部。
本发明实施例中提供的薄膜晶体管以及相应的阵列基板，采用两层IGZO半导体材料作为有源层半导体，富In含量的IGZO半导体层(第二半导体层)靠近GI层，降低有源半导体层受等离子体轰击造成的损伤，提高有源层半导体的载流子迁移率，而少In含量的IGZO半导体层(第一半导体层)则保证有源层半导体不会变为导体，满足薄膜晶体管的特性要求。
附图说明
图1是本发明实施例提供的薄膜晶体管的结构示意图；
图2是本发明实施例提供的薄膜晶体管阵列基板的结构示意图；
图3是本发明实施例提供的薄膜晶体管阵列基板的制备方法的工艺流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明的具体实施方式进行详细说明。这些优选实施方式的示例在附图中进行了例示。附图中所示和根据附图描述的本发明的实施方式仅仅是示例性的，并且本发明并不限于这些实施方式。
在此，还需要说明的是，为了避免因不必要的细节而模糊了本发明，在附图中仅仅示出了与根据本发明的方案密切相关的结构和/或处理步骤，而省略了与本发明关系不大的其他细节。
本实施例首先提供了一种薄膜晶体管，参阅图1，所述薄膜晶体管1形成于衬底00上，所述薄膜晶体管1包括栅电极11、栅极绝缘层12、有源层13、源电极14和漏电极15。
具体地，如图1所示，本实施例提供的薄膜晶体管1是顶栅型的薄膜晶体管，其中，所述衬底00上形成有一缓冲层16，所述有源层13形成于所述缓冲层16上，所述栅极绝缘层12和栅电极11依次形成于所述有源层13上，所述有源层13的两侧分别设置有源极连接部17和漏极连接部18。进一步地，所述栅电极11上设置有绝缘介质层19，并且所述绝缘介质层覆盖所述衬底00和源极连接部17以及漏极连接部18。所述源电极14和漏电极15形成于所述绝缘介质层19上，所述源电极14通过设置于所述绝缘介质层19中的过孔10连接到所述源极连接部17，从而实现与所述有源层13连接；所述漏电极15通过设置于所述绝缘介质层19中的过孔10连接到所述漏极连接部18，从而实现与所述有源层13连接。其中，衬底00可以采用玻璃衬底。
在本实施例中，如图1所示，所述有源层13叠层设置的第一半导体层131和第二半导体层131，第一半导体层131和第二半导体层132依次形成于所述缓冲层16上，第一半导体层131和第二半导体层132的材料均为IGZO(indium gallium zinc oxide，铟镓锌氧化物)，但是两者的In原子数含量不同。具体地，第一半导体层131是少In含量的IGZO半导体层，即，第一半导体层131的IGZO材料中，原子比In/(Ga+Zn)为50％以下，比较优选的范围是原子比In/(Ga+Zn)为40％～50％。第二半导体层132是富In含量的IGZO半导体层，即，第二半导体层132的IGZO材料中，原子比In/(Ga+Zn)为55％以上，比较优选的范围是原子比In/(Ga+Zn)为55％～60％。
如上所提供的薄膜晶体管，采用两层IGZO半导体材料作为有源层半导体，富In含量的IGZO半导体层(第二半导体层)靠近GI层，降低有源半导体层受等离子体轰击造成的损伤，提高有源层半导体的载流子迁移率，而少In含量的IGZO半导体层(第一半导体层)则保证有源层半导体不会变为导体，满足薄膜晶体管的特性要求。由此，从整体上提高了有源层半导体的载流子迁移率，提高器件结构的稳定性。
进一步地，IGZO半导体层对于工艺的条件非常敏感，空气中的H原子及后续工艺过程中都会有一定量的H原子，H原子会使IGZO半导体层的电性能发生变化，甚至会导致IGZO半导体层从半导体变为导体。有鉴于此，在本实施例中，如图1所示，所述第二半导体层132和所述栅绝缘层12之间还设置有氧保护层20。即，在首先在第一半导体层131和第二半导体层132的上方形成氧保护层20，然后再形成其他的结构层，由此减小了后续工艺过程中H原子对IGZO半导体层的电性能的影响，提高器件的品质。进一步地，氧保护层20设置在第二半导体层132和栅绝缘层12之间，还可以避免栅绝缘层12中的缺陷捕获第一半导体层131和第二半导体层132中的载流子。
进一步地，在本实施例中，所述源极连接部17和漏极连接部18是与所述第一半导体层131和第二半导体层132为一体的结构。具体地，参阅图1，所述氧保护层20覆盖所述有源层13的中间区域，所述氧保护层20的两侧裸露出所述有源层13，应用离子注入工艺或等离子轰击(Plasma)工艺，将裸露出的有源层13的第一半导体层131和第二半导体层132的转化为导体，由此，所述有源层13的一端转化为导体后形成源极连接部17，所述有源层13的另一端转化为导体后形成漏极连接部18。其中，离子注入工艺中可以是注入In离子，Plasma工艺可以使用H离子或Ar离子。如上结构中，源极连接部17和漏极连接部18与有源层13(第一半导体层131和第二半导体层132)是同层且为一体的结构，并且源极连接部17和漏极连接部18具有良好的导电性能，由此，源电极14和漏电极15分别通过源极连接部17和漏极连接部18连接到有源层13时，减小了源电极14和漏电极15与有源层13之间的接触电阻，进一步提高了器件的性能。
本实施例还提供了一种薄膜晶体管阵列基板，如图2所示，该薄膜晶体管阵列基板包括玻璃基板2以及阵列设置于玻璃基板2上的薄膜晶体管1(图1中仅示例性示出了其中的3个)，其中，所述薄膜晶体管1为如上实施例所提供的薄膜晶体管1。该薄膜晶体管阵列基板主要应用于LCD中，进一步地，由于其中的薄膜晶体管1具有较高的载流子迁移率，能够满足OLED开发要求，因此薄膜晶体管阵列基板也可以应用在OLED中。
下面参阅图3并结合图1和图2，详细介绍如上所述的薄膜晶体管阵列基板的制备方法。如图3所示，该方法包括步骤：
S1、提供一玻璃基板2(相当于附图1中的衬底00)，在该玻璃基板2上形成缓冲层(Buffer Layer)16。其中，缓冲层16可以通过磁控溅射工艺、等离子体增强化学气相沉积工艺(PECVD)、原子沉积工艺(ALD)或者溶液法等沉积工艺制备获得，缓冲层16的材料可以是有机或无机绝缘材料。
S2、在所述缓冲层16依次制备第一半导体薄膜层和第二半导体薄膜层。第一半导体薄膜层的材料是前述的少In含量的IGZO半导体材料，第二半导体薄膜层的材料是前述的富In含量的IGZO半导体材料。其中，第一半导体薄膜层和第二半导体薄膜层可以通过磁控溅射工艺、等离子体增强化学气相沉积工艺(PECVD)、原子沉积工艺(ALD)或者溶液法等沉积工艺制备获得。
S3、通过第一道光罩工艺将所述第一半导体薄膜和第二半导体薄膜刻蚀形成图案化的有源层13。所述有源层13包括叠层设置的第一半导体层131和第二半导体层132。其中，所述第一半导体层131是由所述第一半导体薄膜刻蚀形成的，所述第二半导体层132是由所述第二半导体薄膜刻蚀形成的。
S4、在具有有源层13的玻璃基板2上依次制备栅绝缘薄膜层和栅电极薄膜层。所述栅绝缘薄膜层的材料可以为二氧化硅，所述栅电极薄膜层的材料主要是金属导电材料。其中，栅绝缘薄膜层和栅电极薄膜层可以通过磁控溅射工艺、等离子体增强化学气相沉积工艺(PECVD)、原子沉积工艺(ALD)或者溶液法等沉积工艺制备获得。
S5、通过第二道光罩工艺将所述栅绝缘薄膜层和栅电极薄膜层刻蚀形成图案化的栅绝缘层12和栅电极11。其中，所述栅绝缘层12是由所述栅绝缘薄膜层刻蚀形成的，所述栅电极11是由所述栅电极薄膜层刻蚀形成的。
S6、在所述栅电极11上制备绝缘介质层19，并且所述绝缘介质层19覆盖所述玻璃基板2。其中，所述绝缘介质层19的材料可以为二氧化硅，可以通过磁控溅射工艺、等离子体增强化学气相沉积工艺(PECVD)、原子沉积工艺(ALD)或者溶液法等沉积工艺制备获得。
S7、通过第三道光罩工艺在所述绝缘介质层19中制备过孔10。
S8、在所述绝缘介质层19上制备一金属导电薄膜层。所述金属导电薄膜层可以通过磁控溅射工艺、等离子体增强化学气相沉积工艺(PECVD)、原子沉积工艺(ALD)或者溶液法等沉积工艺制备获得。
S9、通过第四道光罩工艺将所述金属导电薄膜层刻蚀形成图案化的源电极14和漏电极15。所述源电极14和漏电极15分别通过所述绝缘介质层19中的过孔10与所述有源层13连接。
以上的工艺过程中，采用了四道光罩工艺在玻璃基板2上制备获得薄膜晶体管1，对于使用IGZO半导体材料的薄膜晶体管阵列基板，使用四道光罩工艺已是比较少的光罩次数，降低了生产成本。其中，每一次光罩工艺中又分别包括掩膜、曝光、显影、刻蚀和剥离等工艺，其中刻蚀工艺包括干法刻蚀和湿法刻蚀。光罩工艺已经是现有的比较成熟的工艺技术，在此不再展开详细说明。
另外，需要说明的是，在薄膜晶体管阵列基板中，还应当包括像素电极等其他的一些图案化结构，但是这些结构与本发明方案不是密切相关，在此不再展开详细说明。
进一步地，在本实施例中，其中的步骤S2，在所述第二半导体薄膜层上还制备形成氧保护薄膜层20。具体地，在使用沉积工艺形成第二半导体薄膜层结束时，通入O2和Ar，在第二半导体薄膜层的表面上形成氧保护薄膜层，然后在第一道光罩工艺完成后，即可在第二半导体层132上获得氧保护层20。
进一步地，在本实施例中，步骤S5具体包括：
S51、应用顶栅自对准工艺刻蚀形成所述栅绝缘层12和栅电极11，所述第一半导体层131和第二半导体层132的两端分别从所述栅绝缘层12和栅电极11的两侧延伸出。其中，在刻蚀形成所述栅绝缘层12和栅电极11时，相应地刻蚀所述氧保护层20，仅保留位于所述栅绝缘层12正下方的氧保护层20，即，所述氧保护层20仅覆盖所述有源层13的中间区域，所述氧保护层20的两侧裸露出所述有源层13。
S52、应用离子注入工艺或等离子轰击工艺，将所述第一半导体层131和第二半导体层132的两端(从氧保护层20的两侧裸露出的有源层13)转化为导体，其中的一端形成源极连接部17，另一端形成漏极连接部18。其中，离子注入工艺中可以是注入In离子，Plasma工艺可以使用H离子或Ar离子。得到的结构中，源极连接部17和漏极连接部18与有源层13(第一半导体层131和第二半导体层132)是同层且为一体的结构，并且源极连接部17和漏极连接部18具有良好的导电性能，由此，源电极14和漏电极15分别通过源极连接部17和漏极连接部18连接到有源层13时，减小了源电极14和漏电极15与有源层13之间的接触电阻，进一步提高了器件的性能。
综上所述，如上实施例中提供的薄膜晶体管以及相应的阵列基板，采用两层IGZO半导体材料作为有源层半导体，富In含量的IGZO半导体层(第二半导体层)靠近GI层，降低有源半导体层受等离子体轰击造成的损伤，提高有源层半导体的载流子迁移率，而少In含量的IGZO半导体层(第一半导体层)则保证有源层半导体不会变为导体，满足薄膜晶体管的特性要求。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (10)

1.一种薄膜晶体管，包括形成于衬底上的有源层，其特征在于，所述有源层包括叠层设置的第一半导体层和第二半导体层；所述第一半导体层的材料是原子比In/(Ga+Zn)为50％以下的铟镓锌氧化物，所述第二半导体层的材料是原子比In/(Ga+Zn)为55％以上的铟镓锌氧化物。
2.根据权利要求1所述的薄膜晶体管，其特征在于，所述第一半导体层的材料是原子比In/(Ga+Zn)为40％～50％的铟镓锌氧化物。
3.根据权利要求1所述的薄膜晶体管，其特征在于，所述第二半导体层的材料是原子比In/(Ga+Zn)为55％～60％的铟镓锌氧化物。
4.根据权利要求1-3任一所述的薄膜晶体管，其特征在于，所述第二半导体层上还覆设有一氧保护层。
5.根据权利要求4所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括栅电极、源电极和漏电极；其中，所述衬底上形成有一缓冲层，所述有源层的第一半导体层和第二半导体层依次形成于所述缓冲层上，所述氧保护层上依次形成有栅绝缘层和所述栅电极，所述栅电极上设置有绝缘介质层并且所述绝缘介质层覆盖所述衬底；所述源电极和漏电极形成于所述绝缘介质层上，所述源电极和漏电极分别通过设置于所述绝缘介质层中的过孔与所述有源层连接。
6.根据权利要求5所述的薄膜晶体管，其特征在于，所述氧保护层覆盖所述有源层的中间区域，所述氧保护层的两侧裸露出所述有源层；应用离子注入工艺或等离子轰击工艺，将裸露出的有源层的第一半导体层和第二半导体层转化为导体，在所述有源层的一端形成源极连接部，另一端形成漏极连接部；所述源电极通过设置于所述绝缘介质层中的过孔连接到所述源极连接部，所述漏电极通过设置于所述绝缘介质层中的过孔连接到所述漏极连接部。
7.一种薄膜晶体管阵列基板，包括玻璃基板以及阵列设置于所述玻璃基板上的薄膜晶体管，其特征在于，所述薄膜晶体管为权利要求1-6任一所述的薄膜晶体管。
8.一种如权利要求7所述的薄膜晶体管阵列基板的制备方法，其特征在于，包括步骤：
S1、提供一玻璃基板，在该玻璃基板上形成缓冲层；
S2、在所述缓冲层依次制备第一半导体薄膜层和第二半导体薄膜层；
S3、通过第一道光罩工艺将所述第一半导体薄膜和第二半导体薄膜刻蚀形成图案化的有源层，所述有源层包括叠层设置的第一半导体层和第二半导体层；
S4、在具有有源层的玻璃基板上依次制备栅绝缘薄膜层和栅电极薄膜层；
S5、通过第二道光罩工艺将所述栅绝缘薄膜层和栅电极薄膜层刻蚀形成图案化的栅绝缘层和栅电极；
S6、在所述栅电极上制备绝缘介质层，并且所述绝缘介质层覆盖所述玻璃基板；
S7、通过第三道光罩工艺在所述绝缘介质层中制备过孔；
S8、在所述绝缘介质层上制备一金属导电薄膜层；
S9、通过第四道光罩工艺将所述金属导电薄膜层刻蚀形成图案化的源电极和漏电极；所述源电极和漏电极分别通过所述绝缘介质层中的过孔与所述有源层连接。
9.根据如权利要求8所述的薄膜晶体管阵列基板的制备方法，其特征在于，步骤S2中，在所述第二半导体薄膜层上还制备形成氧保护薄膜层。
10.根据如权利要求8或9所述的薄膜晶体管阵列基板的制备方法，其特征在于，步骤S5具体包括：
S51、应用顶栅自对准工艺刻蚀形成所述栅绝缘层和栅电极；
S52、应用离子注入工艺或等离子轰击工艺，将所述第一半导体层和第二半导体层的两端转化为导体，其中的一端形成源极连接部，另一端形成漏极连接部。
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