CN106158839B - 半导体器件 - Google Patents

半导体器件 Download PDF

Info

Publication number
CN106158839B
CN106158839B CN201610305651.0A CN201610305651A CN106158839B CN 106158839 B CN106158839 B CN 106158839B CN 201610305651 A CN201610305651 A CN 201610305651A CN 106158839 B CN106158839 B CN 106158839B
Authority
CN
China
Prior art keywords
terminal
semiconductor chip
width
heat sink
increased
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201610305651.0A
Other languages
English (en)
Other versions
CN106158839A (zh
Inventor
福冈大辅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Publication of CN106158839A publication Critical patent/CN106158839A/zh
Application granted granted Critical
Publication of CN106158839B publication Critical patent/CN106158839B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H01L27/0664—Vertical bipolar transistor in combination with diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)

Abstract

半导体器件包括半导体芯片(11)、金属构件(13)和端子(14)。所述半导体芯片(11)具有电极(12)。所述金属构件(13)电连接至电极(12)。所述端子从要连接至外部连接构件的所述金属构件(13)延伸。所述端子在从所述端子的连接至所述金属构件的第一端开始的预定区域中具有宽度增加的部分(141a、143a)。

Description

半导体器件
技术领域
本公开内容涉及一种半导体器件，该半导体器件包括：半导体芯片；金属构件，该金属构件电连接至半导体芯片的电极；以及端子，该端子从要连接至外部连接构件的金属构件延伸。
背景技术
例如，JP2012-235081A公开了一种半导体器件，该半导体器件包括：作为半导体芯片的半导体元件；作为电连接至半导体芯片的电极的金属构件的厚板部分；以及用于连接至外部连接构件的端子，例如高电位电源端子、低电位电源端子和输出端子。
在这种半导体器件中，端子从金属构件延伸出预定宽度，例如恒定宽度。具有恒定宽度的端子可能会由于通过连接构件传输的外部振动而振动。在这种情况下，端子的基底部分受压。结果，端子的连接可靠性降低。
关于在金属构件与端子之间的电流路径，电流路径的宽度在基底部分附近发生较大地改变，并且由此电流密度增加。电流的浓度引起电感增加。
发明内容
本公开内容的一个目的是提供一种能够限制端子的振动和电流浓度的半导体器件。
根据本公开内容的一方面，半导体器件包括半导体芯片、金属构件和端子。半导体芯片具有电极。金属构件电连接至电极。端子从要连接至外部连接构件的金属构件延伸。端子在从端子的与金属构件相邻的第一端开始的预定区域中具有宽度增加的部分。
在半导体器件中，端子具有与连接至金属构件的第一端相邻的宽度增加的部分，并且由此加固了连接至金属构件的端子的基底部分。因此，限制了端子由于从外部器件传输的振动而发生振动。
在具有宽度增加的部分的端子中，在端子与金属构件之间的电流路径的宽度的改变小于在不具有宽度增加的部分的端子中的情况。因此，可以减小在端子的第一端处的电流浓度。因此，可以限制端子的振动和在端子中的电流浓度。
附图说明
参考附图根据以下具体实施方式，本公开内容的上述和其它目的、特征和优点将变得更加显而易见，在附图中相同部分用相同附图标记表示，并且在附图中：
图1是应用根据本公开内容的第一实施例的半导体器件的功率转换设备的示意性电路图；
图2是根据第一实施例的半导体器件的示意性平面图；
图3是根据第一实施例的不具有包封树脂体的半导体器件的平面图；
图4是沿着图2中的线Ⅳ-Ⅳ截取的截面图；
图5是根据第一实施例的半导体器件的端子的宽度增加的部分的放大图；以及
图6是根据本公开内容的第二实施例的半导体器件的端子的宽度增加的部分的放大截面图。
具体实施方式
在下文中，将参照附图对本公开内容的各个实施例进行描述。
在以下说明中，相同或者等效部件将用相同附图标记表示。在以下说明中，测量半导体芯片的厚度的厚度方向被称为Z方向。与Z方向垂直并且在其中布置有上臂的半导体芯片和下臂的半导体芯片的方向被称为X方向，并且还被称为布置方向。X方向对应于与厚度方向垂直的方向。与Z方向和X方向垂直的方向被称为Y方向。包括X方向和Y方向的平面被称为XY平面，并且与Z方向垂直。沿着XY平面的形状被称为平面形状。
(第一实施例)
首先，将参照图1对采用半导体器件的功率转换设备的示例进行描述。
功率转换装置1被配置为将从直流电源2供应的直流电压转换为三相交流电，并且将三相交流电输出至三相交流电机3。例如，功率转换设备1安装在电动车辆或者混合动力车辆中。功率转换设备1可以将从电机3生成的电力转换成直流电，并且将直流电充电至直流源2(电池)。因此，电机3还可以被称为电动发电机。在图1中，附图标记4指平滑电容器。
功率转换设备1包括三相逆变器。三相逆变器在连接至直流源2的正端子的高电位电源线5与连接至直流源2的低电位端子的低电位电源线6之间具有用于三个相的上臂和下臂。构成每个相的上臂和下臂由半导体器件10提供。
半导体器件10包括绝缘栅极双极晶体管(在下文中称为IGBT)和反向并联连接至相应的IGBT的续流二极管(在下文中称为FWD)。在本实施例中，IGBT和FWD形成在半导体芯片11中。作为另一示例，IGBT和FWD可以形成在单独的芯片中。在本实施例中，IGBT为n沟道型。FWD的阴极电极与集电极电极共同地连接。FWD的阳极电极与发射极电极共同地连接。
在半导体器件10中，上臂的IGBT的集电极电极电连接至高电位电源线5，并且上臂的IGBT的发射极电极连接至输出线7，输出线7连接至电机3。下臂的IGBT的集电极电极连接至输出线7，并且下臂的IGBT的发射极电极电连接至低电位电源线6。
除了三相逆变器之外，功率转换设备1可以包括：升压转换器，其用于对从直流源2供应的直流电压进行升压；以及控制器，其用于控制对三相逆变器和升压转换器的开关元件的操作。
接下来，将参照图2至图4对半导体器件10的示意性结构进行描述。在图3中，没有图示出包封树脂体。
如图2至图4所示，半导体器件10包括：具有电极12的半导体芯片11；电连接至电极12的散热器13；以及主端子14，其从要电连接至外部连接构件的散热器13延伸。作为主端子14，半导体器件10包括连接至高电位电源线5的高电位电源端子141、连接至低电位电源线6的低电位电源端子142、和连接至输出线7的输出端子143。在下文中，高电位电源端子141还将被称为P端子141。同样，低电位电源端子142还将被称为N端子142，并且输出端子143还将被称为O端子143。主端子14与端子对应。在主端子14中，P端子141和O端子143与具有宽度增加的部分的端子对应。进一步地，P端子141与第一主端子对应，O端子143与第二主端子对应，并且N端子142与第三主端子对应。
半导体器件10进一步包括端子15、信号端子16和包封树脂体17。端子15设置在散热器13与半导体芯片11之间。端子15电连接并且热连接在散热器13与半导体芯片11之间。包封树脂体17将半导体芯片11包封在其中。作为半导体芯片11，半导体器件10包括上臂的半导体芯片111、和下臂的半导体芯片112。作为端子15，半导体器件10包括与半导体芯片111对应的端子151和与半导体芯片112对应的端子152。
作为主端子14，半导体器件10包括连接至高电位电源线5的高电位电源端子141、连接至低电位电源线6的低电位电源端子142、和连接至输出线7的输出端子143。在下文中，高电位电源端子141还被称为P端子141。同样，低电位电源端子142还被称为N端子142，并且输出端子143还被称为O端子143。
半导体芯片11包括由硅(Si)或者碳化硅(SiC)制成的半导体衬底、和形成在半导体衬底上的IGBT和FWD。FWD反向并联连接至IGBT。即，半导体芯片11形成有RC(反向导通)IGBT。IGBT和FWD具有所谓的垂直结构，其允许电流在半导体芯片11的厚度方向(即，在Z方向)上流动。作为电极12，半导体芯片11在一个表面上具有集电极电极12a并且在与所述一个表面相对的另一表面(背表面)上具有发射极电极12b，在所述一个表面上相对于厚度方向(Z方向)设置集电极电极12a。集电极电极12a形成在半导体芯片11的近乎整个表面中。发射极电极12b形成在半导体芯片11的背表面的有源区中。多个焊盘设置在与半导体芯片11的背表面上的有源区不同的***区上。焊盘包括电连接至栅极电极的焊盘。
作为半导体芯片11，半导体器件10包括上臂的半导体芯片111和下臂的半导体芯片112。半导体芯片111、112中的每一个形成有IGBT和FWD。半导体芯片111与第一半导体芯片对应，并且半导体芯片112与第二半导体芯片112对应。半导体芯片111、112具有大体上相同的平面形状(例如矩形形状)以及大体上相同的大小和厚度。半导体芯片111和半导体芯片112被布置为使得相应的集电极电极12相对于Z方向定向在相同方向上，即，相应的集电极电极12相对于Z方向设置在相同侧上。进一步地，半导体芯片111和半导体芯片112在Z方向上位于大体上相同的高度，并且在X方向上被并排布置。
散热器13电连接至相应的半导体芯片11的电极12。散热器13用作布线以将半导体芯片11电连接至外部器件。散热器13还用于将从半导体芯片11生成的热量消散至半导体器件10外部。因此，散热器13由具有导热性和导电性的金属材料(例如铜)制成。散热器13与金属构件对应。
作为散热器13，半导体器件10包括与半导体芯片11的集电极电极12a相邻设置的散热器131、132、和与半导体芯片11的发射极电极12b相邻设置的散热器133、134。具体而言，散热器131与半导体芯片111的集电极电极12a相邻设置，并且散热器133与半导体芯片111的发射极12b相邻设置。在这种情况下，散热器131与第一散热器对应，并且散热器133与第二散热器对应。同样，散热器132与半导体芯片112的集电极电极12a相邻设置，并且散热器134与半导体芯片112的发射极电极12b相邻设置。在这种情况下，散热器132与第三散热器对应，并且散热器134与第四散热器对应。诸如第一散热器至第四散热器131、132、133和134等散热器13中的每一个散热器在平面图中具有矩形形状。
在从Z方向上投射的视图中，与半导体芯片111的集电极电极12a相邻设置的散热器131被布置为环绕半导体芯片111(集电极电极12a)。焊料18设置在散热器131的表面131a与半导体芯片111的集电极电极12a之间。焊料18将散热器131和半导体芯片111的集电极电极12a电连接并且热电连接。包封树脂体117相对于Z方向具有第一表面17a和与第一表面17a相对的第二表面(背表面)17b。散热器131具有与半导体芯片111相邻的表面131a、和与表面131a相对的热辐射表面131b。散热器131的热辐射表面131b从包封树脂体17的第一表面17a暴露出来。热辐射表面131b与第一表面17a大体上共平面。
如图3所示，P端子141连接至散热器131。即，P端子141电连接至散热器131。P端子141可以与散热器131一体形成。替代地，P端子141和散热器131可以由不同零件制成，并且相互连接。在本实施例中，P端子141与散热器131一体形成。P端子141具有比散热器131的厚度更小的厚度。P端子141从散热器131的侧表面中的一个侧表面在Y方向上延伸。如图2所示，P端子141从包封树脂体17的侧表面17c突出到包封树脂体17的外部。
散热器131和散热器132布置在X方向上。散热器132与半导体芯片112的集电极电极12a相邻设置。在从Z方向投射的视图中，散热器132被布置为环绕半导体芯片112(集电极电极12a)。焊料19设置在散热器132的表面132a与半导体芯片112的集电极电极12a之间。焊料19将散热器132和半导体芯片112的集电极电极12a电连接并且热连接。散热器132具有与半导体芯片112相邻的表面132a、和与表面132a相对的热辐射表面132b。热辐射表面132b从包封树脂体17的第一表面17a暴露出来。热辐射表面132b还与包封树脂体17的第一表面17a大体上共平面。
如图3和图4所示，散热器132具有联接部分132c。联接部分132c具有比散热器132的其它部分(本体部分)更小的厚度。联接部分132c从散热器132的侧表面的其中之一朝着散热器133延伸。联接部分132c具有两个弯曲部分。
如图3所示，O端子143连接至散热器132。即，O端子143电连接至散热器132。O端子143可以与散热器132一体形成。替代地，O端子143和散热器132可以由不同零件制成，并且相互连接。在本实施例中，O端子143与散热器132一体形成。O端子143具有比散热器132的厚度更小的厚度。O端子143从散热器132的侧表面的其中之一在Y方向上延伸。如图2所示，O端子143从包封树脂体17的侧表面17c突出至包封树脂体17的外部，该侧表面与P端子141从其突出的侧表面相同。
散热器133与半导体芯片111的发射极电极12b相邻设置。在从Z方向投射的视图中，散热器133被布置为环绕半导体芯片111。端子151设置在散热器133的与半导体芯片111相邻的表面133a与半导体芯片111的发射极电极12b之间。端子151确保用于通过接合线20连接信号端子16和半导体芯片111的焊盘所需的高度。端子151由包括至少一种金属材料的材料制成以具有导电性和导热性。端子151将半导体芯片111的发射极电极12b和散热器133电连接并且热连接。端子151被设置为与半导体芯片111的发射极电极12b相对并且通过焊料21电连接至发射极电极12b。
散热器133被布置为使得当在Z方向上投射时散热器133的大部分与散热器133重叠。散热器133被布置为与端子151的与半导体芯片111相对的表面相对。散热器133的表面133a通过焊料22电连接至端子151。散热器133具有与和端子151相邻的表面133a相对的热辐射表面133b。热辐射表面133b从包封树脂体17的第二表面17b暴露出来。热辐射表面133b与第二表面17b大体上共平面。
如图3和图4所示，散热器133具有联接部分133c。联接部分133c具有比散热器133的其它部分(本体部分)的厚度更小的厚度。联接部分133c从散热器133的侧表面的其中之一朝着散热器134在X方向上延伸。联接133c的尖端部分和联接132c的尖端部分在Z方向上彼此相对并且通过焊料23而彼此电连接。
散热器134与半导体芯片112的发射极电极12b相邻设置。在从Z方向投射的视图中，散热器134被布置为环绕半导体芯片112。端子152设置在散热器134的与半导体芯片112相邻的表面134a与半导体芯片112的发射极电极12b之间。端子152确保用于通过接合线20连接信号端子16和半导体芯片112的焊盘所需的高度。端子152由包括至少一种金属材料的材料制成以具有导电性和导热性。端子152电连接并且热连接在半导体芯片112的发射极电极12b与散热器134之间。端子152设置为与半导体芯片112的发射极电极12b相对。端子152通过焊料24电连接至发射极电极12b。
在从Z方向投射的视图中，散热器134被布置为使得散热器134的大部分与散热器132重叠。散热器134被布置为与端子152的与半导体芯片112相对的表面相对。散热器134的表面134a通过焊料25电连接至端子152。散热器134具有与表面134a相对的热辐射表面134b。热辐射表面134b从包封树脂体17的第二表面17b暴露出来。热辐射表面134b与第二表面17b大体上共平面。
如图3所示，散热器134具有联接部分134c。联接部分134c具有比散热器134的其它部分(本体部分)更小的厚度。联接部分134c从散热器134的侧表面的其中之一朝着散热器133并且在X方向上延伸。联接部分134c在Y方向上从联接部分133c偏移。
如图3所示，N端子142电连接至联接部分134c。N端子142在Y方向上延伸并且从包封树脂体17的侧表面17c突出至包封树脂体17的外部，侧表面17c与P端子141和O端子143从其突出的侧表面相同。主端子14(141、142、143)的从包封树脂体17突出的突出部分位于相对于Z方向大体上相同的位置处。同样，主端子14(141、142、143)的突出部分被布置在Y方向上，使得N端子142位于P端子141与O端子143之间。
信号端子16通过接合线20电连接至对应的半导体芯片11(111、112)的焊盘。如图2和图3所示，信号端子16在Y方向上延伸。信号端子16从包封树脂体17的与侧表面17c相对的侧表面17d突出至包封树脂体17的外部。
包封树脂体17一体包封具有电极12的半导体芯片11(111、112)、散热器13(131、132、133、134)的零件、主端子14(141、142、143)的零件、端子15(151、152)、以及信号端子16的零件。例如，通过传递模塑方法由环氧树脂制成包封树脂体17。如图2所示，包封树脂体17在平面图中具有矩形形状。充当主端子的P端子141、N端子142和O端子143从包封树脂体17的与X方向大体上平行的侧表面17c向外延伸。信号端子16从包封树脂体17的与侧表面17c相对的侧表面17d向外延伸。
具有如上所描述的结构的半导体器件10是所谓的“二合一封装体”，在一个封装体中具有两个半导体芯片11。散热器13位于半导体芯片11中的每个半导体芯片的相对于Z方向的相对侧上。半导体芯片11的热量可以从每个半导体芯片11的相对侧消散。具体地，在上臂中，散热器131、焊料18、半导体芯片111、焊料21、端子151、焊料22、散热器133在Z方向上从包封树脂体17的第一表面17a开始按照该顺序彼此堆叠地布置。在下臂中，散热器132、焊料19、半导体芯片112、焊料24、端子152、焊料25和散热器134在Z方向上从包封树脂体17的表面开始按照该顺序彼此堆叠地布置。即，部件按照相同的顺序在Z方向上布置在上臂与下臂之间。
接下来，将参照图3和图5对主端子14进行描述。
在以下说明中，“宽度”指示在与主端子14的纵向方向(Y方向)垂直并且与主端子14的厚度方向(Z方向)垂直的方向(X)方向中的尺寸。在图3中，用影线示出宽度增加的部分141a、143a以便阐明形成区域。
如图3和图5所示，位于在X方向上紧靠彼此布置的三个主端子14的相对端的P端子141和O端子143对应地连接至散热器13的本体部分。要注意的是本体部分是散热器的不包括联接部分132c、133c和134c的部分。即，本体部分是散热器的大体上矩形的部分。具体而言，P端子141连接至散热器131的本体部分，并且O端子143连接至散热器132的本体部分。位于P端子141与O端子143之间的N端子142连接至对应的散热器134的联接部分134c，而非连接至散热器134的本体部分。
P端子141在从连接至散热器131的端部开始的预定区域中具有宽度增加的部分141a。同样，O端子143在从连接至散热器132的端部开始的预定区域中具有宽度增加的部分143a。
宽度增加的部分141a具有第一端141a1以及第二端141a2，第一端141a1在Y方向上限定连接至散热器131的连接端，第二端141a2与第一端141a1相对。在本实施例中，第二端141a2的宽度是在宽度增加的部分141a中最小的宽度。宽度增加的部分141a的宽度朝着散热器131增加。即，宽度增加的部分141a的宽度从第二端141a2朝着第一端141a1增加，并且在第一端141a1处最大。
在本实施例中，与P端子141的位于包封树脂体17的侧表面17c处的包封端部分141b相比，宽度增加的部分141a位于包封树脂体17的更内部。即，宽度增加的部分141a形成在被包封树脂体17覆盖的位置处。P端子141的突出到包封树脂体17外部的连接部分141c连接至连接构件(未示出)，例如汇流条。在本实施例中，P端子141从第二端141a2至连接部分141c的尖端具有恒定宽度。即，包封端部141b的宽度和连接部分141c的宽度与宽度增加的部分141a的第二端141a2的宽度相同。
具体地，宽度增加的部分141a的在X方向上与N端子142相邻的侧端具有锥形形状。宽度增加的部分141a的与N端子142相对的侧端在Y方向上成直线并且将散热器131和连接部分141c直线连接。即，宽度增加的部分141a在平面图中具有大体上梯形形状。由此，宽度增加的部分141a的宽度从散热器131的本体部分朝着连接部分141c逐渐减小。
宽度增加的部分143a具有与宽度增加的部分141a大体上相似的结构。宽度增加的部分143a具有第一端143a1以及第二端143a2，第一端143a1在Y方向上限定连接至散热器132的连接端，第二端143a2与第一端143a1相对。在本实施例中，第二端143a2的宽度在宽度增加的部分143a中最小。宽度增加的部分141a的宽度朝着散热器131增加。即，宽度增加的部分143a的宽度从第二端143a2朝着第一端143a1增加，并且在第一端143a1处最大。
在本实施例中，与O端子143的位于包封树脂体17的侧表面17c处的包封端部分143b相比，宽度增加的部分143a位于包封树脂体17的更内部。即，宽度增加的部分143a形成在被包封树脂体17覆盖的位置处。O端子143的突出到包封树脂体17外部的连接部分143c连接至连接构件(未示出)，例如汇流条。在本实施例中，O端子143从第二端143a2至连接部分143c具有恒定宽度。即，包封端143b的宽度和连接部分143c的宽度与宽度增加的部分143a的第二端143a2的宽度相同。连接部分143c具有与连接部分141c大体上相同的宽度。
具体地，宽度增加的部分143a的在X方向上与N端子142相邻的侧端具有锥形形状。宽度增加的部分的与N端子142相对的侧端也具有锥形形状。由此，宽度增加的部分143a具有大体上等腰梯形形状。由于宽度增加的部分143a在平面形状中具有大体上等腰梯形形状，所以宽度增加的部分143a的宽度从散热器132的本体部分朝着连接部分143c逐渐减小。
N端子142通过焊料(未示出)连接至散热器134的联接处134c，以使得N端子142连接至散热器134。N端子142具有连接部分142a以连接至联接部分134c。连接部分142a具有恒定宽度。N端子142具有连接部分142b，其为从包封树脂体17突出并且连接有诸如汇流条等连接构件(未示出)的部分。连接部分142a的宽度小于连接部分142b的宽度，以确保用于与在X方向上相邻的P端子141和O端子143中的每个端子绝缘的间隙。
N端子142在从连接至连接部分142a的连接端开始的预定区域中具有宽度增加的部分142c。宽度增加的部分142c具有锥形形状以确保用于与P端子141和O端子143中的每个端子绝缘的间隙。宽度增加的部分142c的锥形形状与P端子141和O端子143的宽度增加的部分141a、143a的锥形形状相对。即，宽度增加的部分142c的宽度在连接至连接部分142a的连接端处最小。宽度增加的部分142c在与连接部分142b相邻的端部处的宽度比在连接至连接部分142a的连接端处的宽度更大，并且在与连接部分142b相邻的端部处最大。
在本实施例中，N端子142在被包封树脂体17覆盖的区域中具有与其它宽度增加的部分141a、143a相似的宽度增加的部分142c。在本实施例中，N端子142的从连接至宽度增加的部分142a的端部到连接部分142b的尖端的部分具有恒定宽度。连接部分142b具有与连接部分141c和143c大体上相同的宽度。
接下来，将对上面描述的半导体器件10的有利效果进行描述。
在本实施例中，在主端子14中，P端子141和O端子143在从连接至对应散热器13(131、132)的连接端开始的预定区域中具有宽度增加的部分141a和143a。因此，与P端子141和O端子143的端部141a1、143a1相邻的部分，即，连接至散热器13的基底部分被加固。与P端子141和O端子143以恒定宽度(即，不具有宽度增加的部分)连接至对应散热器13的常规结构相比，可以减小由于通过连接构件(例如，汇流条)从外部器件传输的振动而引起的P端子141和O端子143的振动。
由于P端子141和O端子143具有宽度增加的部分141a、143a，所以在连接至对应散热器的连接部分处的宽度变化可以小于常规结构在连接部分处的宽度变化。即，在电流路径的宽度中的变化小于常规结构的变化。如此，可以减小在P端子141和O端子143的连接至对应散热器13的连接部分上的电流浓度。如上所描述的，在限制P端子141和O端子143的振动的同时，可以减小电流浓度。由于可以减少P端子141和O端子143的振动，所以可以减小由于振动而发生在包封树脂体17中的分离。
在连接至对应散热器13的基底部分处具有宽度增加的部分的主端子14不限于上面描述的示例。在三个主端子14中，至少一个端子可以具有宽度增加的部分。替代地，所有三个主端子14可以具有宽度增加的部分。在本实施例中，在X方向上布置的三个主端子14的相对侧处布置的P端子141和O端子143具有宽度增加的部分141a、143a。在这种情况下，可以在X方向上的相对端处限制振动，并且与其中仅仅N端子142具有宽度增加的部分的情况相比，可以减小在半导体器件10中的振动。位于P端子141与O端子143之间的N端子142具有带有锥形形状的宽度增加的部分。宽度增加的部分142c的锥形形状与位于相对侧上的宽度增加的部分141c、143c的锥形形状不同，即，与其相对。因此，在保持用于绝缘的间隙的同时，可以限制在X方向上的尺寸的增加。进一步地，宽度增加的部分142c限制在N端子142中的电流浓度。
在本实施例中，宽度增加的部分141a、143a在第二端141a2、143a2处具有最小宽度。因此，与宽度在第一端141a1、143a1与第二端141a2、143a2之间的部分处最小的结构相比，可以有效地限制电流浓度。具体而言，宽度增加的部分141a、143a的宽度朝着对应散热器13(131、132)增加。由于宽度增加的部分141a、143a的宽度朝着对应散热器13逐渐增加，所以可以进一步有效地限制电流浓度。当振动被从外部传输至P端子141和O端子143时，应力较不可能集中于一部分。因此，可以进一步改进连接的可靠性。
作为宽度增加的部分141a、143a的宽度在第二端141a2、143a2处最小的结构，不限于宽度增加的部分141a、143a朝着散热器13逐渐增加的结构。宽度增加的部分141a、143a可以具有任何其它形状。例如，宽度增加的部分141a、143a的宽度可以阶梯式增加。
(第二实施例)
在第二实施例的以下说明中，将不再重复对与第一实施例的半导体器件10的部分相似的部分的说明。
在第二实施例中，除了第一实施例的结构之外，P端子141和O端子143的与散热器13相邻的第一端141a1、143a1的厚度大于第二端141a2、143a2的厚度，并且宽度增加的部分11a、143a的厚度在宽度增加的部分141a、143a处最大。图6是沿着与图3中的线Ⅵ-Ⅵ对应的线截取的宽度增加的部分141a的截面图。
如图6所示，宽度增加的部分141a的厚度在第一端141a1处最大，并且在第二端141a2处最小。在本实施例中，第二端141a2的厚度与连接部分141c的厚度相同。进一步地，在第一端141a1与第二端141a2之间的任何两个任意位置中，与第一端141a1相邻的一个位置的厚度等于或者大于与第二端141a2相邻的另一位置。在本实施例中，在宽度增加的部分141a的从第一端141a1开始的预定范围中的部分的厚度朝着第一端141a1增加，并且宽度增加的部分141a的其余部分的厚度恒定。虽然未图示，但是宽度增加的部分143a具有与宽度增加的部分141a相似的厚度。
在本实施例中，P端子141和O端子143的基底部分不仅在宽度方向上还在厚度方向上都被加固。因此，可以进一步有效地限制由于通过连接构件(例如，汇流条)传输的外部振动而产生的P端子141和O端子143的振动。
P端子141和O端子143的连接至对应散热器13的连接部分的厚度变化小于在常规结构中的变化。因此，电流路径的厚度变化小于在常规结构中的变化。如此，可以进一步有效地减小在P端子141和O端子143的连接至对应散热器13的连接部分处的电流浓度。
与宽度的变化相似，宽度增加的部分14(141a、143a)的厚度可以朝着对应散热器13(131、132)逐渐增加。在宽度增加的部分141a、143a的厚度朝着对应散热器13逐渐增加的情况下，可以进一步有效地限制电流浓度。当从外部传输振动时，应力很难集中于一点。因此，可以进一步改进连接的可靠性。
在上面描述的实施例中，宽度增加的部分141a、143a全部包封在包封树脂体17中。作为另一示例，宽度增加的部分141a、143a可以部分地设置在包封树脂体17外部。即，宽度增加的部分141a、143a可以部分地从包封树脂体17的侧表面17c突出。在这种情况下，包封端141b、143b位于锥形形状上的部分处。
主端子14的在X方向上的布置的顺序未被特别限制。
在上面描述的实施例中，P端子141和O端子143的连接部分141c、143c的宽度从第二端141a2、143a2开始示例性地恒定。即，宽度增加的部分141a、143a的宽度示例性地等于或者大于连接部分141c、143c的宽度。作为另一示例，连接部分141c、143c的宽度可以大于第二端141a2、143a2的宽度。作为又一示例，连接部分141c、143c的宽度可以大于宽度增加的部分141a、143a的宽度。
半导体器件10的结构不限于上面描述的示例。在上文的说明中，半导体器件10具有一个相的上臂和下臂。作为另一示例，半导体器件10可以具有三个相的上臂和下臂。作为又一示例，半导体器件10可以仅仅具有上臂和下臂中的一个，即，可以具有仅仅一个半导体芯片11。
作为两侧热辐射结构的半导体器件10，并不总是需要具有端子15(151、152)。两侧热辐射结构的半导体器件10可以不具有端子15(151、152)。
在上面描述的实施例中，散热器13示例性地设置在半导体芯片11的相对侧上。作为另一示例，半导体器件10可以具有一侧热辐射结构，其中散热器13(金属构件)仅仅设置在半导体芯片11的一侧上。
作为金属构件的示例，采用散热器13。然而，金属构件不限于散热器13，但是可以是电连接至半导体芯片11的电极12的任何金属构件。并不总是需要半导体器件10具有包封树脂体17。
虽然已经仅选取所选择的示例性实施例和示例来图示本公开内容，但是根据该公开内容对本领域的技术人员而言显而易见的是，在不背离根据所附权利要求书所限定的本公开内容的范围的情况下，可以进行各种改变和修改。此外，提供根据本公开内容的示例性实施例和示例的前述说明仅仅是用于进行图示，而并不是用于限制由所附权利要求书及其等效物所限定的本公开内容的目的。

Claims (8)

1.一种半导体器件，其包括：
半导体芯片(11)，所述半导体芯片(11)具有电极(12)；
金属构件(13)，所述金属构件(13)电连接至所述电极；以及
端子，所述端子从要连接至外部连接构件的所述金属构件延伸，所述端子在从所述端子的连接至所述金属构件的第一端开始的预定区域中具有宽度增加的部分(141a、143a)，
所述宽度增加的部分具有第一端(141a1)以及第二端(141a2)，所述第一端(141a1)限定所述端子的第一端，所述第二端(141a2)与所述第一端(141a1)相对，
所述宽度增加的部分的所述第一端具有比所述宽度增加的部分的所述第二端的厚度更大的厚度，并且
所述宽度增加的部分在所述第一端处具有最大厚度。
2.根据权利要求1所述的半导体器件，其中
所述宽度增加的部分在所述第二端处具有最小宽度。
3.根据权利要求2所述的半导体器件，其中
所述宽度增加的部分的所述宽度从所述第二端朝着所述第一端增加。
4.根据权利要求1至3中任一项所述的半导体器件，还包括：
包封树脂体(17)，所述包封树脂体(17)包封所述半导体芯片，其中
所述端子从所述包封树脂体的侧表面突出到所述包封树脂体的外部。
5.根据权利要求4所述的半导体器件，其中
所述宽度增加的部分的所述第一端包封在所述包封树脂体中，并且
所述第一端的宽度大于所述端子在与所述包封树脂体的所述侧表面对应的位置处的宽度。
6.根据权利要求4所述的半导体器件，其中
所述端子包括连接部分(141c、143c)，所述连接部分(141c、143c)位于所述包封树脂体的外部并且要连接至所述连接构件，并且
所述宽度增加的部分的所述宽度等于或者大于所述连接部分。
7.根据权利要求4所述的半导体器件，其中
所述半导体芯片包括第一半导体芯片(111)和第二半导体芯片(112)，
所述第一半导体芯片和所述第二半导体芯片被布置在与所述第一半导体芯片和所述第二半导体芯片的厚度方向垂直的布置方向上，
所述第一半导体芯片和所述第二半导体芯片中的每个半导体芯片在所述厚度方向上在第一表面和与所述第一表面相对的第二表面中的每个表面上具有所述电极，
所述金属构件包括第一散热器(131)、第二散热器(133)、第三散热器(132)和第四散热器(134)，
所述第一散热器电连接至所述第一半导体芯片的所述第一表面上的所述电极，
所述第二散热器电连接至所述第一半导体芯片的所述第二表面上的所述电极，
所述第三散热器电连接至所述第二半导体芯片的所述第一表面上的所述电极并且电连接至所述第二散热器，并且
所述第四散热器电连接至所述第二半导体芯片的所述第二表面上的所述电极，
所述半导体器件包括：
第一主端子(141)，所述第一主端子(141)从所述第一散热器延伸；
第二主端子(143)，所述第二主端子(143)从所述第二散热器和所述第三散热器的至少其中之一延伸；以及
第三主端子(142)，所述第三主端子(142)从所述第四散热器延伸，其中
所述第一主端子、所述第二主端子和所述第三主端子被布置在所述第一半导体芯片和所述第二半导体芯片的所述布置方向上，并且从所述包封树脂体的所述侧表面突出至所述包封树脂体的所述外部，并且
由具有所述宽度增加的部分的所述端子提供所述第一主端子至所述第三主端子中的在所述布置方向上位于相对端处的两个端子。
8.根据权利要求1至3中任一项所述的半导体器件，其中
所述宽度增加的部分是用于加固所述端子的连接至所述金属构件的所述第一端的加固部分，并且
所述端子的宽度在所述宽度增加的部分中朝着所述金属构件逐渐增加。
CN201610305651.0A 2015-05-11 2016-05-10 半导体器件 Active CN106158839B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015096492A JP6394489B2 (ja) 2015-05-11 2015-05-11 半導体装置
JP2015-096492 2015-05-11

Publications (2)

Publication Number Publication Date
CN106158839A CN106158839A (zh) 2016-11-23
CN106158839B true CN106158839B (zh) 2020-03-03

Family

ID=57208621

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610305651.0A Active CN106158839B (zh) 2015-05-11 2016-05-10 半导体器件

Country Status (4)

Country Link
US (1) US9762140B2 (zh)
JP (1) JP6394489B2 (zh)
CN (1) CN106158839B (zh)
DE (1) DE102016207543B4 (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6221542B2 (ja) * 2013-09-16 2017-11-01 株式会社デンソー 半導体装置
JP6757173B2 (ja) * 2016-04-22 2020-09-16 スタンレー電気株式会社 発光装置
JP6772768B2 (ja) * 2016-11-09 2020-10-21 株式会社デンソー 半導体装置
JP6610568B2 (ja) * 2017-01-16 2019-11-27 株式会社デンソー 半導体装置
JP6512231B2 (ja) * 2017-01-27 2019-05-15 トヨタ自動車株式会社 半導体装置
JP6586970B2 (ja) * 2017-03-09 2019-10-09 トヨタ自動車株式会社 半導体装置
JP2018195694A (ja) * 2017-05-17 2018-12-06 株式会社Ｓｏｋｅｎ 電力変換器
JP6943051B2 (ja) * 2017-07-19 2021-09-29 株式会社デンソー 半導体装置の製造方法
CN107516654A (zh) * 2017-08-01 2017-12-26 广东气派科技有限公司 一种集成电路封装结构
JP7192235B2 (ja) * 2018-02-06 2022-12-20 株式会社デンソー 半導体装置
JP7147187B2 (ja) * 2018-03-06 2022-10-05 株式会社デンソー 半導体装置
CN110870188B (zh) * 2018-06-08 2022-10-28 新电元工业株式会社 半导体模块
JP7077893B2 (ja) * 2018-09-21 2022-05-31 株式会社デンソー 半導体装置
JP6958529B2 (ja) * 2018-10-02 2021-11-02 株式会社デンソー 半導体装置
JP7155990B2 (ja) * 2018-12-17 2022-10-19 株式会社デンソー 半導体モジュール
JP7135930B2 (ja) * 2019-02-20 2022-09-13 株式会社デンソー 半導体モジュールとそれを用いた電力変換装置
JP7103279B2 (ja) * 2019-03-11 2022-07-20 株式会社デンソー 半導体装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102201402A (zh) * 2010-03-23 2011-09-28 三垦电气株式会社 半导体装置
CN103493197A (zh) * 2011-04-19 2014-01-01 丰田自动车株式会社 半导体装置及其制造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5001545A (en) * 1988-09-09 1991-03-19 Motorola, Inc. Formed top contact for non-flat semiconductor devices
AU705177B1 (en) * 1997-11-26 1999-05-20 Kabushiki Kaisha Toshiba Semiconductor device
US6040626A (en) * 1998-09-25 2000-03-21 International Rectifier Corp. Semiconductor package
JP3871486B2 (ja) * 1999-02-17 2007-01-24 株式会社ルネサステクノロジ 半導体装置
US6256200B1 (en) * 1999-05-27 2001-07-03 Allen K. Lam Symmetrical package for semiconductor die
US6703707B1 (en) * 1999-11-24 2004-03-09 Denso Corporation Semiconductor device having radiation structure
US6459147B1 (en) * 2000-03-27 2002-10-01 Amkor Technology, Inc. Attaching semiconductor dies to substrates with conductive straps
JP2002026195A (ja) 2000-07-11 2002-01-25 Fuji Electric Co Ltd 樹脂封止型半導体装置及びその製造方法
US6891256B2 (en) * 2001-10-22 2005-05-10 Fairchild Semiconductor Corporation Thin, thermally enhanced flip chip in a leaded molded package
US20040080028A1 (en) * 2002-09-05 2004-04-29 Kabushiki Kaisha Toshiba Semiconductor device with semiconductor chip mounted in package
JP2006324320A (ja) 2005-05-17 2006-11-30 Renesas Technology Corp 半導体装置
JP4893303B2 (ja) * 2006-12-29 2012-03-07 株式会社デンソー 半導体装置
JP2008198718A (ja) 2007-02-09 2008-08-28 Asmo Co Ltd 樹脂封止型半導体装置
JP2010118712A (ja) 2010-03-04 2010-05-27 Renesas Technology Corp Ｑｆｎパッケージの製造方法
WO2012137760A1 (ja) * 2011-04-04 2012-10-11 ローム株式会社 半導体装置および半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102201402A (zh) * 2010-03-23 2011-09-28 三垦电气株式会社 半导体装置
CN103493197A (zh) * 2011-04-19 2014-01-01 丰田自动车株式会社 半导体装置及其制造方法

Also Published As

Publication number Publication date
JP2016213346A (ja) 2016-12-15
US20160336251A1 (en) 2016-11-17
CN106158839A (zh) 2016-11-23
US9762140B2 (en) 2017-09-12
JP6394489B2 (ja) 2018-09-26
DE102016207543B4 (de) 2023-05-04
DE102016207543A1 (de) 2016-11-17

Similar Documents

Publication Publication Date Title
CN106158839B (zh) 半导体器件
US11270984B2 (en) Semiconductor module
US20160172995A1 (en) Power semiconductor module and power conversion device
US9754863B2 (en) Semiconductor device
JP4988784B2 (ja) パワー半導体装置
US9515061B2 (en) Semiconductor module and semiconductor device
CN105470248B (zh) 半导体器件
US20160315038A1 (en) Semiconductor module
CN107731779B (zh) 电子装置
US11456238B2 (en) Semiconductor device including a semiconductor chip connected with a plurality of main terminals
US11380656B2 (en) Semiconductor device
CN109417066B (zh) 半导体装置
US11398448B2 (en) Semiconductor module
US11456244B2 (en) Semiconductor device
US20170213783A1 (en) Multi-chip semiconductor power package
CN112582356A (zh) 半导体器件
US11996344B2 (en) Semiconductor device
CN109427724B (zh) 具有三端子夹具的晶体管封装
WO2016203743A1 (ja) 半導体装置
US20200211954A1 (en) Semiconductor module
JP7428019B2 (ja) 半導体モジュール
CN111613608A (zh) 用于多芯片功率半导体器件的封装
WO2019150870A1 (ja) 半導体モジュール
US20230282622A1 (en) Semiconductor device
JP2023037354A (ja) 半導体装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant