CN105637643A - 碳化硅半导体装置，碳化硅半导体装置的制造方法以及碳化硅半导体装置的设计方法 - Google Patents

碳化硅半导体装置，碳化硅半导体装置的制造方法以及碳化硅半导体装置的设计方法 Download PDF

Info

Publication number
CN105637643A
CN105637643A CN201480003420.3A CN201480003420A CN105637643A CN 105637643 A CN105637643 A CN 105637643A CN 201480003420 A CN201480003420 A CN 201480003420A CN 105637643 A CN105637643 A CN 105637643A
Authority
CN
China
Prior art keywords
silicon carbide
gate trench
area
unit area
horizontal direction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201480003420.3A
Other languages
English (en)
Other versions
CN105637643B (zh
Inventor
井上徹人
菅井昭彦
中村俊一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Publication of CN105637643A publication Critical patent/CN105637643A/zh
Application granted granted Critical
Publication of CN105637643B publication Critical patent/CN105637643B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

碳化硅半导体装置包括:第一导电型碳化硅层32,第二导电型碳化硅层36,栅极沟槽20,被设置在栅极沟槽20内的栅极电极79,以及直到比栅极沟槽20更深的深度处被形成的保护沟槽10。在水平方向上，包含栅极沟槽20，以及将栅极沟槽20的仅一部分在水平方向上包围的保护沟槽10这两者的区域成为单元(cell)区域，在水平方向上，包含保护沟槽10，且设置有栅极衬垫89或者与该栅极衬垫89相连接的布置电极的区域成为栅极区域。在单元区域中的栅极沟槽20的上方以及栅极区域中设有第二导电构件81，该第二导电构件81被设置为经过单元区域中不设有保护沟槽10的地方的上方，从栅极沟槽20的上方起延展到栅极区域。

Description

碳化硅半导体装置，碳化硅半导体装置的制造方法以及碳化硅半导体装置的设计方法
技术领域
本发明涉及一种使用碳化硅的碳化硅半导体装置，碳化硅半导体装置的制造方法以及碳化硅半导体装置的设计方法。
背景技术
以往，已知使用硅(Silicon)的沟槽(Trench)型Si-MOSFET等的半导体装置。在日本特开平06-132539号公报中，公开一种具有纵型绝缘栅(Gate)型场效应晶体管的半导体装置，包括：第一导电型半导体基板，被设置在该半导体基板主表面的具有低杂质浓度的第一导电型第一半导体层，被设置在该第一半导体层的上表面的第二导电型半导体层，被设置在该第二半导体层的表层部的一部分中的第一导电型第三半导体层，形成在被设为从该第三半导体层的中央部表面穿过第二半导体层的一部分直到第一半导体层的大致呈U字状截面的栅极沟槽的内壁面中的栅极氧化膜，被设为在该栅极氧化膜上将沟填埋的栅极电极，被设为覆盖在该栅极电极上以及第二半导体层的露出表面上的绝缘层，被设置在该绝缘膜上且与栅极电极相接触(Contact)的栅极配线，被设置在绝缘膜上且经由接触孔(ContactHole)从而与第三半导体层相接触的源极(Source)电极，以及被设置在半导体基板背面的漏极(Drain)电极。在该日本特开平06-132539号公报中，公开了将栅极沟槽(GateTrench)设置为环(Ring)状的结构。
然而，在使用碳化硅的Si-MOSFET等的半导体装置中，由于绝缘击穿电压高，在只有栅极沟槽的情况下外加到栅极氧化膜的电场过于集中，导致存在氧化膜损坏的可能性。
因此，在寻求一种在栅极沟槽20的水平方向的整个周围设置保护沟槽(ProtectionTrench)10从而防止电场外加到栅极沟槽20的方法。然而，在采用这样的保护沟槽10的情况下，必须要将从栅极沟槽20的上方通往衬垫(GatePad)的多晶硅(Polysilicon)等的导电构件81的配线设置为穿过保护沟槽10(参照图7)。因此，必须要将氧化物等的绝缘材料埋入保护沟槽10的指定的地方(在图7所示的形态中用“箭头”指出的地方)，且必须使导电构件的配线在该绝缘材料上穿过，导致存在制造工序增加的缺点。
发明内容
鉴于以上情况，本发明提供一种不会特别增加制造工序，且能够以保护沟槽将栅极沟槽的周围包围住从而防止电场外加到栅极沟槽中的碳化硅半导体装置，碳化硅半导体装置的制造方法以及碳化硅半导体装置的设计方法。
本发明的碳化硅半导体装置包括：
第一导电型碳化硅层，
被形成在所述第一导电型碳化硅层上的第二导电型碳化硅层，
被形成在从所述第二导电型碳化硅层的表面直到到达所述第一导电型碳化硅层的深度处的栅极沟槽，
在所述栅极沟槽内经由绝缘膜从而被设置的栅极电极，
被形成在从所述第二导电型碳化硅层的表面直到比所述栅极沟槽更深的深度处的保护沟槽，
以及被设置在所述保护沟槽内的第一导电构件，
在水平方向上，包含所述栅极沟槽，以及将所述栅极沟槽的仅一部分在水平方向上包围的所述保护沟槽这两者的区域成为单元区域，
在水平方向上，包含所述保护沟槽，且设置有栅极衬垫或者与该栅极衬垫相连接的布置电极的区域成为栅极区域，
在所述单元区域的所述栅极沟槽的上方以及所述栅极区域中设有第二导电构件，
所述第二导电构件被设置为经过所述单元区域中不设有所述保护沟槽的地方，从所述单元区域的所述栅极沟槽的上方起延展到所述栅极区域。
在本发明的碳化硅半导体装置中，
被包含在所述单元区域中的所述保护沟槽具有一对在水平方向上直线延伸的所述单元区域直线沟槽和在水平方向上弯曲的单元区域曲线沟槽，
在所述一对单元区域直线沟槽的一端设有所述单元区域曲线沟槽，
在所述一对所述单元区域直线沟槽的水平方向之间设有所述栅极沟槽，
所述第二导电构件被设置为经过所述一对单元区域直线沟槽的另一端侧的上方，从所述单元区域的所述栅极沟槽的上方起延展到所述栅极区域亦可。
在本发明的碳化硅半导体装置中，
所述栅极沟槽在水平方向上直线延伸。
所述栅极沟槽与所述单元区域直线沟槽在水平方向上呈平行延伸亦可。
在本发明的碳化硅半导体装置中，
被包含在所述栅极区域中的所述保护沟槽具有在水平方向上弯曲的栅极区域曲线沟槽，
在所述一对单元区域沟槽的另一端侧设有在水平方向上朝所述栅极沟槽侧突出的所述栅极区域曲线沟槽亦可。
在本发明的碳化硅半导体装置中，
还设有与朝所述栅极沟槽侧突出的所述栅极区域曲线沟槽相邻，且朝该栅极区域曲线沟槽侧突出的所述栅极区域曲线沟槽亦可。
在本发明的碳化硅半导体装置中，
所述保护沟槽不具有在水平方向上的端部亦可。
本发明的碳化硅半导体装置的制造方法包括：
形成第一导电型碳化硅层的工序，
在所述第一导电型碳化硅层上形成第二导电型碳化硅层的工序，
在从所述第二导电型碳化硅层的表面直到到达所述第一导电型碳化硅层的深度处形成栅极沟槽的工序，
在从所述第二导电型碳化硅层的表面直到比所述栅极沟槽更深的深度处形成保护沟槽的工序，
在所述栅极沟槽内经由绝缘膜从而设置栅极电极的工序，
以及在所述保护沟槽内设置第一导电构件的工序，
在水平方向上，由包含所述栅极沟槽，以及将所述栅极沟槽的仅一部分在水平方向上包围的所述保护沟槽这两者的区域成为单元区域，
在水平方向上，由包含所述保护沟槽，且设置有栅极衬垫或者与该栅极衬垫相连接的布置电极的区域成为栅极区域，
在所述单元区域的所述栅极沟槽的一部分的上方以及所述栅极区域中设置第二导电构件，
将所述第二导电构件设置为经过所述单元区域中不设有所述保护沟槽的地方，从所述单元区域的所述栅极沟槽的上方起延展到所述栅极区域。
在本发明的碳化硅半导体装置的设计方法中，
所述碳化硅半导体装置包括：
第一导电型碳化硅层，
被形成在所述第一导电型碳化硅层上的第二导电型碳化硅层，
被形成在从所述第二导电型碳化硅层的表面直到到达所述第一导电型碳化硅层的深度处的栅极沟槽，
在所述栅极沟槽内被设置为经由绝缘膜的栅极电极，
被形成在从所述第二导电型碳化硅层的表面直到比所述栅极沟槽更深的深度处的保护沟槽，
以及被设置在所述保护沟槽内的第一导电构件，
在水平方向上，包含所述栅极沟槽，以及将所述栅极沟槽的仅一部分在水平方向上包围的所述保护沟槽这两者的区域成为单元区域，
在水平方向上，包含所述保护沟槽，且设置有栅极衬垫或者与该栅极衬垫相连接的布置电极的区域成为栅极区域，
在所述单元区域的所述栅极沟槽的上方以及所述栅极区域中设置第二导电构件，
所述第二导电构件被设计为经过所述单元区域中不设有所述保护沟槽的地方，从所述单元区域的所述栅极沟槽的上方起延展到所述栅极区域。
【发明效果】
根据本发明，第二导电构件被设置为经过没有被所述单元区域的保护沟槽包围的地方，从单元区域的栅极沟槽的上方起延展到栅极区域。因此，本发明不需要将氧化物等的绝缘材料埋入保护沟槽内，不会特别增加制造工序，且能够以保护沟槽将栅极沟槽的周围包围住从而防止电场外加到栅极沟槽中。
【简单附图说明】
【图1】图1是本发明的实施方式涉及的碳化硅半导体装置的截面图，且是将图3的一部分沿上下方向切断的截面图。
【图2】图2是本发明的实施方式涉及的碳化硅半导体装置的截面图，且是将图3的一部分沿左右方向切断的截面图。
【图3】图3是将本发明的实施方式涉及的碳化硅半导体装置的一部分扩大的上方平面图，且是显示相当于图4的A处的上方平面图。
【图4】图4是用于显示本发明的实施方式涉及的碳化硅半导体装置的单元区域以及栅极区域的概略上方平面图。
【图5】图5是用于显示本发明的实施方式涉及的碳化硅半导体装置中的第二导电构件的设置情况的概略上方平面图。
【图6】图6是用于说明本发明的实施方式涉及的碳化硅半导体装置的制造方法的截面图，且是与图1相对应的截面图。
【图7】图7是用于显示以保护沟槽将栅极沟槽在水平方向上的整个周围包围住的形态的概略上方平面图。
发明实施方式
第一实施方式
《结构》
以下，将参照附图关于碳化硅半导体装置，碳化硅半导体装置的制造方法以及碳化硅半导体装置的设计方法的实施方式进行说明。
本实施方式的碳化硅半导体装置例如是沟槽结构型MOSFET。以下，将使用沟槽结构型MOSFET作为碳化硅半导体装置进行说明，但该沟槽结构型MOSFET仅是碳化硅半导体装置的一个示例，还能够适用于具有绝缘栅双极型晶体管(BipolarTransistor)(IGBT)等的MOS栅极的其他装置结构。
如图1所示，本实施方式的碳化硅半导体装置包括：高浓度n型碳化硅半导体基板(第一导电型碳化硅半导体基板)31，被形成在高浓度n型碳化硅半导体基板31上的低浓度n型碳化硅层(第一导电型碳化硅层)32，以及被形成在低浓度n型碳化硅层32上的p型碳化硅层(第二导电型碳化硅层)36。另外，在p型碳化硅层36表面的一部分区域设有含有高浓度杂质的n型碳化硅区域37。
在本实施方式中，在从含有高浓度杂质的n型碳化硅区域37的表面穿过p型碳化硅层36直到低浓度n型碳化硅层32的深度处，形成栅极沟槽20。另外，在该栅极沟槽20内经由栅极绝缘膜75a从而设置栅极电极79。另外，在栅极电极79的上方设有层间绝缘膜75b。因此，栅极电极79被栅极绝缘膜75a以及层间绝缘膜75b包围从而被设置。
另外，从p型碳化硅层36的表面直到比栅极沟槽20更深的深度处，形成有保护沟槽10。在该护沟槽10内，设有例如由多晶硅(Polysilicon)构成的第一导电构件61。另外，在本实施方式中，该第一导电构件61与源极电极69为一体，在外加电压时，变为相同电位(参照图1)。另外，在保护沟槽10的侧壁形成有侧壁绝缘膜65。
另外，在本实施方式中，在保护沟槽10的底部，设有通过铝(Aluminium)等的离子(Ion)注入从而被形成的高浓度p型半导体区域33。另外，在n型碳化硅半导体基板31的背面侧(图1的下表面侧)，设有漏极电极39。
如图4所示，在本实施方式中，在水平方向上，包含栅极沟槽20，以及在水平方向上以开口的状态将栅极沟槽20的仅一部分包围的保护沟槽10这两者的区域成为“单元(cell)区域”。另外，图4仅为用于显示本实施方式涉及的碳化硅半导体装置的单元区域以及栅极区域的概略上方平面图。因此，在图4中，没有显示保护沟槽10的细微结构，也没有考虑在水平方向上保护沟槽10之间的距离。另外，图4中所示的在水平方向上单元区域以及栅极区域的大小没有特殊含义。
另外，如图4所示，在本实施方式中，在水平方向上，包含保护沟槽10，且设置有栅极衬垫89(参照图2)或者与该栅极衬垫89相连接的布置电极的区域成为“栅极区域”。另外，第二导电构件81的材料例如是多晶硅。
在如图4中央部所示的栅极区域中设置有栅极衬垫89(参照图2)，布置电极与该栅极衬垫89相连接。另外，如图5所示，第二导电构件81主要被设置在位于单元区域的保护沟槽10的上方以往的地方。
如图3所示，被包含在本实施方式中的栅极区域中的保护沟槽10具有：在水平方向上直线延伸的栅极区域直线沟槽16，和在水平方向上弯曲的栅极区域曲线沟槽17。另外，符号“17”为包含后述的符号“17a”以及符号“17b”的概念。另外，p型半导体区域33和第一导电构件61形成欧姆接触(OhmicContact)，在外加电压时变为相同电位。
本实施方式的栅极沟槽20在水平方向上直线延伸，更具体而言，在图3中在左右方向上呈直线状延伸。而且，栅极沟槽20与单元区域直线沟槽11在水平方向上呈平行(图3的左右方向)地延伸。
如图3所示，被包含在单元区域中的保护沟槽10具有一对在水平方向上直线延伸的单元区域直线沟槽11，和在水平方向上弯曲的单元区域曲线沟槽12。而且，在一对单元区域直线沟槽11之间设有在水平方向上直线延伸的(在图3的左右方向上延伸)栅极沟槽20，在一对单元区域直线沟槽11的一端设有单元区域曲线沟槽12，在一对单元区域直线沟槽11的另一端不形成保护沟槽10。于是，保护沟槽10在水平方向上将栅极沟槽20的“仅一部分”包围。另外，在本实施方式中，在水平方方向上单元区域的保护沟槽10呈连续的“S字形状”，一对单元区域直线沟槽11的“另一端”的位置在图3中的上下方向上依次进行左右反转。因此，便能够同时满足保护沟槽10在水平方向上将栅极沟槽20的“仅一部分”包围，和在保护沟槽10中不形成水平方向的端部这两个条件。
如图2所示，在单元区域中的栅极沟槽20的一部分的上方以及栅极区域中，设有第二导电构件81。第二导电构件81被设置为经过单元区域中不设有保护沟槽10的地方和在本实施方式中的一对单元区域直线沟槽11的另一端侧，从栅极沟槽20的上方起延展到栅极区域(参照图5)。于是，第二导电构件81被设置为经过一对单元区域直线沟槽11的另一端的上方，从栅极电极79的上方延展到栅极衬垫89的下方。另外，如图2所示，该栅极衬垫89被设置为在栅极区域的保护沟槽10上经由SiO2等的绝缘层85以及第二导电构件81。从图2明显可知，第二导电构件81与栅极电极79电连接。
另外，如图3所示，在一对单元区域直线沟槽11的另一端侧设有在水平方向上朝栅极沟槽20侧突出的栅极区域曲线沟槽17a。另外，还设有与这样地朝栅极沟槽20侧突出的栅极区域曲线沟槽17a相邻接，且朝该栅极区域曲线沟槽17a侧突出的栅极区域曲线沟槽17b。
另外，如图4所示，在本实施方式中，设有将栅极区域以及单元区域在水平方向上包围的保护环80。另外，在图4中，只显示一个保护环80，而实际上设置多个保护环80呈同心圆状亦可。
另外，如图4所示，本实施方式的各个保护沟槽10在平面上看具有由一笔画成的水平方向的端部。
《制造工序》
接着，将主要使用图6对包含上述结构的本实施方式的碳化硅半导体装置的制造工序进行说明。另外，在本实施方式中，还包含如以下这样被制造的碳化硅半导体装置的设计方法。
首先，准备高浓度n型碳化硅半导体基板31(参照图6(a))。
接着，在高浓度n型碳化硅半导体基板31上通过外延(Epitaxial)生长从而形成低浓度n型碳化硅层32。
然后，在低浓度n型碳化硅层32上通过外延(Epitaxial)生长或者离子(Ion)注入从而形成p型碳化硅层36。
然后，通过在p型碳化硅层36中的栅极沟槽20的预定形成处的近旁将磷等进行离子注入，从而形成含有高浓度杂质的n型碳化硅区域37。之后，将保护层91形成薄膜，并将该保护层91图形化(Patterning)，从而形成由于形成保护沟槽10的开口(参照图6(b))。接着，将该保护层91作为掩膜(Mask)，从p型碳化硅层36的表面直到到达低浓度n型碳化硅层32的深度处形成保护沟槽10。
接着，形成将保护层91以及保护沟槽10覆盖的保护膜92(参照图6(c))。
接着，仅将保护膜92中保护沟槽10的底部去除，将残留的保护膜92作为掩膜，通过在保护沟槽10的底部将铝(Aluminium)等进行离子注入从而形成含有高浓度杂质的p型半导体区域33。之后，将保护膜92以及保护层91去除。之后，实施活性化退火(Anneal)处理。
之后，将保护层93形成薄膜，并将该保护层93图形化(Patterning)，从而形成由于形成栅极沟槽20的开口(参照图6(d))。接着，将该保护层93作为掩膜(Mask)，从p型碳化硅层36的表面直到到达低浓度n型碳化硅层32的深度处形成栅极沟槽20。另外，该栅极沟槽20的深度比保护沟槽10的深度浅。之后，将保护层93去除。
接着，在含有栅极沟槽20以及保护沟槽10的碳化硅半导体装置的表面实施热处理，形成作为栅极绝缘膜75a以及侧壁绝缘膜65的氧化膜。之后，在该栅极绝缘膜75a上将多晶硅等的导电构件形成薄膜。该成膜之后，根据需要实施热处理亦可。通过这样，便如图6(e)所示那样在栅极沟槽20上形成栅极电极79以及第二导电构件81。
接着，通过采用等离子(Plasma)CVD等形成由二氧化硅(SiO2)等构成的绝缘膜使得将含有保护沟槽10的碳化硅半导体装置的表面覆盖，从而在栅极电极79上形成层间绝缘膜75，且栅极电极79被栅极绝缘膜75a和层间绝缘膜75b包围(参照图6(f))。另外，保护沟槽10底部的绝缘膜通过选择性地蚀刻(Etching)被去除，仅残留保护沟槽10侧壁的侧壁绝缘膜65。
之后，通过适当地设置第一导电构件61，绝缘层85，第二导电构件81，栅极衬垫89，源极电极69，漏极电极39，布置电极等，从而制造本实施方式的碳化硅半导体装置(参照图1以及图2)。
另外，这样被制造的碳化硅半导体装置的保护沟槽10的水平面内的设置将在“结构”处陈述。另外，上述制造方法仅仅为一个示例，无论哪种制造方法，只要能够制造专利权利要求范围中所记载的碳化硅半导体装置就可以采用。
《作用·效果》
接着，将关于本实施方式涉及的作用·效果进行说明。
根据本实施方式，第二导电构件81被设置为经过没有被所述单元区域的保护沟槽10包围的地方，从单元区域的栅极沟槽20的上方起延展到栅极区域。因此，本发明不需要将氧化物等的绝缘材料埋入保护沟槽内，不会特别增加制造工序，且能够以保护沟槽10将栅极沟槽20的周围包围住从而防止电场外加到栅极沟槽中。
即，从前，必须要将从栅极沟槽20的上方通往衬垫(GatePad)的多晶硅(Polysilicon)等的导电构件的配线设置为穿过保护沟槽10(参照图7)。因此，必须要将氧化物等的绝缘材料埋入保护沟槽10的指定的地方(在图7所示的形态中用“箭头”指出的地方)，且必须使导电构件的配线在该绝缘材料上穿过，导致存在制造工序增加的缺点。
与此相对，根据本实施方式，第二导电构件81被设置为经过没有被所述单元区域的保护沟槽10包围的地方，更具体而言是经过单元区域中不设有保护沟槽10的地方和在本实施方式中的一对单元区域直线沟槽11的另一端侧的上方，从栅极电极79的上方延展到栅极衬垫89的下方(参照图2以及图5)。因此，在本实施方式中，不需要向从前那样必须将氧化物等的绝缘材料埋入保护沟槽中，因此，便能够相较于从前技术减少制造工序。
另外，在本实施方式中，在水平方方向上单元区域的保护沟槽10呈连续的“S字形状”，一对单元区域直线沟槽11的“另一端”的位置在图3中的上下方向上依次进行左右反转。因此，便能够同时满足保护沟槽10在水平方向上将栅极沟槽20的“仅一部分”包围，和在保护沟槽10中不形成水平方向的端部这两个条件。
另外，当在保护沟槽10中形成水平方向的起点或者终点时，会在该端部形成棱角部分。而且，一旦形成这样的棱角部分，便会导致在该部分引起电场集中的可能性。与此相对，根据本实施方式，保护沟槽10在水平方向上(在平面角度上)呈一笔画成，在水平方向上没有形成起点或终点。
因此，根据本实施方式，能够达成相较于从前技术减少制造工序的效果，还能够达成防止电场在保护沟槽10的端部过于集中的效果。
另外，根据本实施方式，被包含在栅极区域中的保护沟槽10具有在水平方向上弯曲的栅极区域曲线沟槽17。并且，在一对单元区域直线沟槽11的另一端侧设有在水平方向上朝栅极沟槽20侧突出的栅极区域曲线沟槽17a。因此，能够防止被包含在单元区域中的保护沟槽10与栅极区域曲线沟槽17之间的水平方向距离变长，便能够达成相较于从前技术减少制造工序的效果。
关于该点进行说明。
通常保护沟槽10之间的水平方向距离越长，外加到保护沟槽10中的电场就越大。然而，由于当像本实施方式这样在一对单元区域直线沟槽11的另一端不形成单元区域曲线沟槽12时，向栅极区域侧突出的保护沟槽10便不存在，因此在该另一端侧中，被包含在单元区域的保护沟槽10与被包含在栅极区域的保护沟槽10的水平方向距离趋于边长。
这一点，根据本实施方式，被包含在栅极区域中的保护沟槽10具有在水平方向上朝栅极沟槽20侧突出的栅极区域曲线沟槽17。因此，能够将被包含在单元区域中的保护沟槽10与栅极区域曲线沟槽17之间的水平方向距离缩短。因此，在满足保护沟槽10在水平方向上将栅极沟槽20的“仅一部分”包围的条件下，在偏压时，能够减小在被包含在单元区域中的保护沟槽10与栅极区域曲线沟槽17之间产生的电场，便能够防止在该区域中局部电场过于集中的情况。
另外，在本实施方式中，还设有与朝栅极沟槽20侧突出的栅极区域曲线沟槽17a相邻接，且朝该栅极区域曲线沟槽17a侧突出的栅极区域曲线沟槽17b。因此，能够将朝栅极沟槽20侧突出的栅极区域曲线沟槽17a与朝该栅极区域曲线沟槽17a侧突出的栅极区域曲线沟槽17b之间的水平方向距离缩短。因此，在偏压时，能够减小在栅极区域曲线沟槽17之间产生的电场，便能够防止在该区域中局部电场过于集中的情况。
另外，在本实施方式中的“水平方向距离”代表在水平方向上的“最短长度”的意思。当列举单元区域直线沟槽11进行说明时，从某个单元区域直线沟槽11的一点起，相对于对向的单元区域直线沟槽11的长度有无数个，如图3所示，除了D1之外还能够列举D1'或者D1”等。这一点，如上所述，由于将本实施方式中的“水平方向距离”定义为在水平方向上的“最短长度”，因此“水平方向距离”不是D1'或者D1”，而是D1。
变形例
另外，在本实施方式中，采用单元区域曲线沟槽12的曲率半径越小，与邻接于该单元区域曲线沟槽12的栅极区域的保护沟槽10的水平方向距离就越小的形态亦可。
像这样在采用单元区域曲线沟槽12的曲率半径越小，与邻接于该单元区域曲线沟槽12的栅极区域的保护沟槽10的水平方向距离就越小的形态的情况下，在偏压时，能够防止在单元区域曲线沟槽12的曲率半径小的地方局部电场过于集中的情况。
另外，同样地，采用栅极区域曲线沟槽17的曲率半径越小，与邻接于该栅极区域曲线沟槽17的栅极区域的保护沟槽10的水平方向距离就越小的形态亦可。
像这样地在采用栅极区域曲线沟槽17的曲率半径越小，与邻接于该栅极区域曲线沟槽17的栅极区域的保护沟槽10的水平方向距离就越小的形态的情况下，在偏压时，能够防止在栅极区域曲线沟槽17的曲率半径小的地方局部电场过于集中的情况。
最后，上述实施方式的记载，变形例以及附图的公开只是用于对专利权利要求范围中所记载的发明进行说明的一个示例，并不仅限于被记载于上述实施方式的记载，变形例以及附图所公开的发明。
符号说明
10保护沟槽
11单元区域直线沟槽
12单元区域曲线沟槽
16栅极区域直线沟槽
16a栅极区域直线沟槽
1b6栅极区域直线沟槽
17栅极区域曲线沟槽
17a栅极区域曲线沟槽
17b栅极区域曲线沟槽
20栅极沟槽
31n型碳化硅半导体基板(第一导电型碳化硅半导体基板)
32n型碳化硅层(第一导电型碳化硅层)
36p型碳化硅层(第二导电型碳化硅层)
61第一导电构件(导电构件)
69源极电极
79栅极电极
80保护环

Claims (8)

1.一种碳化硅半导体装置，其特征在于，包括：
第一导电型碳化硅层，
被形成在所述第一导电型碳化硅层上的第二导电型碳化硅层，
被形成在从所述第二导电型碳化硅层的表面直到到达所述第一导电型碳化硅层的深度处的栅极沟槽，
在所述栅极沟槽内经由绝缘膜从而被设置的栅极电极，
被形成在从所述第二导电型碳化硅层的表面直到比所述栅极沟槽更深的深度处的保护沟槽，以及
被设置在所述保护沟槽内的第一导电构件，
其中，在水平方向上，包含所述栅极沟槽，以及将所述栅极沟槽的仅一部分在水平方向上包围的所述保护沟槽这两者的区域成为单元区域，
在水平方向上，包含所述保护沟槽，且设置有栅极衬垫或者与该栅极衬垫相连接的布置电极的区域成为栅极区域，
在所述单元区域的所述栅极沟槽的上方以及所述栅极区域中设有第二导电构件，
所述第二导电构件被设置为经过所述单元区域中不设有所述保护沟槽的地方，从所述单元区域的所述栅极沟槽的上方起延展到所述栅极区域。
2.根据权利要求1所述的碳化硅半导体装置，其特征在于：
其中，被包含在所述单元区域中的所述保护沟槽具有一对在水平方向上直线延伸的所述单元区域直线沟槽和在水平方向上弯曲的单元区域曲线沟槽，
在所述一对单元区域直线沟槽的一端设有所述单元区域曲线沟槽，
在所述一对所述单元区域直线沟槽的水平方向之间设有所述栅极沟槽，
所述第二导电构件被设置为经过所述一对单元区域直线沟槽的另一端侧的上方，从所述单元区域的所述栅极沟槽的上方起延展到所述栅极区域。
3.根据权利要求2所述的碳化硅半导体装置，其特征在于：
其中，所述栅极沟槽在水平方向上直线延伸，
所述栅极沟槽与所述单元区域直线沟槽在水平方向上呈平行延伸。
4.根据权利要求2或3中任意一项所述的碳化硅半导体装置，其特征在于：
其中，被包含在所述栅极区域中的所述保护沟槽具有在水平方向上弯曲的栅极区域曲线沟槽，
在所述一对单元区域沟槽的另一端侧设有在水平方向上朝所述栅极沟槽侧突出的所述栅极区域曲线沟槽。
5.根据权利要求4所述的碳化硅半导体装置，其特征在于：
其中，设有与朝所述栅极沟槽侧突出的所述栅极区域曲线沟槽相邻，且朝该栅极区域曲线沟槽侧突出的所述栅极区域曲线沟槽。
6.根据权利要求1～5中任意一项所述的碳化硅半导体装置，其特征在于：
其中，所述保护沟槽在水平方向上呈一笔画成。
7.一种碳化硅半导体装置的制造方法，其特征在于，包括：
形成第一导电型碳化硅层的工序，
在所述第一导电型碳化硅层上形成第二导电型碳化硅层的工序，
在从所述第二导电型碳化硅层的表面直到到达所述第一导电型碳化硅层的深度处形成栅极沟槽的工序，
在从所述第二导电型碳化硅层的表面直到比所述栅极沟槽更深的深度处形成保护沟槽的工序，
在所述栅极沟槽内经由绝缘膜从而设置栅极电极的工序，以及
在所述保护沟槽内设置第一导电构件的工序，
其中，在水平方向上，由包含所述栅极沟槽，以及将所述栅极沟槽的仅一部分在水平方向上包围的所述保护沟槽这两者的区域成为单元区域，
在水平方向上，由包含所述保护沟槽，且设置有栅极衬垫或者与该栅极衬垫相连接的布置电极的区域成为栅极区域，
在所述单元区域的所述栅极沟槽的一部分的上方以及所述栅极区域中设置第二导电构件，
将所述第二导电构件设置为经过所述单元区域中不设有所述保护沟槽的地方，从所述单元区域的所述栅极沟槽的上方起延展到所述栅极区域。
8.一种碳化硅半导体装置的设计方法，其特征在于：
其中，所述碳化硅半导体装置具有：
第一导电型碳化硅层，
被形成在所述第一导电型碳化硅层上的第二导电型碳化硅层，
被形成在从所述第二导电型碳化硅层的表面直到到达所述第一导电型碳化硅层的深度处的栅极沟槽，
在所述栅极沟槽内被设置为经由绝缘膜的栅极电极，
被形成在从所述第二导电型碳化硅层的表面直到比所述栅极沟槽更深的深度处的保护沟槽，以及
被设置在所述保护沟槽内的第一导电构件，
在水平方向上，包含所述栅极沟槽，以及将所述栅极沟槽的仅一部分在水平方向上包围的所述保护沟槽这两者的区域成为单元区域，
在水平方向上，包含所述保护沟槽，且设置有栅极衬垫或者与该栅极衬垫相连接的布置电极的区域成为栅极区域，
在所述单元区域的所述栅极沟槽的上方以及所述栅极区域中设置第二导电构件，
所述第二导电构件被设计为经过所述单元区域中不设有所述保护沟槽的地方，从所述单元区域的所述栅极沟槽的上方起延展到所述栅极区域。
CN201480003420.3A 2014-09-24 2014-09-24 碳化硅半导体装置，碳化硅半导体装置的制造方法以及碳化硅半导体装置的设计方法 Active CN105637643B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2014/075193 WO2016046901A1 (ja) 2014-09-24 2014-09-24 炭化ケイ素半導体装置、炭化ケイ素半導体装置の製造方法及び炭化ケイ素半導体装置の設計方法

Publications (2)

Publication Number Publication Date
CN105637643A true CN105637643A (zh) 2016-06-01
CN105637643B CN105637643B (zh) 2018-10-09

Family

ID=54874343

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480003420.3A Active CN105637643B (zh) 2014-09-24 2014-09-24 碳化硅半导体装置，碳化硅半导体装置的制造方法以及碳化硅半导体装置的设计方法

Country Status (6)

Country Link
US (1) US9640618B2 (zh)
EP (1) EP3200236B1 (zh)
JP (1) JP5833274B1 (zh)
CN (1) CN105637643B (zh)
TW (1) TWI574405B (zh)
WO (1) WO2016046901A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105637644B (zh) * 2014-09-24 2018-10-09 新电元工业株式会社 碳化硅半导体装置，碳化硅半导体装置的制造方法以及碳化硅半导体装置的设计方法
JP2019165182A (ja) * 2018-03-20 2019-09-26 株式会社東芝 半導体装置
WO2024055049A2 (en) * 2022-09-09 2024-03-14 Semiconductor Components Industries, Llc Termination structures for mosfets

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3167457B2 (ja) 1992-10-22 2001-05-21 株式会社東芝 半導体装置
JP4363736B2 (ja) * 2000-03-01 2009-11-11 新電元工業株式会社 トランジスタ及びその製造方法
US7786533B2 (en) * 2001-09-07 2010-08-31 Power Integrations, Inc. High-voltage vertical transistor with edge termination structure
JP3689420B1 (ja) * 2004-03-29 2005-08-31 新電元工業株式会社 半導体装置
DE112005001434B4 (de) * 2004-06-25 2018-06-07 International Rectifier Corporation MOS-gatterverknüpftes Leistungshalbleiter-Bauelement mit Source-Feldelektrode
JP5617175B2 (ja) * 2008-04-17 2014-11-05 富士電機株式会社 ワイドバンドギャップ半導体装置とその製造方法
US8304829B2 (en) * 2008-12-08 2012-11-06 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
JP2012164851A (ja) * 2011-02-08 2012-08-30 Toyota Motor Corp 半導体装置
JP5667926B2 (ja) * 2011-05-12 2015-02-12 新電元工業株式会社 半導体素子
JP5767857B2 (ja) 2011-05-20 2015-08-19 新電元工業株式会社 トレンチ型ｍｏｓｆｅｔ及びその製造方法
US9443972B2 (en) * 2011-11-30 2016-09-13 Infineon Technologies Austria Ag Semiconductor device with field electrode
US9105744B2 (en) * 2012-03-01 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices having inactive fin field effect transistor (FinFET) structures and manufacturing and design methods thereof
CN105637644B (zh) 2014-09-24 2018-10-09 新电元工业株式会社 碳化硅半导体装置，碳化硅半导体装置的制造方法以及碳化硅半导体装置的设计方法
KR102293874B1 (ko) 2014-12-10 2021-08-25 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조 방법

Also Published As

Publication number Publication date
US20160254356A1 (en) 2016-09-01
EP3200236A4 (en) 2018-05-23
JP5833274B1 (ja) 2015-12-16
EP3200236A1 (en) 2017-08-02
WO2016046901A1 (ja) 2016-03-31
EP3200236B1 (en) 2021-05-05
CN105637643B (zh) 2018-10-09
US9640618B2 (en) 2017-05-02
TW201613092A (en) 2016-04-01
TWI574405B (zh) 2017-03-11
JPWO2016046901A1 (ja) 2017-04-27

Similar Documents

Publication Publication Date Title
US11257944B2 (en) Semiconductor device and semiconductor device manufacturing method
US8415711B2 (en) Semiconductor device and method for manufacturing the same
JP5849882B2 (ja) 縦型半導体素子を備えた半導体装置
US7332770B2 (en) Semiconductor device
CN105637644A (zh) 碳化硅半导体装置，碳化硅半导体装置的制造方法以及碳化硅半导体装置的设计方法
JP6600475B2 (ja) 半導体装置
US7601596B2 (en) Semiconductor device with trench transistors and method for manufacturing such a device
TW201801318A (zh) 半導體裝置及半導體裝置之製造方法
KR20100111906A (ko) 반도체 장치
JP2009088199A (ja) 半導体装置
CN113826213A (zh) 碳化硅半导体装置及其制造方法
CN105637643A (zh) 碳化硅半导体装置，碳化硅半导体装置的制造方法以及碳化硅半导体装置的设计方法
US9324800B1 (en) Bidirectional MOSFET with suppressed bipolar snapback and method of manufacture
JP2009141185A (ja) 半導体装置及びその製造方法
JP6438247B2 (ja) 横型半導体装置
CN105374854B (zh) 半导体装置以及半导体装置的制造方法
US9006824B2 (en) Power semiconductor device with reduced on-resistance and increased breakdown voltage
JP2024003808A (ja) 半導体装置およびその製造方法
TWI582939B (zh) 半導體結構
JP2005286059A (ja) 半導体装置
JP2006041154A (ja) 横型ｍｏｓトランジスタ

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant