TWI574405B - Silicon carbide semiconductor device, method for manufacturing silicon carbide semiconductor device, and design method of silicon carbide semiconductor device - Google Patents

Silicon carbide semiconductor device, method for manufacturing silicon carbide semiconductor device, and design method of silicon carbide semiconductor device Download PDF

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TWI574405B
TWI574405B TW104127540A TW104127540A TWI574405B TW I574405 B TWI574405 B TW I574405B TW 104127540 A TW104127540 A TW 104127540A TW 104127540 A TW104127540 A TW 104127540A TW I574405 B TWI574405 B TW I574405B
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gate
trench
region
tantalum carbide
protective
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TW104127540A
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TW201613092A (en
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Tetsuto Inoue
Akihiko Sugai
Shunichi Nakamura
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Shindengen Electric Manufacturing Co Ltd
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    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
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Description

碳化矽半導體裝置，碳化矽半導體裝置的製造方法以及碳化矽半導體裝置的設計方法
本發明涉及一種使用碳化矽的碳化矽半導體裝置，碳化矽半導體裝置的製造方法以及碳化矽半導體裝置的設計方法。
以往，已知使用矽（Silicon）的溝槽（Trench）型Si-MOSFET 等的半導體裝置。在日本特開平06-132539 號公報中，公開一種具有縱型絕緣柵（Gate）型場效應電晶體的半導體裝置，包括：第一導電型半導體基板，被設置在該半導體基板主表面的具有低雜質濃度的第一導電型第一半導體層，被設置在該第一半導體層的上表面的第二導電型半導體層，被設置在該第二半導體層的表層部的一部分中的第一導電型第三半導體層，形成在被設為從該第三半導體層的中央部表面穿過第二半導體層的一部分直到第一半導體層的大致呈U字狀截面的柵極溝槽的內壁面中的柵極氧化膜，被設為在該柵極氧化膜上將溝填埋的柵極電極，被設為覆蓋在該柵極電極上以及第二半導體層的露出表面上的絕緣層，被設置在該絕緣膜上且與柵極電極相接觸（Contact）的柵極配線，被設置在絕緣膜上且經由接觸孔（Contact Hole）從而與第三半導體層相接觸的源極（Source）電極，以及被設置在半導體基板背面的漏極（Drain）電極。在該日本特開平06-132539 號公報中，公開了將柵極溝槽（Gate Trench）設置為環（Ring）狀的結構。
然而，在使用碳化矽的Si-MOSFET等的半導體裝置中，由於絕緣擊穿電壓高，在只有柵極溝槽的情況下外加到柵極氧化膜的電場過於集中，導致存在氧化膜損壞的可能性。
因此，在尋求一種在柵極溝槽20的水準方向的整個周圍設置保護溝槽（Protection Trench）10從而防止電場外加到柵極溝槽20的方法。然而，在採用這樣的保護溝槽10的情況下，必須要將從柵極溝槽20的上方通往襯墊（Gate Pad）的多晶矽（Polysilicon）等的導電構件81的配線設置為穿過保護溝槽10（參照圖7）。因此，必須要將氧化物等的絕緣材料埋入保護溝槽10的指定的地方（在圖7所示的形態中用“箭頭”指出的地方），且必須使導電構件的配線在該絕緣材料上穿過，導致存在製造工序增加的缺點。
鑒於以上情況，本發明提供一種不會特別增加製造工序，且能夠以保護溝槽將柵極溝槽的周圍包圍住從而防止電場外加到柵極溝槽中的碳化矽半導體裝置，碳化矽半導體裝置的製造方法以及碳化矽半導體裝置的設計方法。
本發明的碳化矽半導體裝置包括： 　第一導電型碳化矽層， 　被形成在所述第一導電型碳化矽層上的第二導電型碳化矽層， 　被形成在從所述第二導電型碳化矽層的表面直到到達所述第一導電型碳化矽層的深度處的柵極溝槽， 　在所述柵極溝槽內經由絕緣膜從而被設置的柵極電極， 　被形成在從所述第二導電型碳化矽層的表面直到比所述柵極溝槽更深的深度處的保護溝槽， 　以及被設置在所述保護溝槽內的第一導電構件， 　在水準方向上，包含所述柵極溝槽，以及將所述柵極溝槽的僅一部分在水準方向上包圍的所述保護溝槽這兩者的區域成為單元區域， 　在水準方向上，包含所述保護溝槽，且設置有柵極襯墊或者與該柵極襯墊相連接的佈置電極的區域成為柵極區域， 　在所述單元區域的所述柵極溝槽的上方以及所述柵極區域中設有第二導電構件， 　所述第二導電構件被設置為經過所述單元區域中不設有所述保護溝槽的地方，從所述單元區域的所述柵極溝槽的上方起延展到所述柵極區域。
在本發明的碳化矽半導體裝置中， 　被包含在所述單元區域中的所述保護溝槽具有一對在水準方向上直線延伸的所述單元區域直線溝槽和在水準方向上彎曲的單元區域曲線溝槽， 　在所述一對單元區域直線溝槽的一端設有所述單元區域曲線溝槽， 　在所述一對所述單元區域直線溝槽的水準方向之間設有所述柵極溝槽， 　所述第二導電構件被設置為經過所述一對單元區域直線溝槽的另一端側的上方，從所述單元區域的所述柵極溝槽的上方起延展到所述柵極區域亦可。
在本發明的碳化矽半導體裝置中， 　所述柵極溝槽在水準方向上直線延伸。 　所述柵極溝槽與所述單元區域直線溝槽在水準方向上呈平行延伸亦可。
在本發明的碳化矽半導體裝置中， 　被包含在所述柵極區域中的所述保護溝槽具有在水準方向上彎曲的柵極區域曲線溝槽， 　在所述一對單元區域溝槽的另一端側設有在水準方向上朝所述柵極溝槽側突出的所述柵極區域曲線溝槽亦可。
在本發明的碳化矽半導體裝置中， 　還設有與朝所述柵極溝槽側突出的所述柵極區域曲線溝槽相鄰，且朝該柵極區域曲線溝槽側突出的所述柵極區域曲線溝槽亦可。
在本發明的碳化矽半導體裝置中， 　所述保護溝槽不具有在水準方向上的端部亦可。
本發明的碳化矽半導體裝置的製造方法包括： 　形成第一導電型碳化矽層的工序， 　在所述第一導電型碳化矽層上形成第二導電型碳化矽層的工序， 　在從所述第二導電型碳化矽層的表面直到到達所述第一導電型碳化矽層的深度處形成柵極溝槽的工序， 　在從所述第二導電型碳化矽層的表面直到比所述柵極溝槽更深的深度處形成保護溝槽的工序， 　在所述柵極溝槽內經由絕緣膜從而設置柵極電極的工序， 　以及在所述保護溝槽內設置第一導電構件的工序， 　在水準方向上，由包含所述柵極溝槽，以及將所述柵極溝槽的僅一部分在水準方向上包圍的所述保護溝槽這兩者的區域成為單元區域， 　在水準方向上，由包含所述保護溝槽，且設置有柵極襯墊或者與該柵極襯墊相連接的佈置電極的區域成為柵極區域， 　在所述單元區域的所述柵極溝槽的一部分的上方以及所述柵極區域中設置第二導電構件， 　將所述第二導電構件設置為經過所述單元區域中不設有所述保護溝槽的地方，從所述單元區域的所述柵極溝槽的上方起延展到所述柵極區域。
在本發明的碳化矽半導體裝置的設計方法中， 　所述碳化矽半導體裝置包括： 　第一導電型碳化矽層， 　被形成在所述第一導電型碳化矽層上的第二導電型碳化矽層， 　被形成在從所述第二導電型碳化矽層的表面直到到達所述第一導電型碳化矽層的深度處的柵極溝槽， 　在所述柵極溝槽內被設置為經由絕緣膜的柵極電極， 　被形成在從所述第二導電型碳化矽層的表面直到比所述柵極溝槽更深的深度處的保護溝槽， 　以及被設置在所述保護溝槽內的第一導電構件， 　在水準方向上，包含所述柵極溝槽，以及將所述柵極溝槽的僅一部分在水準方向上包圍的所述保護溝槽這兩者的區域成為單元區域， 　在水準方向上，包含所述保護溝槽，且設置有柵極襯墊或者與該柵極襯墊相連接的佈置電極的區域成為柵極區域， 　在所述單元區域的所述柵極溝槽的上方以及所述柵極區域中設置第二導電構件， 　所述第二導電構件被設計為經過所述單元區域中不設有所述保護溝槽的地方，從所述單元區域的所述柵極溝槽的上方起延展到所述柵極區域。   發明效果
根據本發明，第二導電構件被設置為經過沒有被所述單元區域的保護溝槽包圍的地方，從單元區域的柵極溝槽的上方起延展到柵極區域。因此，本發明不需要將氧化物等的絕緣材料埋入保護溝槽內，不會特別增加製造工序，且能夠以保護溝槽將柵極溝槽的周圍包圍住從而防止電場外加到柵極溝槽中。
以下，將參照附圖關於碳化矽半導體裝置，碳化矽半導體裝置的製造方法以及碳化矽半導體裝置的設計方法的實施方式進行說明。
以下，將參照附圖關於碳化矽半導體裝置，碳化矽半導體裝置的製造方法以及碳化矽半導體裝置的設計方法的實施方式進行說明。
本實施方式的碳化矽半導體裝置例如是溝槽結構型MOSFET。以下，將使用溝槽結構型MOSFET作為碳化矽半導體裝置進行說明，但該溝槽結構型MOSFET僅是碳化矽半導體裝置的一個示例，還能夠適用於具有絕緣柵雙極型電晶體（Bipolar Transistor）（IGBT）等的MOS柵極的其他裝置結構。
如圖1所示，本實施方式的碳化矽半導體裝置包括：高濃度n型碳化矽半導體基板（第一導電型碳化矽半導體基板）31，被形成在高濃度n型碳化矽半導體基板31上的低濃度n型碳化矽層（第一導電型碳化矽層）32，以及被形成在低濃度n型碳化矽層32上的p型碳化矽層（第二導電型碳化矽層）36。另外，在p型碳化矽層36表面的一部分區域設有含有高濃度雜質的n型碳化矽區域37。
在本實施方式中，在從含有高濃度雜質的n型碳化矽區域37的表面穿過p型碳化矽層36直到低濃度n型碳化矽層32的深度處，形成柵極溝槽20。另外，在該柵極溝槽20內經由柵極絕緣膜75a從而設置柵極電極79。另外，在柵極電極79的上方設有層間絕緣膜75b。因此，柵極電極79被柵極絕緣膜75a以及層間絕緣膜75b包圍從而被設置。
另外，從p型碳化矽層36的表面直到比柵極溝槽20更深的深度處，形成有保護溝槽10。在該保護溝槽10內，設有例如由多晶矽（Polysilicon）構成的第一導電構件61。另外，在本實施方式中，該第一導電構件61與源極電極69為一體，在外加電壓時，變為相同電位（參照圖1）。另外，在保護溝槽10的側壁形成有側壁絕緣膜65。
另外，在本實施方式中，在保護溝槽10的底部，設有通過鋁（Aluminium）等的離子（Ion）注入從而被形成的高濃度p型半導體區域33。另外，在高濃度n型碳化矽半導體基板31的背面側（圖1的下表面側），設有漏極電極39。
如圖4所示，在本實施方式中，在水準方向上，包含柵極溝槽20，以及在水準方向上以開口的狀態將柵極溝槽20的僅一部分包圍的保護溝槽10這兩者的區域成為“單元（cell）區域”。另外，圖4僅為用於顯示本實施方式涉及的碳化矽半導體裝置的單元區域以及柵極區域的概略上方平面圖。因此，在圖4中，沒有顯示保護溝槽10的細微結構，也沒有考慮在水準方向上保護溝槽10之間的距離。另外，圖4中所示的在水準方向上單元區域以及柵極區域的大小沒有特殊含義。
另外，如圖4所示，在本實施方式中，在水準方向上，包含保護溝槽10，且設置有柵極襯墊89（參照圖2）或者與該柵極襯墊89相連接的佈置電極的區域成為“柵極區域”。另外，第二導電構件81的材料例如是多晶矽。
在如圖4中央部所示的柵極區域中設置有柵極襯墊89（參照圖2），佈置電極與該柵極襯墊89相連接。另外，如圖5所示，第二導電構件81主要被設置在位於單元區域的保護溝槽10的上方以往的地方。
如圖3所示，被包含在本實施方式中的柵極區域中的保護溝槽10具有：在水準方向上直線延伸的柵極區域直線溝槽16，和在水準方向上彎曲的柵極區域曲線溝槽17。另外，符號“17”為包含後述的符號“17a”以及符號“17b”的概念。另外，高濃度p型半導體區域33和第一導電構件61形成歐姆接觸(Ohmic Contact)，在外加電壓時變為相同電位。
本實施方式的柵極溝槽20在水準方向上直線延伸，更具體而言，在圖3中在左右方向上呈直線狀延伸。而且，柵極溝槽20與單元區域直線溝槽11在水準方向上呈平行（圖3的左右方向）地延伸。
如圖3所示，被包含在單元區域中的保護溝槽10具有一對在水準方向上直線延伸的單元區域直線溝槽11，和在水準方向上彎曲的單元區域曲線溝槽12。而且，在一對單元區域直線溝槽11之間設有在水準方向上直線延伸的（在圖3的左右方向上延伸）柵極溝槽20，在一對單元區域直線溝槽11的一端設有單元區域曲線溝槽12，在一對單元區域直線溝槽11的另一端不形成保護溝槽10。於是，保護溝槽10在水準方向上將柵極溝槽20的“僅一部分”包圍。另外，在本實施方式中，在水平方方向上單元區域的保護溝槽10呈連續的“S字形狀”，一對單元區域直線溝槽11的“另一端”的位置在圖3中的上下方向上依次進行左右反轉。因此，便能夠同時滿足保護溝槽10在水準方向上將柵極溝槽20的“僅一部分”包圍，和在保護溝槽10中不形成水準方向的端部這兩個條件。
如圖2所示，在單元區域中的柵極溝槽20的一部分的上方以及柵極區域中，設有第二導電構件81。第二導電構件81被設置為經過單元區域中不設有保護溝槽10的地方和在本實施方式中的一對單元區域直線溝槽11的另一端側，從柵極溝槽20的上方起延展到柵極區域（參照圖5）。於是，第二導電構件81被設置為經過一對單元區域直線溝槽11的另一端的上方，從柵極電極79的上方延展到柵極襯墊89的下方。另外，如圖2所示，該柵極襯墊89被設置為在柵極區域的保護溝槽10上經由SiO2 等的絕緣層85以及第二導電構件81。從圖2明顯可知，第二導電構件81與柵極電極79電連接。
另外，如圖3所示，在一對單元區域直線溝槽11的另一端側設有在水準方向上朝柵極溝槽20側突出的柵極區域曲線溝槽17a。另外，還設有與這樣地朝柵極溝槽20側突出的柵極區域曲線溝槽17a相鄰接，且朝該柵極區域曲線溝槽17a側突出的柵極區域曲線溝槽17b。
另外，如圖4所示，在本實施方式中，設有將柵極區域以及單元區域在水準方向上包圍的保護環80。另外，在圖4中，只顯示一個保護環80，而實際上設置多個保護環80呈同心圓狀亦可。
另外，如圖4所示，本實施方式的各個保護溝槽10在平面上看具有由一筆劃成的水準方向的端部。   製造工序
接著，將主要使用圖6對包含上述結構的本實施方式的碳化矽半導體裝置的製造工序進行說明。另外，在本實施方式中，還包含如以下這樣被製造的碳化矽半導體裝置的設計方法。
首先，準備高濃度n型碳化矽半導體基板31（參照圖6（a））。
接著，在高濃度n型碳化矽半導體基板31上通過外延（Epitaxial）生長從而形成低濃度n型碳化矽層32。
然後，在低濃度n型碳化矽層32上通過外延（Epitaxial）生長或者離子（Ion）注入從而形成p型碳化矽層36。
然後，通過在p型碳化矽層36中的柵極溝槽20的預定形成處的近旁將磷等進行離子注入，從而形成含有高濃度雜質的n型碳化矽區域37。之後，將保護層91形成薄膜，並將該保護層91圖形化（Patterning），從而形成由於形成保護溝槽10的開口（參照圖6（b））。接著，將該保護層91作為掩膜（Mask），從p型碳化矽層36的表面直到到達低濃度n型碳化矽層32的深度處形成保護溝槽10。
接著，形成將保護層91以及保護溝槽10覆蓋的保護膜92（參照圖6（c））。
接著，僅將保護膜92中保護溝槽10的底部去除，將殘留的保護膜92作為掩膜，通過在保護溝槽10的底部將鋁（Aluminium）等進行離子注入從而形成含有高濃度雜質的p型半導體區域33。之後，將保護膜92以及保護層91去除。之後，實施活性化退火（Anneal）處理。
之後，將保護層93形成薄膜，並將該保護層93圖形化（Patterning），從而形成由於形成柵極溝槽20的開口（參照圖6（d））。接著，將該保護層93作為掩膜（Mask），從p型碳化矽層36的表面直到到達低濃度n型碳化矽層32的深度處形成柵極溝槽20。另外，該柵極溝槽20的深度比保護溝槽10的深度淺。之後，將保護層93去除。
接著，在含有柵極溝槽20以及保護溝槽10的碳化矽半導體裝置的表面實施熱處理，形成作為柵極絕緣膜75a以及側壁絕緣膜65的氧化膜。之後，在該柵極絕緣膜75a上將多晶矽等的導電構件形成薄膜。該成膜之後，根據需要實施熱處理亦可。通過這樣，便如圖6（e）所示那樣在柵極溝槽20上形成柵極電極79以及第二導電構件81。
接著，通過採用等離子（Plasma）CVD等形成由二氧化矽（SiO2 ）等構成的絕緣膜使得將含有保護溝槽10的碳化矽半導體裝置的表面覆蓋，從而在柵極電極79上形成層間絕緣膜75，且柵極電極79被柵極絕緣膜75a和層間絕緣膜75b包圍（參照圖6（f））。另外，保護溝槽10底部的絕緣膜通過選擇性地蝕刻（Etching）被去除，僅殘留保護溝槽10側壁的側壁絕緣膜65。
之後，通過適當地設置第一導電構件61，絕緣層85，第二導電構件81，柵極襯墊89，源極電極69，漏極電極39，佈置電極等，從而製造本實施方式的碳化矽半導體裝置（參照圖1以及圖2）。
另外，這樣被製造的碳化矽半導體裝置的保護溝槽10的水平面內的設置將在“結構”處陳述。另外，上述製造方法僅僅為一個示例，無論哪種製造方法，只要能夠製造專利權利要求範圍中所記載的碳化矽半導體裝置就可以採用。   作用與效果
接著，將關於本實施方式涉及的作用·效果進行說明。
根據本實施方式，第二導電構件81被設置為經過沒有被所述單元區域的保護溝槽10包圍的地方，從單元區域的柵極溝槽20的上方起延展到柵極區域。因此，本發明不需要將氧化物等的絕緣材料埋入保護溝槽內，不會特別增加製造工序，且能夠以保護溝槽10將柵極溝槽20的周圍包圍住從而防止電場外加到柵極溝槽中。
即，從前，必須要將從柵極溝槽20的上方通往襯墊（Gate Pad）的多晶矽（Polysilicon）等的導電構件的配線設置為穿過保護溝槽10（參照圖7）。因此，必須要將氧化物等的絕緣材料埋入保護溝槽10的指定的地方（在圖7所示的形態中用“箭頭”指出的地方），且必須使導電構件的配線在該絕緣材料上穿過，導致存在製造工序增加的缺點。
與此相對，根據本實施方式，第二導電構件81被設置為經過沒有被所述單元區域的保護溝槽10包圍的地方，更具體而言是經過單元區域中不設有保護溝槽10的地方和在本實施方式中的一對單元區域直線溝槽11的另一端側的上方，從柵極電極79的上方延展到柵極襯墊89的下方（參照圖2以及圖5）。因此，在本實施方式中，不需要向從前那樣必須將氧化物等的絕緣材料埋入保護溝槽中，因此，便能夠相較於從前技術減少製造工序。
另外，在本實施方式中，在水平方方向上單元區域的保護溝槽10呈連續的“S字形狀”，一對單元區域直線溝槽11的“另一端”的位置在圖3中的上下方向上依次進行左右反轉。因此，便能夠同時滿足保護溝槽10在水準方向上將柵極溝槽20的“僅一部分”包圍，和在保護溝槽10中不形成水準方向的端部這兩個條件。
另外，當在保護溝槽10中形成水準方向的起點或者終點時，會在該端部形成棱角部分。而且，一旦形成這樣的棱角部分，便會導致在該部分引起電場集中的可能性。與此相對，根據本實施方式，保護溝槽10在水準方向上（在平面角度上）呈一筆劃成，在水準方向上沒有形成起點或終點。
因此，根據本實施方式，能夠達成相較於從前技術減少製造工序的效果，還能夠達成防止電場在保護溝槽10的端部過於集中的效果。
另外，根據本實施方式，被包含在柵極區域中的保護溝槽10具有在水準方向上彎曲的柵極區域曲線溝槽17。並且，在一對單元區域直線溝槽11的另一端側設有在水準方向上朝柵極溝槽20側突出的柵極區域曲線溝槽17a。因此，能夠防止被包含在單元區域中的保護溝槽10與柵極區域曲線溝槽17之間的水準方向距離變長，便能夠達成相較於從前技術減少製造工序的效果。
關於該點進行說明。
通常保護溝槽10之間的水準方向距離越長，外加到保護溝槽10中的電場就越大。然而，由於當像本實施方式這樣在一對單元區域直線溝槽11的另一端不形成單元區域曲線溝槽12時，向柵極區域側突出的保護溝槽10便不存在，因此在該另一端側中，被包含在單元區域的保護溝槽10與被包含在柵極區域的保護溝槽10的水準方向距離趨於邊長。
這一點，根據本實施方式，被包含在柵極區域中的保護溝槽10具有在水準方向上朝柵極溝槽20側突出的柵極區域曲線溝槽17。因此，能夠將被包含在單元區域中的保護溝槽10與柵極區域曲線溝槽17之間的水準方向距離縮短。因此，在滿足保護溝槽10在水準方向上將柵極溝槽20的“僅一部分”包圍的條件下，在偏壓時，能夠減小在被包含在單元區域中的保護溝槽10與柵極區域曲線溝槽17之間產生的電場，便能夠防止在該區域中局部電場過於集中的情況。
另外，在本實施方式中，還設有與朝柵極溝槽20側突出的柵極區域曲線溝槽17a相鄰接，且朝該柵極區域曲線溝槽17a側突出的柵極區域曲線溝槽17b。因此，能夠將朝柵極溝槽20側突出的柵極區域曲線溝槽17a與朝該柵極區域曲線溝槽17a側突出的柵極區域曲線溝槽17b之間的水準方向距離縮短。因此，在偏壓時，能夠減小在柵極區域曲線溝槽17之間產生的電場，便能夠防止在該區域中局部電場過於集中的情況。
另外，在本實施方式中的“水準方向距離”代表在水準方向上的“最短長度”的意思。當列舉單元區域直線溝槽11進行說明時，從某個單元區域直線溝槽11的一點起，相對於對向的單元區域直線溝槽11的長度有無數個，如圖3所示，除了D1 之外還能夠列舉D1 '或者D1 ''等。這一點，如上所述，由於將本實施方式中的“水準方向距離”定義為在水準方向上的“最短長度”，因此“水準方向距離”不是D1 '或者D1 ''，而是D1 。變形例
另外，在本實施方式中，採用單元區域曲線溝槽12的曲率半徑越小，與鄰接於該單元區域曲線溝槽12的柵極區域的保護溝槽10的水準方向距離就越小的形態亦可。
像這樣在採用單元區域曲線溝槽12的曲率半徑越小，與鄰接於該單元區域曲線溝槽12的柵極區域的保護溝槽10的水準方向距離就越小的形態的情況下，在偏壓時，能夠防止在單元區域曲線溝槽12的曲率半徑小的地方局部電場過於集中的情況。
另外，同樣地，採用柵極區域曲線溝槽17的曲率半徑越小，與鄰接於該柵極區域曲線溝槽17的柵極區域的保護溝槽10的水準方向距離就越小的形態亦可。
像這樣地在採用柵極區域曲線溝槽17的曲率半徑越小，與鄰接於該柵極區域曲線溝槽17的柵極區域的保護溝槽10的水準方向距離就越小的形態的情況下，在偏壓時，能夠防止在柵極區域曲線溝槽17的曲率半徑小的地方局部電場過於集中的情況。
最後，上述實施方式的記載，變形例以及附圖的公開只是用於對專利權利要求範圍中所記載的發明進行說明的一個示例，並不僅限於被記載於上述實施方式的記載，變形例以及附圖所公開的發明。
10‧‧‧保護溝槽
11‧‧‧單元區域直線溝槽
12‧‧‧單元區域曲線溝槽
16‧‧‧柵極區域直線溝槽
16a‧‧‧柵極區域直線溝槽
1b6‧‧‧柵極區域直線溝槽
17‧‧‧柵極區域曲線溝槽
17a‧‧‧柵極區域曲線溝槽
17b‧‧‧柵極區域曲線溝槽
20‧‧‧柵極溝槽
31‧‧‧高濃度n型碳化矽半導體基板（第一導電型碳化矽半導體基板）
32‧‧‧低濃度n型碳化矽層（第一導電型碳化矽層）
33‧‧‧高濃度p型半導體區域
36‧‧‧p型碳化矽層（第二導電型碳化矽層）
37‧‧‧n型碳化矽區域
39‧‧‧漏極電極
61‧‧‧第一導電構件（導電構件）
65‧‧‧側壁絕緣膜
69‧‧‧源極電極
75‧‧‧層間絕緣膜
75a‧‧‧柵極絕緣膜
75b‧‧‧層間絕緣膜
79‧‧‧柵極電極
80‧‧‧保護環
81‧‧‧第二導電構件
85‧‧‧絕緣層
89‧‧‧柵極襯墊
91‧‧‧保護層
92‧‧‧保護膜
93‧‧‧保護層
圖1是本發明的實施方式涉及的碳化矽半導體裝置的截面圖，且是將圖3的一部分沿上下方向切斷的截面圖。
圖2是本發明的實施方式涉及的碳化矽半導體裝置的截面圖，且是將圖3的一部分沿左右方向切斷的截面圖。
圖3是將本發明的實施方式涉及的碳化矽半導體裝置的一部分擴大的上方平面圖，且是顯示相當於圖4的A處的上方平面圖。
圖4是用於顯示本發明的實施方式涉及的碳化矽半導體裝置的單元區域以及柵極區域的概略上方平面圖。
圖5是用於顯示本發明的實施方式涉及的碳化矽半導體裝置中的第二導電構件的設置情況的概略上方平面圖。
圖6是用於說明本發明的實施方式涉及的碳化矽半導體裝置的製造方法的截面圖，且是與圖1相對應的截面圖。
圖7是用於顯示以保護溝槽將柵極溝槽在水準方向上的整個周圍包圍住的形態的概略上方平面圖。
10‧‧‧保護溝槽
20‧‧‧柵極溝槽
31‧‧‧高濃度n型碳化矽半導體基板(第一導電型碳化矽半導體基板)
32‧‧‧低濃度n型碳化矽層(第一導電型碳化矽層)
33‧‧‧高濃度p型半導體區域
36‧‧‧p型碳化矽層(第二導電型碳化矽層)
39‧‧‧漏極電極
61‧‧‧第一導電構件(導電構件)
65‧‧‧側壁絕緣膜
69‧‧‧源極電極
75‧‧‧層間絕緣膜
75a‧‧‧柵極絕緣膜
75b‧‧‧層間絕緣膜
79‧‧‧柵極電極
80‧‧‧保護環
81‧‧‧第二導電構件
85‧‧‧絕緣層
89‧‧‧柵極襯墊

Claims (8)

  1. 一種碳化矽半導體裝置，其特徵在於，包括：   第一導電型碳化矽層， 　被形成在所述第一導電型碳化矽層上的第二導電型碳化矽層， 　被形成在從所述第二導電型碳化矽層的表面直到到達所述第一導電型碳化矽層的深度處的柵極溝槽， 　在所述柵極溝槽內經由絕緣膜從而被設置的柵極電極， 　被形成在從所述第二導電型碳化矽層的表面直到比所述柵極溝槽更深的深度處的保護溝槽，以及 　被設置在所述保護溝槽內的第一導電構件， 　其中，在水準方向上，包含所述柵極溝槽，以及將所述柵極溝槽的僅一部分在水準方向上包圍的所述保護溝槽這兩者的區域成為單元區域， 　在水準方向上，包含所述保護溝槽，且設置有柵極襯墊或者與該柵極襯墊相連接的佈置電極的區域成為柵極區域， 　在所述單元區域的所述柵極溝槽的上方以及所述柵極區域中設有第二導電構件， 　所述第二導電構件被設置為經過所述單元區域中不設有所述保護溝槽的地方，從所述單元區域的所述柵極溝槽的上方起延展到所述柵極區域。
  2. 如請求項1所述的碳化矽半導體裝置，其特徵在於： 其中，被包含在所述單元區域中的所述保護溝槽具有一對在水準方向上直線延伸的所述單元區域直線溝槽和在水準方向上彎曲的單元區域曲線溝槽， 在所述一對單元區域直線溝槽的一端設有所述單元區域曲線溝槽， 在所述一對所述單元區域直線溝槽的水準方向之間設有所述柵極溝槽， 所述第二導電構件被設置為經過所述一對單元區域直線溝槽的另一端側的上方，從所述單元區域的所述柵極溝槽的上方起延展到所述柵極區域。
  3. 如請求項2所述的碳化矽半導體裝置，其特徵在於： 其中，所述柵極溝槽在水準方向上直線延伸， 所述柵極溝槽與所述單元區域直線溝槽在水準方向上呈平行延伸。
  4. 如請求項2或3中任意一項所述的碳化矽半導體裝置，其特徵在於： 其中，被包含在所述柵極區域中的所述保護溝槽具有在水準方向上彎曲的柵極區域曲線溝槽， 在所述一對單元區域溝槽的另一端側設有在水準方向上朝所述柵極溝槽側突出的所述柵極區域曲線溝槽。
  5. 如請求項4所述的碳化矽半導體裝置，其特徵在於： 其中，設有與朝所述柵極溝槽側突出的所述柵極區域曲線溝槽相鄰，且朝該柵極區域曲線溝槽側突出的所述柵極區域曲線溝槽。
  6. 如請求項1所述的碳化矽半導體裝置，其特徵在於： 其中，所述保護溝槽在水準方向上呈一筆劃成。
  7. 一種碳化矽半導體裝置的製造方法，其特徵在於，包括：   形成第一導電型碳化矽層的工序， 　在所述第一導電型碳化矽層上形成第二導電型碳化矽層的工序， 　在從所述第二導電型碳化矽層的表面直到到達所述第一導電型碳化矽層的深度處形成柵極溝槽的工序， 　在從所述第二導電型碳化矽層的表面直到比所述柵極溝槽更深的深度處形成保護溝槽的工序， 　在所述柵極溝槽內經由絕緣膜從而設置柵極電極的工序，以及 　在所述保護溝槽內設置第一導電構件的工序， 　其中，在水準方向上，由包含所述柵極溝槽，以及將所述柵極溝槽的僅一部分在水準方向上包圍的所述保護溝槽這兩者的區域成為單元區域， 　在水準方向上，由包含所述保護溝槽，且設置有柵極襯墊或者與該柵極襯墊相連接的佈置電極的區域成為柵極區域， 　在所述單元區域的所述柵極溝槽的一部分的上方以及所述柵極區域中設置第二導電構件， 　將所述第二導電構件設置為經過所述單元區域中不設有所述保護溝槽的地方，從所述單元區域的所述柵極溝槽的上方起延展到所述柵極區域。
  8. 一種碳化矽半導體裝置的設計方法，其特徵在於：     其中，所述碳化矽半導體裝置具有： 　　第一導電型碳化矽層， 　被形成在所述第一導電型碳化矽層上的第二導電型碳化矽層， 　被形成在從所述第二導電型碳化矽層的表面直到到達所述第一導電型碳化矽層的深度處的柵極溝槽， 　在所述柵極溝槽內被設置為經由絕緣膜的柵極電極， 　被形成在從所述第二導電型碳化矽層的表面直到比所述柵極溝槽更深的深度處的保護溝槽，以及 　被設置在所述保護溝槽內的第一導電構件， 　在水準方向上，包含所述柵極溝槽，以及將所述柵極溝槽的僅一部分在水準方向上包圍的所述保護溝槽這兩者的區域成為單元區域， 　在水準方向上，包含所述保護溝槽，且設置有柵極襯墊或者與該柵極襯墊相連接的佈置電極的區域成為柵極區域， 　在所述單元區域的所述柵極溝槽的上方以及所述柵極區域中設置第二導電構件， 　所述第二導電構件被設計為經過所述單元區域中不設有所述保護溝槽的地方，從所述單元區域的所述柵極溝槽的上方起延展到所述柵極區域。
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