CN105247679B - 碳掺杂半导体器件 - Google Patents

碳掺杂半导体器件 Download PDF

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CN105247679B
CN105247679B CN201480015652.0A CN201480015652A CN105247679B CN 105247679 B CN105247679 B CN 105247679B CN 201480015652 A CN201480015652 A CN 201480015652A CN 105247679 B CN105247679 B CN 105247679B
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斯塔西亚·凯勒
布赖恩·L·斯文森
尼古拉斯·费希滕鲍姆
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Chuan Shi Boat Electronics Co Ltd
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Abstract

一种制造半导体器件的方法，包括在反应器中形成III‑N半导体层以及把烃前体注入反应器中，由此碳掺杂III‑N半导体层并使III‑N半导体层绝缘或半绝缘。一种半导体器件，包括衬底以及衬底上的碳掺杂绝缘或半绝缘III‑N半导体层。III‑N半导体层中的碳掺杂密度大于5×1018cm‑3且III‑N半导体层中的位错密度小于2×109cm‑2。

Description

碳掺杂半导体器件
技术领域
本发明一般涉及制造半导体器件，特别涉及碳掺杂半导体器件。
背景技术
用于功率电子应用中的许多晶体管都由硅(Si)半导体材料制造。用于功率应用的通常晶体管器件包括Si CoolMOS，Si功率MOSFET以及Si绝缘栅双极晶体管(IGBT)。虽然Si功率器件廉价，但是它们存在许多缺点，包括较低的开关速度以及高水平的电噪声。最近，已经考虑采用碳化硅(SiC)功率器件，因为它们具有优越的特性。III族氮化物或III-N半导体器件，例如氮化镓(GaN)基器件目前已作为具有吸引力的候选器件，其可承载较大电流，支持高电压，且能提供非常低的导通电阻以及快速的切换时间。
发明内容
在一方面，制造半导体器件的方法包括在反应器中形成III-N半导体层，以及在形成III-N半导体层时将烃前体注入反应器中，由此碳掺杂III-N半导体层且使III-N半导体层绝缘或半绝缘。
在第二方面，半导体器件可包括衬底以及衬底上的碳掺杂绝缘或半绝缘III-N半导体层。III-N半导体层中的碳掺杂密度大于1×1018、5×1018或1×1019cm-3且III-N半导体层中的位错密度小于2×109cm-2。
在第三方面，形成半导体材料结构的方法可包括在反应器中在衬底上形成第一III-N半导体层，且在形成第一III-N半导体层时，将烃前体注入反应器中，由此碳掺杂第一III-N半导体层并使第一III-N半导体层绝缘或半绝缘。该方法可还包括在第一III-N半导体层上形成第二III-N材料层，其中第二III-N材料层基本上具有比第一III-N材料层低的碳浓度。
在第四方面，材料结构可包括异质衬底上的第一III-N半导体层，以及相对于异质衬底在第一III-N材料结构反面一侧上的第二III-N半导体层，第二III-N半导体层薄于第一III-N半导体层。第一III-N半导体层整个层中可具有大于1×1018cm-3的碳浓度，且整个第二III-N半导体层的碳浓度可小于整个第一III-N半导体层的碳浓度。而且，相对于衬底在反面的第二III-N材料层的表面可具有小于5特征/cm2的宏观特征密度，其中各个宏观特征具有大于100纳米的平均高度。
在第五方面，材料结构包括异质衬底上的第一III-N半导体层，以及相对于异质衬底在第一III-N材料结构反面一侧上的第二III-N半导体层，第二III-N半导体层薄于第一III-N半导体层。第一III-N可以是具有大于1×1018cm-3的碳浓度的绝缘或半绝缘层。第二III-N半导体层的碳浓度可小于第一III-N半导体层的碳浓度，且相对于异质衬底在反面的第二III-N半导体层的表面处的位错密度可小于2×109cm-2。
本文中说明的方法和器件可各包括以下特征。注入烃前体可包括注入具有化学式(CxHy)的烃前体，其中x和y是大于或等于1的整数。在衬底上形成III-N半导体层可包括在硅衬底上的III-N成核层上形成作为III-N缓冲层的III-N半导体层。方法可包括在III-N缓冲层上形成III-N沟道层以及在III-N沟道层上形成III-N势垒层，由此相邻于沟道层和势垒层之间的界面形成二维电子气(2DEG)有源沟道。形成作为III-N缓冲层的III-N半导体层可包括在多种生长条件下形成III-N缓冲层，且形成III-N沟道层可包括在相同或基本相同的生长条件下形成III-N沟道层。多种生长条件可包括表面温度和反应器压力。多种生长条件可还包括III族前体流速与V族前体流速的比值。在衬底上形成III-N半导体层可包括通过金属有机化学气相沉积(MOCVD)形成III-N半导体层。势垒层可包括AlGaN，沟道层可包括非掺杂或非故意掺杂(UID)GaN，且缓冲层可包括AlGaN或GaN或上述两种。
形成III-N半导体层可包括在III族前体摩尔流速下将III族前体注入反应器，且将烃注入反应器可包括在烃前体摩尔流速下将烃前体注入反应器，其中烃前体摩尔流速至少为III族前体摩尔流速的0.02倍。形成III-N半导体层可包括在III族前体摩尔流速下将III族前体注入反应器，以及将烃前体注入反应器可包括在烃前体摩尔流速下将烃前体注入反应器，其中烃前体摩尔流速大于III族前体摩尔流速。烃前体可包括丙烷或甲烷或上述两种。方法可还包括将栅端子，漏端子以及源端子加入半导体器件，由此形成III-N高电子迁移率晶体管(HEMT)。方法可还包括将阳极端子和阴极端子加入半导体器件，由此形成III-N二极管。使III-N半导体层绝缘或半绝缘可包括使III-N半导体层具有至少1×105或1×107ohm-cm的电阻率。碳掺杂III-N半导体层可致使III-N半导体层具有大于1×1018cm-3的碳浓度。烃前体可注入反应器中，同时形成第一III-N材料层，但是不同时形成第二III-N材料层。
III-N半导体层可具有远离衬底的第一侧以及第一侧和衬底之间的第二侧，其中III-N半导体层的位错密度是相邻于III-N半导体层的第一侧的位错密度。III-N半导体层可包括III-N成核层上的III-N缓冲层，其中衬底是硅衬底。器件可还包括III-N缓冲层上的III-N沟道层以及III-N沟道层上的III-N势垒层，由此形成相邻于沟道层和势垒层之间界面的二维电子气(2DEG)有源沟道。势垒层可包括AlGaN，沟道层可包括非掺杂或非故意掺杂(UID)GaN，且缓冲层可包括AlGaN或GaN或上述两种。衬底可以是异质衬底。器件可还包括栅端子，漏端子以及源端子，其中半导体器件是III-N高电子迁移率晶体管(HEMT)。器件可还包括阳极端子和阴极端子，其中半导体器件是III-N二极管。III-N半导体层中的碳掺杂密度可小于5×1021cm-3。
相对于衬底在反面的第二III-N材料层的表面可具有小于5特征/cm2的宏观特征密度，其中各个宏观特征都具有大于100纳米的平均高度。第一III-N半导体层和第二III-N半导体层的组合厚度可小于6微米，例如小于5微米，小于4微米或小于3微米。第二III-N材料层可薄于第一III-N材料层。
可实施本说明书中说明的主旨的特殊实施例以便实现一个以上的以下优点。与常规技术相比，绝缘或半绝缘碳掺杂III-N层可形成有宽范围浓度(1e16-1e22cm-3)的碳掺杂水平且对层的一个以上的生长参数具有更少限制。绝缘或半绝缘层可形成有低位错密度以及异质衬底上生长的光滑表面，例如Si或SiC衬底。在金属有机化学气相沉积(MOCVD)过程中注入不含卤素的前体(例如烃前体)可降低或消除包含分子的卤素与金属有机前体的相互作用，由此避免碳掺杂AlGaN的MOCVD生长过程中CX4(X＝卤素)前体对合金组分(即，AlGaN中Al与Ga的比值)的影响。
附图说明
图1A和1B是一个实例III-N半导体器件的截面图。
图2是制造包括碳掺杂层的III-N半导体器件的一个实例方法的流程图。
图3是制造具有碳掺杂的至少一个层的III-N半导体器件的***的框图。
图4是一个实例III-N半导体材料结构的截面图。
图5A和5B分别是形成在III-N材料结构的表面上的宏观特征的截面和平面示意图。
各个附图中相同的参考符号表示相同的元件。
具体实施方式
图1A是一个实例III-氮化物(即III-N)半导体器件100的截面图。例如，如图1B中所示，通过将源极114，漏极116以及栅极118的端子加入该器件，该器件可以是晶体管，例如III-N高电子迁移率晶体管(HEMT)。在另一实例中，该器件可以是通过将阳极和阴极端子加入器件的二极管(未示出)。
器件包括衬底102。衬底例如可以是硅、SiC、氮化铝(AlN)、GaN、蓝宝石(Al2O3)或用于III-N材料生长的任何其他合适的生长衬底。因为较大的同质衬底(即由III-N材料形成的衬底)目前不能获得且往往非常昂贵，因此该器件通常形成在异质衬底(即由不是III-N材料的材料形成的衬底)上，例如硅、碳化硅或蓝宝石。器件包括衬底上的成核层104。成核层可以是III-N成核层且例如可包括AlN。
器件包括缓冲层106。缓冲层可以是III-N缓冲层且例如可包括C掺杂的AlGaN或GaN或上述两种。缓冲层可包括若干不同的层，例如具有更高Al浓度的更靠近衬底的某些层以及具有更低Al浓度的远离衬底的某些层。可通过碳掺杂缓冲层而使缓冲层绝缘或半绝缘。这里如可用于避免次表层泄漏或过早击穿。
器件包括III-N沟道层108和III-N势垒层110，其中选择沟道层和势垒层的组分以感生相邻于沟道层和势垒层之间界面的二维电子气(2DEG)112有源沟道。例如，沟道层可包括非掺杂或非故意掺杂(UID)GaN且势垒层可包括AlGaN。
术语III-氮化物或III-N材料、层、器件以及结构是指由根据化学计量式BwAlxInyGazN的化合物半导体材料构成的材料、器件或结构，其中w+x+y+z约为1，且w,x,y和z各大于或等于零且小于或等于1。在III-氮化物或III-N器件中，导电沟道可部分或整体包含在III-N材料层中。
可通过在反应器中的分子束取向附生(MBE)或金属有机化学气相沉积(MOCVD)或其他技术形成器件的层。一种实现通过具有作为氮前体的NH3的MOCVD形成的III-N层中的碳掺杂的方式是调整层生长条件以使碳从金属有机前体(例如TMGa或TMAl或上述两种)混入层中。例如，适于碳混入的某些生长条件包括：低反应器压力，低NH3分压，低沉积温度以及高生长速度。
当执行这些生长条件用于在足以使层变成绝缘或半绝缘以用于某些应用的水平下进行碳掺杂，相对于层的其他特征的校准会限制生长条件，例如层的螺旋位错密度和表面粗糙度。例如，考虑在异质衬底(即非III-N)上形成层，例如硅(Si)，碳化硅(SiC)或蓝宝石(Al2O3)。
可在包括较低反应器压力，较低NH3分压，较低沉积温度以及较高生长速度中的一种以上的生长条件下形成这种层，但是这些生长条件也会导致层中更高的位错密度和点缺陷的更高水平。利用这些方法将碳掺杂水平增至大于约5×1018cm-3(且在某些情况下大于8×1017cm-3)会额外导致表面粗糙或差的表面形态或上述两者。
在层中实现碳掺杂的另一方式是在层的生长过程中将烃前体注入反应器中。烃前体包括化学组分(CxHy)，其中x和y是大于或等于1的整数的分子。烃的实例包括丙烷(C3H8)，甲烷(CH4)以及C2H2。
这种实现碳掺杂的方式可致使层中具有超过1×1018、5×1018、1×1019或3×1019cm-3的碳掺杂，而同时具有小于2×109cm-2，例如约1×109cm-2或小于约8×108cm-2以下的位错密度。III-N半导体层中的碳掺杂密度可处于1×1019cm-3和5×1021cm-3之间，或处于1×1018cm-3和5×1021cm-3。在某些实施方式中，成核层为20-50nm之间厚，缓冲层为1－10微米之间厚(例如约5微米)，沟道层约200-1000nm厚(典型地约400nm)，且势垒层为10-40nm之间厚(例如约25nm)。
图2是制造包括碳掺杂层的III-N半导体器件的实例方法200的流程图。为了说明，将参考图1的实例器件100说明该方法，但是该方法可用于制造其他器件且在其他器件中的其他类型的层中进行碳掺杂。
成核层形成在硅衬底上(202)。例如，硅衬底可置于诸如MOCVD反应器的反应器中，且可在反应器中沉积例如作为AlN层的成核层。
缓冲层形成在成核层上(204)。例如，可例如沉积缓冲层作为AlGaN或GaN或这两者的层。在某些实施方式中，缓冲层包括一个以上的层。沉积AlGaN的层，且在各个连续的层中提高Al的量。最终，可沉积一个以上的GaN层。
在形成缓冲层时，把烃前体注入反应器(206)。例如，可在将III族和/或V族前体注入反应器时同时或交替把烃前体注入反应器。
沟道层形成在缓冲层(208)上。例如，可沉积沟道层例如作为非掺杂或非故意掺杂(UID)GaN的层。在某些实施方式中，在与缓冲层相同或基本相同的生长条件下形成沟道层。其中缓冲层包括GaN的顶层，可通过在没有改变反应器中的任何其他生长条件的情况下停止注入烃前体并继续沉积GaN而沉积沟道层。即，对于沟道层和对于紧邻沟道层的部分缓冲层而言，反应器压力和/或温度和/或注入反应器中的总气体摩尔流速和/或V族前体摩尔流速与III族前体摩尔流速的比值可相同，且在紧邻沟道层的部分缓冲层的生长过程中而不是沟道层的生长过程中将烃前体注入反应器中。
势垒层形成在沟道层上(210)。例如，可沉积势垒层例如作为AlGaN的层。相邻于沟道层和势垒层之间的界面感生二维电子气(2DEG)有源沟道。较之沟道层势垒层可具有更大的带隙(bandgap)，其又可至少部分地引起沟道层中感生2DEG。为了形成晶体管，随后在III-N材料层结构上形成源极、栅极和漏极端子(212)。或者，为了形成二极管，随后在III-N材料层结构上形成阳极和阴极端子(未示出)。
图3是制造具有被碳掺杂的至少一个层的III-N半导体器件的***300的框图。该***例如可用于执行图2的方法以制造图1A和1B的器件。
***包括反应器302，例如MOCVD反应器。衬底304置于反应器中且III-N层306形成在衬底上。反应器控制***308通过调整一个或多个生长条件而控制层306的形成。反应器控制***可控制一种或多种材料注入反应器，包括载气316(例如诸如H2或N2或上述两者的惰性载气)，V族前体气体318(例如NH3)，III族前体气体320(例如TMGa或TMAl或上述两者)，以及烃前体气体322(例如C3H8,CH4,以及C2H2的一种以上)。
可实现反应器控制***例如作为一个以上的计算机以及用于气体的存储模块的***，计算机接收来自操作者的输入并例如提供输出至反应器的控制信号。反应器控制***例如可包括压力控制模块310(例如控制反应器中的压力)、沉积温度控制模块312(例如控制将要形成的层的表面温度)、生长速率模块314以及其他模块。生长速率模块314可通过控制影响生长速率的变量，例如反应器压力，表面温度以及各种前体和载气的流速而直接控制生长速率。
在某些实施方式中，反应器控制***构造为通过将III族前体在III族前体摩尔流速下注入反应器以及通过将烃前体在烃前体摩尔流速下注入反应器而形成III-N半导体层。层中的碳掺杂量可通过改变烃前体摩尔流速和III族前体摩尔流速之间的比值而至少部分地控制。
已经发现，在III-N材料的MOCVD生长过程中用于III-N材料的碳掺杂的某些烃前体，特别是丙烷(C3H8)，掺杂剂混入效率远低于在III-N材料的MOCVD生长过程中典型地引入的其他掺杂剂的混入效率。例如，对于诸如硅的掺杂剂来说，其中硅烷或乙硅烷用作硅前体，当硅前体摩尔流速与III族前体摩尔流速的比值约为1/1000(且在某些情况下更低)时，III-N材料中的硅掺杂水平约等于III-N材料中的掺杂剂的饱和极限，其可约为1×1021cm-3。相对于III族前体摩尔流速将硅前体摩尔流速增加至更高的值基本上不会增加层中的电有源硅的浓度，且通常会导致所得的III-N层的更差的结构质量，例如致使更高的位错和点缺陷密度，以及较差的表面形态。但是，对于利用丙烷作为碳前体的MOCVD生长过程中的III-N材料的碳掺杂来说，当在对应于没有丙烷前体的较低碳掺杂水平(例如小于1×1017cm-3)的反应器条件下执行生长时，在约为III族前体摩尔流速的1/1000的摩尔流速下加入丙烷基本上不会增加III-N材料中的碳掺杂，且通常仍能产生小于1×1017cm-3的碳掺杂水平。
在某些***中，且特别在丙烷(C3H8)用作烃前体时，需要约为或至少为III族前体摩尔流速0.02倍的烃前体摩尔流速以使层中的碳掺杂水平处于约1×1017和1×1019cm-3之间，或超过1×1017cm-3。在某些***中，当烃前体摩尔流速约为或至少为III族前体摩尔流速0.2倍时，层中的碳掺杂水平可约为或超过1×1018cm-3，或处于约1×1018和1×1020cm-3之间。在某些***中，当烃前体摩尔流速基本上大于III族前体摩尔流速时，例如为III族前体摩尔流速的2倍或20倍或200倍或2000倍或20000倍时，层中的碳掺杂水平可约为或超过1×1018或1×1019或1×1020cm-3。借助丙烷前体形成的碳掺杂层的电阻率对于约1e18cm-3以上的碳掺杂水平可大于1×105ohm-cm，或对于约1×1019cm-3以上的碳掺杂水平可大于1×107ohm-cm或对于约1×1020cm-3以上的碳掺杂水平可大于1×108ohm-cm。
在某些实施方式中，反应器控制***构造为在1077C的表面温度以及200mBarr的压力下形成至少一层(例如UID GaN沟道层)。反应器控制***使氮前体例如氨气(NH3)在0.54mol/min的速率下流入反应器，使三甲基镓(TMGa)在0.65milli-mol/min的速率下流入反应器，并在或约80公升每分钟下控制总气体流入反应器。反应器控制***可通过增加或降低载气流动量以补偿其他流动量的增加或降低而在基本恒定的速率下保持总气体流动量。这致使这个层中约5×1016cm-3以下的碳掺杂。
反应器控制***可通过使烃前体流入反应器而在相同或基本相同的生长条件下形成碳掺杂层。例如，对于碳掺杂层来说，如果表面温度保持在1077C，则压力保持在200mBarr，氨气流速保持在0.54mol/min，TMGa流速保持在0.65milli-mol/min，且反应器中的总气体流量速率保持在80公升每分钟，通过使烃前体流入反应器，可实现大于1×1018cm-3，大于5×1018cm-3，大于1×1019cm-3，或大于1×1020cm-3的碳掺杂水平。同时，如果碳掺杂III-N层形成在诸如硅的异质衬底上，则碳掺杂III-N层的上部(即，相邻于最远离衬底的碳掺杂III-N层的表面的部分)的位错密度可保持在小于2×109cm-2的水平下，且典型地小于1×109cm-2，即使结构中的III-N层的总厚度小于6微米，小于5微米，小于4微米或小于3微米。
通过比较，如果烃前体没有在碳掺杂层的生长过程中流入反应器，则反应器控制***可将一个或多个或全部生长参数调整为混入足够的碳以使碳掺杂层变成绝缘至规定程度。例如，反应器控制***可将压力降至50mBarr，将温度降至1020C，将NH3流速降至0.045mol/min，在约80公升每分钟下保持总气体流量，并保持III族前体气体的流量。
这些对生长条件的调整可致使碳掺杂升至约5×1018cm-3。当在这些条件下生长层时的层的上表面的位错密度可大于2×109cm-2，且典型地处于5×109以及6×109cm-2之间。进一步调整反应器条件以进一步增大这些层中的碳浓度可致使材料结构的表面形态的实质退化，且典型地也致使更高的位错密度。
现在参考图4，在许多III-N半导体器件中，器件的有源部包含在最远离衬底402的III-N结构420的层418中。例如，参考图1A和1B的晶体管结构，器件沟道112包含在沟道层108(因此图1A和1B的沟道层108和势垒层110对应于图4的附加层418)中。在这种器件中，通常优选将衬底402和/或成核层404和/或缓冲层406与附加层418电绝缘，同时在导致附加层418中最小缺陷和/或陷阱的条件下形成附加层418。如上所述，这可通过分别在成核层404和/或缓冲层406的生长的过程中将烃前体注入反应器而实现，以借助碳对这些层进行掺杂以使它们绝缘或半绝缘，同时以基本上更低的碳水平生长某些或全部附加层418而作为非掺杂(或非故意掺杂)层。在许多情况下，缓冲层406的厚度大于附加层418的厚度，以使III-N材料机构的至少一半的厚度都具有实质的碳掺杂。与成核层和/或缓冲层的碳掺杂由其他方法实现的情况相比，这种结构可致使附加层418的表面处的降低的位错密度，以及使III-N材料结构420的上表面基本上更光滑。这些改善的特性致使起稿的器件性能以及更高的良率。
例如，当通过上述其他方法实现碳掺杂时，例如在碳掺杂层的生长过程中降低反应器压力和温度，已经发现生长在异质衬底(例如硅衬底)上的所得的III-N薄膜具有表面上更大的宏观特征。虽然这些特征往往具有其间的明显的空间分隔量，但是直接形成在这些特征上的器件不能工作或比晶圆上的其他器件更差的执行。
在导致这些特征的更高密度的条件下生长的III-N材料结构520的表面上形成的宏观特征500的示意图在图5A和5B中示出。图5A是特征500的截面图，且图5B是特征500的平面图(顶视图)。如图5B的平面图中可以看出，特征500可具有六边形。特征的平均直径502典型地大于20微米，且更具体为约20-500微米范围内，且特征的平均高度504典型地大于100纳米，例如约200-500纳米。为了比较，不包括这些宏观特征的晶圆的区域中，表面高度的平均偏差典型地远小于20纳米。
再次参考图4，已经发现当成核层404和/或缓冲层406分别具有大于1×1018cm-3的的碳掺杂密度时，当通过调整反应器条件，例如通过降低表面温度和反应器压力以将更高浓度的碳混入III-N层中而实现碳掺杂时，III-N材料结构420的表面具有大于8特征/cm2的宏观特征500的密度。另一方面，当通过在层404和/或406的生长过程中将诸如丙烷的烃前体注入而实现碳掺杂时，可使宏观特征500的密度小于5特征/cm2，且典型地小于2特征/cm2。
已经说明了多种实施方式。然而，将理解可在不脱离本文说明的技术和器件的精神和范围内进行各种变型。例如，本文说明的用于形成碳掺杂III-N层的工艺可用于需要绝缘或半绝缘层的其他器件，例如光伏电池，激光器和LED的制造中。因此，其他实施方式也处于下述权利要求的范围内。

Claims (31)

1.一种制造半导体器件的方法，该方法包括：
在反应器中在衬底上形成III-N半导体层，其中形成所述III-N半导体层包括在III-N成核层上方形成III-N缓冲层；以及
在形成所述III-N缓冲层时，把第一前体、第二前体和第三前体同时注入所述反应器中，其中所述第一前体是III族前体，所述第二前体是V族前体，并且所述第三前体是烃前体，由此碳掺杂所述III-N缓冲层，使所述III-N缓冲层绝缘或半绝缘并且具有比所述III-N成核层高的碳掺杂浓度。
2.如权利要求1的方法，其中注入烃前体包括注入具有化学式(CxHy)的烃前体，其中x和y是大于或等于1的整数。
3.如权利要求1的方法，其中所述衬底是Si衬底。
4.如权利要求1的方法，还包括在所述III-N缓冲层上形成III-N沟道层以及在所述III-N沟道层上形成III-N势垒层，由此形成相邻于所述沟道层和所述势垒层之间的界面的二维电子气(2DEG)有源沟道。
5.如权利要求4的方法，其中形成所述III-N缓冲层包括多个生长条件，并且其中形成所述III-N沟道层包括在相同的生长条件下形成所述III-N沟道层。
6.如权利要求5的方法，其中所述多个生长条件包括表面温度和反应器压力。
7.如权利要求6的方法，其中所述多个生长条件还包括III族前体流速与V族前体流速的比值。
8.如权利要求4的方法，其中所述势垒层包括AlGaN，所述沟道层包括非掺杂或非故意掺杂GaN，且所述缓冲层包括AlGaN或GaN或这两者。
9.如权利要求1-8任一项的方法，其中在所述衬底上形成所述III-N半导体层包括通过金属有机化学气相沉积(MOCVD)形成所述III-N半导体层。
10.如权利要求1-8任一项的方法，其中形成所述III-N缓冲层包括在所述III族前体摩尔流速下把III族前体注入所述反应器，并且把烃前体注入所述反应器包括在烃前体摩尔流速下把烃前体注入所述反应器，其中所述烃前体摩尔流速是III族前体摩尔流速的至少0.02倍。
11.如权利要求1-8任一项的方法，其中形成所述III-N缓冲层包括在III族前体摩尔流速下把所述III族前体注入所述反应器，并且把烃前体注入所述反应器包括在烃前体摩尔流速下把烃前体注入所述反应器，其中烃前体摩尔流速大于III族前体摩尔流速。
12.如权利要求1-8任一项的方法，其中所述烃前体包括丙烷或甲烷或这两者。
13.如权利要求1-8任一项的方法，还包括将栅极端子、漏极端子以及源极端子加入所述半导体器件，由此形成III-N高电子迁移率晶体管(HEMT)。
14.如权利要求1-8任一项的方法，还包括把阳极端子和阴极端子加入所述半导体器件，由此形成III-N二极管。
15.如权利要求1-8任一项的方法，其中使所述III-N缓冲层绝缘或半绝缘包括使所述III-N缓冲层具有至少1×107ohm-cm的电阻率。
16.如权利要求1-8任一项的方法，其中使所述III-N缓冲层绝缘或半绝缘包括使所述III-N缓冲层具有至少1×105ohm-cm的电阻率。
17.如权利要求1-8任一项的方法，其中碳掺杂所述III-N缓冲层导致所述III-N缓冲层具有大于1×1018cm-3的碳浓度。
18.一种半导体器件，包括：
衬底；以及
所述衬底上的碳掺杂绝缘或半绝缘III-N半导体层，所述III-N半导体层包括III-N成核层上方的III-N缓冲层，
所述III-N缓冲层中的碳掺杂密度大于所述III-N成核层中的碳掺杂密度，其中
所述III-N缓冲层中的碳掺杂密度大于5×1018cm-3且所述III-N缓冲层中的位错密度小于2×109cm-2。
19.如权利要求18的半导体器件，其中所述III-N半导体层具有远离所述衬底的第一侧以及所述第一侧和所述衬底之间的第二侧，且所述III-N半导体层中的位错密度是相邻于所述III-N半导体层的第一侧的位错密度。
20.如权利要求19的半导体器件，其中所述衬底是异质衬底。
21.如权利要求19的半导体器件，其中所述衬底是硅衬底。
22.如权利要求21的半导体器件，还包括所述III-N缓冲层上的III-N沟道层以及所述III-N沟道层上的III-N势垒层，由此形成相邻于所述沟道层和所述势垒层之间的界面的二维电子气(2DEG)有源沟道。
23.如权利要求22的半导体器件，其中所述势垒层包括AlGaN，所述沟道层包括非掺杂或非故意掺杂GaN，以及所述缓冲层包括AlGaN或GaN或这两者。
24.如权利要求18-23中任一项的半导体器件，还包括栅极端子、漏极端子以及源极端子，其中所述半导体器件是III-N高电子迁移率晶体管(HEMT)。
25.如权利要求18-23中任一项的半导体器件，还包括阳极端子和阴极端子，其中所述半导体器件是III-N二极管。
26.如权利要求18-23中任一项的半导体器件，其中所述III-N缓冲层中的碳掺杂密度小于5×1021cm-3。
27.一种材料结构，包括：
异质衬底上的第一III-N半导体层；
在所述第一III-N半导体层上方的第二III-N半导体层；以及
在所述第二III-N半导体层上方的第三III-N半导体层，所述第一III-N半导体层和所述第三III-N半导体层薄于所述第二III-N半导体层；其中
所述第二III-N半导体层在整个层具有大于1×1018cm-3的碳浓度；
整个所述第一III-N半导体层和所述第三III-N半导体层的碳浓度小于整个所述第二III-N半导体层的碳浓度；以及
相对于所述衬底在反面的所述第三III-N材料层的表面具有小于5特征/cm2的宏观特征的密度，其中每个宏观特征都具有大于100纳米的平均高度。
28.如权利要求27的材料结构，所述第三III-N半导体层包括III-N势垒层和III-N沟道层，其中二维电子气(2DEG)有源沟道相邻于所述III-N沟道层和所述III-N势垒层之间的界面。
29.如权利要求27或28的材料结构，其中所述第一III-N半导体层、所述第二III-N半导体层和所述第三III-N半导体层的组合厚度小于6微米。
30.一种材料结构，包括：
异质衬底上的第一III-N半导体层；
在所述第一III-N半导体层上的第二III-N半导体层；以及
在所述第二III-N半导体层上方的第三III-N半导体层，所述第一III-N半导体层和所述第三III-N半导体层薄于所述第二III-N半导体层；其中
所述第二III-N半导体层是具有大于1×1018cm-3的碳浓度的绝缘或半绝缘层；
所述第一III-N半导体层和所述第三III-N半导体层的碳浓度小于所述第二III-N半导体层的碳浓度；以及
相对于所述异质衬底在反面的所述第三III-N半导体层的表面处的位错密度小于2×109cm-2。
31.如权利要求30的材料结构，其中所述第一III-N半导体层、所述第二III-N半导体层和所述第三III-N半导体层的组合厚度小于6微米。
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