CN104425397B - 一种晶圆级封装方法及封装结构 - Google Patents

一种晶圆级封装方法及封装结构 Download PDF

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CN104425397B
CN104425397B CN201410064021.XA CN201410064021A CN104425397B CN 104425397 B CN104425397 B CN 104425397B CN 201410064021 A CN201410064021 A CN 201410064021A CN 104425397 B CN104425397 B CN 104425397B
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conductive pole
wafer
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chip
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CN104425397A (zh
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廖宗仁
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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Abstract

本发明提供一种晶圆级封装方法及封装结构，其包含下列步骤：例如，形成一贯穿孔于一中介层，其中该中介层的厚度不大于第一导电柱的长度；设置该第一导电柱于该贯穿孔；沉积一线路重布层，其电性连接该第一导电柱；设置一锡球于该线路重布层上，以形成一晶圆级封装结构。

Description

一种晶圆级封装方法及封装结构
技术领域
本发明涉及一种封装方法及封装结构，更具体地说，涉及一种晶圆级封装方法及封装结构。
技术背景
目前的硅中介层主要为运用硅穿孔(TSV)技术及铜电镀制程来形成导通硅中介层的上层与硅中介层的下层的介面。由于硅穿孔(TSV)技术所形成的孔径较小，因此铜电镀制程很难于硅穿孔中形成导通的电路。此外，铜电镀制程完成后，还需要将硅中介层进行研磨而促进硅中介层的上层与硅中介层的下层间的电性导通，因此良率不高。且铜电镀制程中，电镀药水及机台均需重新调配及设计，而使整体成本升高。
发明内容
本发明提供一种晶圆级封装方法及封装结构，其方法包含下列步骤：
提供一第一晶圆，其包含一表面，其中一介电层及一第一导电柱于该表面上，且该第一导电柱穿透该介电层；
切割该第一晶圆而形成一第一晶片；
形成一贯穿孔于一中介层，其中该中介层的厚度不大于该第一导电柱的长度；
设置该第一导电柱于该贯穿孔；
覆盖一封装层于该第一晶片及部份的中介层(30)上；
涂布一第一电绝缘层于该中介层的一表面上；
沉积一线路重布层于该第一电绝缘层上，其中该线路重布层电性连接该第一导电柱；以及
设置一锡球于该线路重布层上，进而完成晶圆级封装结构。
本公开提供一种晶圆级封装结构包含一第一晶片、一中介层、一封装层、一第一电绝缘层、一线路重布层及一锡球。第一晶片包含一表面，其中一介电层及一第一导电柱设置于该表面上，且该第一导电柱穿透该介电层。中介层具有至少一贯穿孔，其中该中介层的厚度不大于该第一导电柱的长度。该第一晶片设置于该中介层上，使该第一导电柱设置于该贯穿孔中。封装层覆盖于该第一晶片及部份的中介层上。第一电绝缘层设置于该中介层的一表面上。线路重布层设置于该第一电绝缘层上，其中该线路重布层电性连接该第一导电柱以及锡球连接于该线路重布层上。
本发明的其他目的，部分将在后续说明中陈述，而部分可由内容说明中轻易得知，或可由本发明的实施而得知。本发明的各方面将可利用后附的权利要求书中所特别指出的元件及组合而理解并达成。需了解，先述的一般说明及下列详细说明均仅作举例之用，并非用以限制本发明。
附图说明
为了使本发明的叙述更加详尽与完备，可参照下列描述并配合下列附图，其中类似的元件符号代表类似的元件。然以下实施例中所述，仅用以说明本发明，并非用以限制本发明的范围。
图1为根据本发明的一个实施例的第一晶圆的示意图；
图2为根据本发明的一个实施例的第一晶圆切割后所形成的第一晶片的示意图；
图3为根据本发明的一个实施例的第二晶圆的示意图；
图4为根据本发明的一个实施例的第二晶圆切割后所形成的第二晶片的示意图；
图5为根据本发明的一个实施例的形成贯穿孔于中介层的示意图；
图6为根据本发明的一个实施例的第一晶片及第二晶片设置于中介层上的示意图；
图7为根据本发明的一个实施例的覆盖封装层于中介层上的示意图；
图8为根据本发明的一个实施例的涂布第一电绝缘层于中介层上的示意图；
图9为根据本发明的一个实施例的沉积线路重布层于电绝缘层上的示意图；
图10为根据本发明的一个实施例的涂布第二电绝缘层于中介层上的示意图；以及
图11为根据本发明的一个实施例的设置锡球于线路重布层上的示意图。
具体实施方式
本发明的晶圆级封装方法及封装结构包含下列所述的各个附图的步骤，然而并不限于此，亦可因应不同的设计而省略或修正特定步骤。
如图1所示，提供一第一晶圆10。第一晶圆10包含一表面11。至少一第一导电柱14形成于晶圆10表面11上。此外，一介电层13形成于表面11，但不覆盖第一导电柱14。换言之，第一导电柱14穿透介电层13。如图1所示，至少一第一导电柱14设置于表面11上。在此说明书及权利要求书中的名词“上”包含第一物件直接或间接地 设置于第二物件的上方。例如，至少一第一导电柱14设置于表面11上就包含，第一导电柱14“直接”设置于表面11上及第一导电柱14“间接”设置于表面11上，两种意义。此处的“间接”是指两个物件在某一方位的垂直方向中具有上与下的关系，且两者中间仍有其他物体、物质或间隔将两者隔开。
如图2所示，第一晶圆10切割而形成第一晶片15。换言之，第一晶片15就是部分的第一晶圆10。因此，第一晶片15的结构与第一晶圆10相同。
如图3所示，第二晶圆20包含一上表面21。至少一第二导电柱24形成于上表面21上。此外，一电隔离层23形成设于上表面21，但不覆盖第二导电柱24。换言之，第二导电柱24穿透电隔离层23。在此实施例中，第二导电柱24与第一导电柱14的直径或宽度并不相同。具体而言，第二导电柱24的半径小于第一导电柱14的半径。然而在其他实施例(图未示)中，第二导电柱24亦可设计为与第一导电柱14的直径或宽度相同。
如图4所示，第二晶圆20切割而形成第二晶片25。换言之，第二晶片25就是部分的第二晶圆20。因此，第二晶片25的结构与第二晶圆20相同。此外，此实施例中，设置于上表面21上的电隔离层23的厚度与介电层13的厚度不相同。具体而言，电隔离层23的厚度厚于介电层13的厚度。此厚度的差异可用来避免寄生效应或短路的现象。再者，此实施例中，第二导电柱24之间的距离与第一导电柱14之间的距离并不相同。具体而言，第二导电柱24之间的距离小于第一导电柱14之间的距离。然而在其他实施例(图未示)中，第一晶圆10与第二晶圆20可为相同的结构。换言之，第一导电柱14与第二导电柱24之间的直径或宽度、距离可为相同，且电隔离层23的厚度亦可与介电层13的厚度相同。
在其他实施例中，第一晶片15与第二晶片25为具有相同功能的晶片，因此第一晶片15与第二晶片25的厚度、大小为相同。在此实施例中，第一晶片15与第二晶片25相对应的介电层13与电隔离层 23亦可为相同的材料及厚度。再者，至少一第一导电柱14间的间距亦可与至少一第二导电柱24间的间距相同，此时第一导电柱14及第二导电柱24的长度与直径亦可相同。
如图5所示，贯穿孔31形成于中介层30中。在此实施例中，中介层30的材质例如可为硅晶圆，贯穿孔31的孔径因应于第一导电柱14与第二导电柱24的位置及直径或宽度而调整，因此贯穿孔31彼此之间具有差异。然而在其他实施例(图未示)中，贯穿孔31亦可设计于具有相同的孔径。
于贯穿孔31形成步骤中，贯穿孔31对齐于第一导电柱14与第二导电柱24，以供第一导电柱14与第二导电柱24容置于贯穿孔31内。
如图5所示，中介层30的厚度不大于第一导电柱14与第二导电柱24的长度。具体而言，中介层30的厚度不大于第一导电柱14与第二导电柱24分别扣掉介电层13与电隔离层23的长度。
如图6所示，第一晶片15及第二晶片25设置于中介层30上。使第一导电柱14与第二导电柱24分别设置于贯穿孔31内。具体而言，设置电隔离层23及介电层13于中介层30的另一面33，亦即是第一晶片15与第二晶片25相对于中介层30之间的表面33上。在另一可行的实施例中，电隔离层23及介电层13例如为一粘晶胶，使第一晶片15与第二晶片25可先行粘置于中介层30上，作为初步的定位。
如图7所示，进行一封装作业，使封装层40覆盖于第一晶片15及第二晶片25上。换言之，封装层40覆盖于第一晶圆10、第二晶圆20及部分的中介层30上。具体而言，第一晶圆10包含一底面12而第二晶圆20包含一下表面22，封装层40主要覆盖于底面12及下表面22上。封装层40的覆盖可协助将第一晶片15及第二晶片25固定于中介层30上，因此对于中介层30的下层的进一步制程时，并不会因为将中介层30翻面而导致第一晶片15及第二晶片25脱离中介层30。
如图8所示，涂布一第一电绝缘层50于中介层30的一表面32。由于贯穿孔31与第一导电柱14及第二导电柱24之间具有间隔，因此第一电绝缘层50位于贯穿孔31附近的区域会下陷沈入贯穿孔31中填充涂布后，再利用一道光刻制程使第一导电柱14与第二导电柱24局部显露出来，以供后续电性连接。是故，由于电隔离层23及介电层13与第一电绝缘层50的存在，使得中介层30的上层不会电性短路于中介层30的下层。
如图9所示，沉积(或电镀)一图案化的线路重布层60于第一电绝缘层50上。由于第一电绝缘层50并无覆盖第一导电柱14与第二导电柱24，因此线路重布层60电性连接第一导电柱14与第二导电柱24。如图10所示，涂布一第二电绝缘层70于第一电绝缘层50与线路重布层60上，再利用一道光刻制程，使部份的线路重布层60露出。具体而言，第二电绝缘层70可全面覆盖线路重布层60仅暴露出后续需与外部端子(例如是锡球)连接的区域，藉以透过第二电绝缘层70保护线路重布层60避免氧化。
如图11所示，设置一锡球80于暴露出的部分线路重布层60上，进而完成晶圆级封装结构。
本发明的技术内容及技术特点已揭示如上，然而本发明所属技术领域中具有通常知识者应了解，在不背离后附权利要求书所界定之本发明精神和范围内，本发明的教示及揭示可作种种之替换及修饰。例如，上文揭示之许多装置或结构可以不同之方法实施或以其它结构予以取代，或者采用上述二种方式的组合。
附图标记说明
。

Claims (12)

1.一种晶圆级封装方法，包含：
提供一第一晶圆，其包含一表面，其中一介电层及一第一导电柱于该表面上，且该第一导电柱穿透该介电层；
切割该第一晶圆而形成一第一晶片；
形成一贯穿孔于一中介层，其中该中介层包含一第一表面及一相对于该第一表面的第二表面，该中介层的厚度不大于该第一导电柱的长度；
设置该第一晶片于该中介层的该第一表面且设置该第一导电柱于该贯穿孔；
覆盖一封装层于该第一晶片及部份的中介层上；
涂布一第一电绝缘层于该中介层的该第二表面上；
形成一线路重布层于该第一电绝缘层上，其中该线路重布层电性连接该第一导电柱；以及
设置一锡球于该线路重布层上。
2.根据权利要求1所述的封装方法，进一步包含步骤：涂布一第二电绝缘层于该线路重布层及该第一电绝缘层上。
3.根据权利要求1所述的封装方法，其中该贯穿孔形成步骤包含对齐该贯穿孔于该第一导电柱的步骤。
4.根据权利要求1所述的封装方法，进一步包含步骤：
提供一第二晶圆，其包含一上表面，其中一电隔离层及一第二导电柱于该上表面上，且该第二导电柱穿透该电隔离层。
5.根据权利要求4所述的封装方法，进一步包含步骤：切割该第二晶圆而形成一第二晶片。
6.根据权利要求5所述的封装方法，其中该第一晶圆包含一底面，而该第二晶圆包含一下表面，于封装层覆盖步骤中另包含覆盖该封装层于该底面及该下表面上的步骤。
7.根据权利要求6所述的封装方法，其中该介电层的厚度等于该电隔离层的厚度。
8.根据权利要求4所述的封装方法，进一步包含步骤：设置该电隔离层及该介电层于该中介层的另一面上。
9.根据权利要求4所述的封装方法，进一步包含步骤：设置该第二导电柱于该贯穿孔。
10.根据权利要求5所述的封装方法，进一步包含步骤：覆盖一封装层于该第二晶片及部份的中介层上。
11.根据权利要求4所述的封装方法，其中该线路重布层形成步骤包含电性连接该线路重布层于该第二导电柱的步骤。
12.一种晶圆级封装结构，包含：
一第一晶片，包含一表面，其中一介电层及一第一导电柱设置于该表面上，且该第一导电柱穿透该介电层；
一中介层具有一第一表面、一相对于该第一表面的第二表面及至少一贯穿孔，其中该中介层的厚度不大于该第一导电柱的长度；
该第一晶片设置于该中介层的该第一表面上，使该第一导电柱设置于该贯穿孔中；
一封装层覆盖于该第一晶片及部份的中介层上；
一第一电绝缘层设置于该中介层的该第二表面上；
一线路重布层设置于该第一电绝缘层上，其中该线路重布层电性连接该第一导电柱；以及
一锡球连接于该线路重布层上。
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