CN203085525U - 可用于堆叠的集成电路 - Google Patents

可用于堆叠的集成电路 Download PDF

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Publication number
CN203085525U
CN203085525U CN201220625573XU CN201220625573U CN203085525U CN 203085525 U CN203085525 U CN 203085525U CN 201220625573X U CN201220625573X U CN 201220625573XU CN 201220625573 U CN201220625573 U CN 201220625573U CN 203085525 U CN203085525 U CN 203085525U
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wafer
integrated circuit
semiconductor wafer
opening
front surface
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P·巴尔
S·若布洛
N·奥特利尔
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STMicroelectronics SA
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STMicroelectronics SA
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Abstract

本申请涉及可用于堆叠的集成电路，其具有能够被放置在另一集成电路、印刷电路或者封装上的表面，并且具有能够接收附加集成电路的另一表面，通过形成装配的芯片的划片获得的集成电路包括：第一半导体晶片，具有厚度小于10μm的衬底，第一半导体晶片的前表面包括在有源区中的部件的掺杂区域并且支持互连层，第一晶片包括填充有传导材料的贯通绝缘开口；第二半导体晶片，其支持绝缘层的前表面被放置以抵靠第一晶片的支持互连层的前表面，并且使其后表面支持包括接触区域的再分布层，第二晶片包括多个通过孔但是不包括部件；以及铜柱，能够接收来自附加集成电路的接触，被附接至在第一晶片的后表面侧上的填充有传导材料的开口。

Description

可用于堆叠的集成电路
相关申请的交叉引用
本申请要求于2011年12月2目提交的法国专利申请号11/61066的优先权权益，在法律允许的最大程度内通过引用将该申请结合于此。 
技术领域
本公开涉及一种可用于堆叠的集成电路，并且更具体地，涉及可用于堆叠的如下集成电路芯片，该集成电路芯片的前表面及其后表面借助于穿过晶片的过孔而电连接。 
背景技术
为了改进集成电路的紧凑性及性能，期望向半导体晶片(或者半导体衬底)的后表面转移对在该半导体晶片的前表面上制造的部件的连接。为了实现这一目的，应当形成在现有技术中当前指定为TSV(衬底通孔)的形成晶片的过孔。此类过孔包括作为良好电导体和/或热导体的一个或者若干材料。 
为了限制待穿过的衬底的厚度，形成包括TSV类型过孔的集成电路通常导致操纵非常小厚度的半导体晶片。这在晶片和在集成电路中产生高机械应力。此外，为了限制在晶片的形成部件的侧上的可用区域的损失，期望形成截面尽可能小的过孔。因而，期望形成具有高形状因数的过孔，过孔的形状因数被定义为过孔的深度与该过孔的宽度的比率。 
通常，当前使用的技术能够容易地制造形状因数的范围在1和10之间的过孔。对于厚度的数量级为80μm的薄晶片，可能易于制造的最小过孔宽度因此大约为8μm。对于基本有源部件的维度小于 1微米、或者甚至小于十分之一微米的技术而言，此类宽度相对于所制造部件(主要是晶体管)的维度而言是非常大的。一般专用于部件制造的半导体晶片的表面的部分因此被牺牲用于通孔的制造。因而，提供过孔可以导致每表面面积单位的部件密度下降。 
为了降低通过孔的宽度，晶片因而应该变得尽可能地薄。大直径的晶片(例如，具有300mm直径的晶片)通常的初始厚度范围大约从700至800μm，在经过减薄之后，该晶片变得易碎并且难以操纵。因而，晶片的前表面被粘合至临时分选机(temporary handle)，即，粘合至另一较厚晶片，在此之后，晶片被减薄。继而，从晶片的新的后表面形成开口，在此之后，开口的侧壁和底部由传导材料层所覆盖。为了在开口的侧壁和底部上获得传导材料的保形沉积，应该使用高温。当前，用于临时粘合晶片的粘合剂不能承受高于大约250℃的温度。此类方法的不利之处在于如下事实：它们可能受限于简化过孔制造，其中该过孔具有通常范围在1和3之间的受限的形状因数。 
根据另一已知方法，为了改进过孔的形状因数，在将晶片临时粘合至分选机上之前、并且在减薄晶片之前形成通过孔。然而，由于晶片的期望最终厚度通常为80μm的数量级，因此这样的方法的不利之处在于价格高昂的过孔填充。 
上述方法的另一不利之处在于，一旦分选机被去除，则晶片是易碎的。继而在后续的封装步骤中难以操纵晶片。因而，以此方法，难以获得厚度小于大约80μm的晶片，并且因而获得宽度小于8μm的过孔。 
因而，需要一种能够通过具有最小可能宽度的过孔，来向半导体晶片的后表面转移对在半导体晶片的前表面上制造的部件的连接的方法。 
实用新型内容
为了克服上述技术问题中的至少一些，本实用新型的一个实施方 式提供了一种可用于堆叠的集成电路，所述集成电路具有能够被放置在另一集成电路、印刷电路或者封装上的表面，并且所述集成电路具有能够接收附加集成电路的另一表面，通过形成装配的芯片的划片获得的所述集成电路包括： 
第一半导体晶片，具有厚度小于10μm的衬底，所述第一半导体晶片的前表面包括在有源区中的部件的掺杂区域并且支持互连层，所述第一晶片包括填充有传导材料的贯通绝缘开口； 
第二半导体晶片，通过热压键合或者直接键合，使其支持绝缘层的前表面被放置以抵靠所述第一晶片的支持互连层的所述前表面，并且使其后表面支持包括接触区域的再分布层，所述第二晶片包括多个通过孔但是不包括部件；以及 
铜柱，能够接收来自附加集成电路的接触，被附接至在所述第一晶片的所述后表面侧上的填充有传导材料的所述开口。 
优选地，所述第一晶片的所述衬底的厚度范围在3和10μm之间，并且小于所述开口的深度，并且其中所述开口的宽度小于1μm。 
优选地，所述第一晶片进一步包括：填充有绝缘材料的第二贯通开口，能够完全将有源区绝缘。 
优选地，所述第二晶片的所述衬底的厚度范围在80和350μm之间，并且其中所述通孔的宽度范围在8和50μm之间。 
优选地，用于填充所述开口的材料选自包括以下的组：多晶硅、钨和铜，以及用于填充所述第二开口的材料是氧化硅。 
使用上述技术方案，可以实现如下技术效果：具有最小可能宽度的过孔，来向半导体晶片的后表面转移对在半导体晶片的前表面上制造的部件的连接。 
结合附图，在下文具体实施方式的非限定性描述中，将详细讨论上述和其他特征和优势。 
附图说明
图1A至图1K是示出用于形成集成电路的方法的连续步骤的截 面视图；以及 
图2是两个堆叠集成电路(以三维(3D)形式)的装配的截面视图，此装配通过诸如结合图1A至图1K所描述的方法来获得。 
为清楚起见，在不同的附图中，相同的元件被指定为相同的参考数字，进一步，像往常一样，在集成电路的表示中，各个附图不必依比例绘制。 
具体实施方式
图1A至图1K是示意性地示出用于形成集成电路的方法的连续步骤的截面视图。 
图1A示出了半导体晶片W1，其中已经从前表面3形成了开口1。开口的深度小于晶片厚度。例如，晶片厚度范围在650和750μm之间(例如，700μm)，而开口的深度小于10μm。开口例如具有环形截面。开口1的直径(或者宽度)例如小于1μm。 
在形成开口1之后，开口的侧壁被覆盖有绝缘材料，在此之后，如图1B中所示，开口由传导材料5完全填充，传导材料5例如是多晶硅或者钨。因而获得非常小宽度的过孔7。 
如图1C中所示，下一步骤包括在过孔7没有占据的位置处的、在靠近晶片W1的前表面的有源区9中形成部件的掺杂区域。优选地，在过孔7的边缘和掺杂区域的界限之间提供例如1μm数量级的确定区域。 
根据变体，可以首先形成部件的掺杂区域，并且继而形成开口1。用于填充开口的传导材料5继而可以例如是多晶硅、钨或者铜。 
继而，在晶片W1的前表面上形成互连层11。表面金属化13示出为一个示例，以及中间层的金属化也是示例。互连层11的上表面由此被平坦化(1evel)，例如通过化学-机械抛光进行。 
在图1D中示出的步骤中，另一晶片W2的前表面19(例如，相同半导体的、与晶片W1相同维度的)被覆盖有绝缘体层17。在此步骤中，传导接触21(例如，由铜制造)可以在绝缘体层17的表面 处形成。绝缘体层17的上表面继而被平坦化，例如通过化学-机械抛光进行。 
如图1E中所示，下一步骤包括将涂敷有绝缘体层17的晶片W2的前表面施加在晶片W1的支持互连层11的前表面上。施加为彼此抵靠的两个晶片的表面先前已被处理并被平坦化，以在晶片W1和W2之间执行热压缩键合或者直接键合。此外，已经在图1D中示出的步骤中在绝缘体层17的表面处形成的每个接触21变得与晶片W1的表面金属化13相接触。 
在图1F中示出的步骤中，晶片W2被减薄，从而使得晶片W2在减薄之后的厚度例如在80和350μm之间，例如，在300μm的数量级。此类厚度能够在无需使用临时分选机的情况下确保晶片W2的足够的机械完整性。 
在已经将晶片W2减薄之后，如图1G中所示，从晶片W2的新的后表面形成开口23以到达晶片W1的互连层，图中示出了一个单一的开口。开口23的底部例如与连接到表面金属化13的接触21重合，或者与表面金属化直接重合。开口23的直径在8和50μm之间，例如在35μm的数量级。层25的开口23的侧壁继而被覆盖有绝缘材料。继而，沉积传导材料层26，传导材料层26覆盖开口的侧壁和底部，并且变得与导体21或者表面金属化13相接触。根据一个实施方式，层26可以是键合层，例如，由Ti、TiN、Ta、TaN或者Cu制造。继而，在晶片W2的后表面和传导层26的表面图案上形成绝缘体层28。绝缘体层28可以是开放的，以便使得传导层26在局部可访问。根据一个优选实施方式，在形成开口23之前，第一绝缘体层22可以在晶片W2的后表面之上形成，此绝缘体层22旨在保护晶片W2的后表面。最后，在晶片W2的后表面之上，获得由绝缘体层22和28形成并且包括传导层26的表面图案的绝缘体层29。 
如图1H中所示，下一步骤包括利用材料31完全填充开口23。材料31可以是诸如传导膏的传导材料(例如，基于铜)或者诸如聚酯亚胺的绝缘材料。传导材料26和材料31形成通孔33。再分布层 30可以在绝缘体层29之上进一步形成，此再分布层包括传导层26的表面图案之上的接触区域34。接触区域34旨在接收用于表面(倒装芯片)装配的传导焊球或者铜柱。 
如图1I中所示，在已经形成通孔33之后，晶片W1被减薄以便在减薄之后晶片W1的厚度小于过孔7的深度，并且过孔的末端被暴露。晶片W1在减薄之后的厚度例如范围在3和10μm之间，例如在5μm的数量级。继而，优选地，在晶片W1的新的后表面上沉积薄绝缘体层35。 
在本方法的这一阶段，在不更改晶片W1和W2或者所形成的集成电路的机械完整性的情况下，因而通过晶片W1中的非常小宽度的通孔7，并且通过不包括部件的晶片W2中的较大宽度的通孔33，已经将对在晶片W1的前表面上制造的部件的连接转移至晶片W2的后表面。 
如图1J中所示，绝缘体层35在每个过孔7前面是开放的，并且从晶片W1的过孔7形成铜柱37。柱37的宽度例如在20μm的数量级。柱27例如旨在接收来自另一集成电路芯片的接触。 
如图1K中所示，传导焊球41被附接至晶片W2的后表面的再分布层30的接触区域34。在此操作期间，晶片W1的后表面可以被涂敷有临时保护层39。保护晶片W1的后表面的另一方式是借助于支撑来提升晶片，以避免后表面与用于重新熔融焊球的熔炉的带相接触。焊球41例如旨在被焊接至封装或者印刷电路板的另一芯片的焊盘。 
以此获得的装配包括：厚度小于10μm的晶片W1以及厚度范围例如在80和350μm之间的较厚晶片W2。晶片W1包括在其前表面侧上的有源区9中的部件、以及宽度小于1μm并穿过半导体衬底的过孔7。晶片W1的前表面支持互连层11，并且铜柱37被附接至后表面侧上的通孔7。晶片W2的涂敷有绝缘体层17的前表面被放置以抵靠晶片W1的支持互连层11的前表面。晶片W2包括通孔33，例如宽度范围在8和50μm之间。晶片W2的后表面可以支持包括 被附接至传导焊球41的接触区域34的再分布层30。 
在图1K中示出的状态中的被彼此抵靠地放置的晶片W1和W2继而被划片为芯片，优选地在它们被粘合至临时保护层39时进行。 
图2示出了此类集成电路芯片42的部分。芯片42的焊球41已经被焊接至另一芯片、封装或者印刷电路板43的焊盘。另一集成电路芯片45的接触已经被附接至铜柱37。芯片45不必与芯片42具有相同的尺寸。因而获得彼此相堆叠的两个集成电路42、45的装配(在三维(3D)中)。 
由诸如关于图1A至图1K描述的方法获得的集成电路的优势在于如下事实：包括半导体部件的晶片W1可以非常薄——厚度小于10μm。因而，通过较小宽度(例如小于1μm)的过孔，对于在晶片W1的前表面上制造的部件的连接被转移至其后表面。对于其中基本部件维度小于1微米甚至小于十分之一微米的技术而言，此类宽度相对于部件维度是相当可接受的。此外，以此限制了在部件上的过孔的机械影响并降低了寄生电耦合。 
诸如图2中所示的集成电路的附加优势在于：对于前表面的附加访问可以由在抵靠晶片W1放置的另一晶片W2中形成的通孔33来提供。晶片W2中的过孔具有不可忽略的直径，这确保了对由在晶片W1中操作的部件生成的热进行良好的散热。此外，通常由铜制成的对应于金属化13、15并且具有高密度的互连层11(在本领域中称为BEOL“线路后端”)继而位于部件之下，并且可以被优化以改进集成电路的散热。 
诸如关于图1A至图1K所述的方法的优势在于，能够不使用将集成电路的支持部件的前表面粘合至临时分选机并从其分离的任何步骤。由于不存在粘合剂，在图1G和图1H中示出的、在晶片W2中形成通孔33的步骤中可以使用高温。因而可以形成在两种情形中具有降低制造约束的、高形状因数的、完全填充或者不被填充的通孔33。 
此类方法的优势在于，其特别适用于在将晶片W1和W2进行键 合的直接键合技术中使用。这是由于晶片W2不包括部件和集成电路的事实。如果晶片W2的前表面在有源区中还具有部件，则在晶片键合步骤中应当考虑由两个晶片的相应有源区占据的表面区域中的约束。 
此类方法的附加优势在于，在图1A中示出的形成开口1的步骤中，还可以形成旨在用作有源区之间的绝缘区域的其他开口51。在图1B中所示的步骤中，开口51例如可以是填充有绝缘材料(例如，氧化硅)53的沟槽。例如，在图1C中已经示出了在两个沟槽51之间形成的有源区59填充有绝缘材料53。由于支持部件的晶片W1的厚度在减薄之后小于填充有绝缘体53的沟槽51的深度，因此如图1I中所示，位于两个沟槽51之间的有源区59被完全隔离。继而，改进了此类有源区的部件或者部件的组、在其有源或者无源时的性能。 
已经描述了特定实施方式。本领域技术人员可以进行各种调整、修改和改进。特别是，可以在关于图1A至图1K所述的方法的开始处，在开口1之前形成部件的掺杂区域。 
此类调整、修改和改进旨在作为本公开的一部分，并且旨在落在本实用新型的精神和范围之内。因而，上述说明书仅出于示例方式而并不旨在进行限制。本实用新型仅由如下文的权利要求书及其等效项所定义的进行限制。 

Claims (5)

1.一种可用于堆叠的集成电路，其特征在于，所述集成电路具有能够被放置在另一集成电路、印刷电路或者封装上的表面，并且所述集成电路具有能够接收附加集成电路的另一表面，通过形成装配的芯片的划片获得的所述集成电路包括：
第一半导体晶片，具有厚度小于10μm的衬底，所述第一半导体晶片的前表面包括在有源区中的部件的掺杂区域并且支持互连层，所述第一晶片包括填充有传导材料的贯通绝缘开口；
第二半导体晶片，通过热压键合或者直接键合，使其支持绝缘层的前表面被放置以抵靠所述第一晶片的支持互连层的所述前表面，并且使其后表面支持包括接触区域的再分布层，所述第二晶片包括多个通过孔但是不包括部件；以及
铜柱，能够接收来自附加集成电路的接触，被附接至在所述第一晶片的所述后表面侧上的填充有传导材料的所述开口。
2.根据权利要求1所述的集成电路，其特征在于，所述第一晶片的所述衬底的厚度范围在3和10μm之间，并且小于所述开口的深度，并且其中所述开口的宽度小于1μm。
3.根据权利要求1所述的集成电路，其特征在于，所述第一晶片进一步包括：填充有绝缘材料的第二贯通开口，能够完全将有源区绝缘。
4.根据权利要求1所述的集成电路，其特征在于，所述第二晶片的所述衬底的厚度范围在80和350μm之间，并且其中所述通孔的宽度范围在8和50μm之间。
5.根据权利要求3所述的集成电路，其特征在于，用于填充所述开口的材料选自包括以下的组：多晶硅、钨和铜，以及用于填充所述第二开口的材料是氧化硅。
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