CN103918067B - 半导体模块及其制造方法 - Google Patents

半导体模块及其制造方法 Download PDF

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Publication number
CN103918067B
CN103918067B CN201380003744.2A CN201380003744A CN103918067B CN 103918067 B CN103918067 B CN 103918067B CN 201380003744 A CN201380003744 A CN 201380003744A CN 103918067 B CN103918067 B CN 103918067B
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mentioned
source electrode
copper connector
bare chip
gate electrode
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CN103918067A (zh
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须永崇
金子昇
三好修
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NSK Ltd
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NSK Ltd
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Abstract

提供对于晶体管裸芯片的电极和基板上的布线图案之间的接合，通过构成为利用焊锡封装作业进行，从而能够通过与在将晶体管裸芯片或其他表面封装部件封装于基板上的布线图案上时进行的焊锡封装作业相同的工序进行的半导体模块及其制造方法。半导体模块(30)包括：形成于绝缘层(32)上的多个布线图案(33a)～(33d)；通过焊锡(34a)封装于多个布线图案(33a)～(33d)中的一个布线图案(33a)上的晶体管裸芯片(35)；用于通过焊锡(34b)、(34c)将形成于晶体管裸芯片(35)的上表面的电极(S)、(G)与多个布线图案(33a)～(33d)中的其他布线图案(33b)、(33c)接合的、由铜板构成的铜连接器(36a)、(36b)。

Description

半导体模块及其制造方法
技术领域
本发明涉及安装于汽车用电气设备的功率模块等半导体模块及其制造方法。
背景技术
近来，汽车等车辆中的各种电气设备的控制中逐渐引入了电子装置。作为安装有电子装置的电气设备的一例，在电动助力转向装置中，在收容与汽车的转向相关的电动马达的壳体内设置有马达驱动部，将电子装置搭载于该马达驱动部。该电子装置作为功率模块安装于马达驱动部。
功率模块作为适于电动助力转向装置那样的以比较大的电流驱动的电气设备的控制、例如搭载了FET(Field Effect Transistor，场效应晶体管)、IGBT(Insulated GateBipolar Transistor，绝缘栅双极性晶体管)等功率元件的所谓的半导体模块而构成。这种功率模块由于搭载于车辆故也被称作车载模块(In-vehicle Module，车载模块)。
以往，作为这种半导体模块，例如已知图14所示的半导体模块(参照专利文献1)。图14是以往的半导体模块的一例的截面示意图。
图14所示的半导体模块100包括金属制的基板101、设置于基板101的凹部的底部平坦面上的树脂102、以及形成于树脂102上的多个铜箔(布线图案)103a、103b、103c、103d。在铜箔103a及铜箔103c与铜箔103d之间形成有槽109。而且，在多个铜箔103a、103b、103c、103d中的铜箔103a、103b之上分别形成有热缓冲板104a、104b，在热缓冲板104a、104b上分别形成有IGBT105a、105b。各IGBT105a、105b是IGBT裸芯片(晶体管裸芯片)。
而且，利用由金属线构成的布线106a将IGBT105a的发射极和铜箔103b接合，另外，同样利用由金属线构成的布线106b将IGBT105b的发射极和铜箔103c接合。
另外，利用凝胶107将树脂102、铜箔103a、103b、103c、热缓冲板104a、104b、IGBT105a、105b以及布线106a、106b封入。另外，将基板101的凹部覆盖的盖108固定于基板101的上部。
另外，作为以往的半导体模块的其他例，例如已知图15所示(参照专利文献2)的半导体模块。图15是表示以往的半导体模块的其他例的俯视示意图。
在图15所示的半导体模块200中，在基板(未图示)上形成有多个导电焊盘201、202。而且，在多个导电焊盘201、202中的一个导电焊盘201上焊锡连接有MOS芯片203。另外，在MOS芯片203的上表面形成有多个源电极205及单一的栅电极204，在MOS芯片203的下表面形成有未图示的漏电极。
而且，利用引线210将MOS芯片203的源电极205和形成于基板上的多个导电焊盘201、202中的其他导电焊盘202相互接合。引线210是通过对金属板进行冲压及弯曲加工而形成的，包括：沿图15所示的Ｘ方向及Ｙ方向(水平方向)延伸的矩形平板状的源电极接合部211；沿Ｘ方向及Ｙ方向延伸的平板状的电极接合部212；以及将源电极接合部211和电极接合部212连接的向Ｚ方向(上下方向)倾斜的连结部213。在此，源电极接合部211与MOS芯片203的源电极205软钎焊接，另外，电极接合部212与基板上的多个导电焊盘201、202中的其他导电焊盘202软钎焊接。
而且，源电极接合部211的Ｘ方向的宽度a在多个源电极205的Ｘ方向的宽度b以上。由此，可以防止源电极205中的不均匀的焊料浸润和该焊锡的回流引起的相对于该源电极205的位置错位。
在先技术文献
专利文献
专利文献1：日本特开2004-335725号公报
专利文献2：日本特开2007-95984号公报
发明内容
发明要解决的问题
但是，这些以往的图14所示的半导体模块100及图15所示的半导体模块200存在以下的问题点。
即，在图14所示的半导体模块100的情况下，对于IGBT105a的发射极和铜箔103b之间的接合及IGBT105b的发射极和铜箔103c之间的接合，是使用由金属线构成的布线106a、106b进行接合。对于使用了该金属线的接合，存在以下的问题：由于使用线接合装置(未图示)来进行，所以封装布线106a、106b的作业与将IGBT105a、 105b和其他表面封装部件封装于基板上的布线图案上时进行的焊锡封装作业不同，制造工序成为不同的工序。若基于线接合的封装作业与焊锡封装作业不同而需要另外的制造工序，则存在制造节拍变长，并且需要线接合的专用设备而使制造成本变高的问题。
另外，在图15所示的半导体模块200的情况下，接合于源电极205的引线210的引出方向只是图15所示的Ｙ方向，另一方面，对于接合于栅电极204的引线没有任何记载。在此，若接合于源电极205的引线210的引出方向只是一个方向，则没有封装于基板上的MOS芯片203的配置自由度，没有基板上的布线的设计自由度。由于没有该基板上的布线的设计自由度，从而存在不能使基板上的半导体模块的布局紧凑之类的问题。另外，若接合于源电极205的引线210的引出方向只是一个方向，则存在如下问题：难以使基板上的三相马达的各相的路径的长度相同，从而各相的阻抗特性不同，难以使三相马达的各相特性一致。
因此，本发明是为了解决上述的问题点而完成的，其目的在于提供对于晶体管裸芯片的电极和基板上的布线图案之间的接合，通过构成为利用焊锡封装作业进行，从而能够通过与在将晶体管裸芯片或其他表面封装部件封装于基板上的布线图案上时进行的焊锡封装作业相同的工序进行的半导体模块及其制造方法。
另外，本发明的其他的目的在于，提供使封装于基板上的晶体管裸芯片的配置及基板上的布线的设计具有自由度，可以使基板上的半导体模块的布局紧凑，并且能够容易使基板上的三相马达的各相的路径的长度相同的半导体模块及其制造方法。
用于解决问题的方案
为了解决上述问题，本发明的某一形态的半导体模块，其特征在于，包括：金属制的基板；形成于该基板之上的绝缘层；形成于该绝缘层上的多个布线图案；通过焊锡封装于该多个布线图案中的一个布线图案上的晶体管裸芯片；以及用于通过焊锡将形成于该晶体管裸芯片的上表面的电极和上述多个布线图案中的其他布线图案进行接合的、由铜板构成的铜连接器。
根据该半导体模块，通过使用由铜板构成的铜连接器，利用焊锡封装作业进行晶体管裸芯片的电极和基板上的布线图案之间的接合。因此，可以通过与在将晶体管裸芯片或其他表面封装部件封装于基板上的布线图案上时进行的焊锡封装作业相同的工序，进行晶体管裸芯片的电极和基板上的布线图案之间的接合。由此，可以缩短半 导体模块的制造节拍，并且不需要线接合的专用设备，可以降低半导体模块的制造成本。即，由于也能够利用焊锡封装作业用的设备进行晶体管裸芯片的电极和基板上的布线图案之间的接合，所以可以抑制设备投资。并且，也能够同时进行将晶体管裸芯片或其他表面封装部件封装于基板上的布线图案上的工序和进行晶体管裸芯片的电极和基板上的布线图案之间的接合的工序。
此外，铜板及铜连接器分别地可以是具有与铜同样的电气、机械特性的材质的板状部件，和具有与铜同样的电气、机械特性的材质的连接器，但是，由于工业上质量稳定的物品容易比较便宜地得到，所以优选使用铜板、铜连接器。
另外，在该半导体模块中，上述晶体管裸芯片是在上表面形成有源电极及栅电极的FET裸芯片，上述铜连接器包括源电极用铜连接器和栅电极用铜连接器，利用上述源电极用铜连接器通过焊锡使上述FET裸芯片的源电极上和上述多个布线图案中的其他布线图案上接合，利用上述栅电极用铜连接器通过焊锡使上述FET裸芯片的栅电极上和上述多个布线图案中的另外其他布线图案上接合。
根据该半导体模块，通过对FET裸芯片的源电极和基板上的布线图案之间的接合使用源电极用铜连接器，对FET裸芯片的栅电极和基板上的另外的布线图案之间的接合使用栅电极用铜连接器，从而能够通过焊锡封装作业进行，所以可以通过与在将FET裸芯片或其他表面封装部件封装于基板上的布线图案上时进行的焊锡封装作业相同的工序，进行FET裸芯片的源电极和基板上的布线图案之间的接合及FET裸芯片的栅电极和基板上的另外的布线图案之间的接合。
另外，在该半导体模块中，上述栅电极用铜连接器为一种，上述源电极用铜连接器是相对于上述栅电极用铜连接器进行180°直线配置的第一源电极用铜连接器和相对于上述栅电极用铜连接器进行90°直角配置的第二源电极用铜连接器的这两种连接器，在一个FET裸芯片中，将上述一种的栅电极用铜连接器与从上述两种连接器即第一源电极用铜连接器及第二源电极用铜连接器中选择的任意一方的源电极用铜连接器组合进行使用。
根据该半导体模块，封装于基板上的晶体管裸芯片的配置上产生自由度，基板上的布线的设计自由度增大，可以使基板上的半导体模块的布局紧凑，并且可以容易地使基板上的三相马达的各相的路径的长度相同。由此，可以容易地使三相马达的各相特性、特别是各相的阻抗特性一致，能够提高转矩和速度等的脉动精度。
另外，在该半导体模块中，形成于上述FET裸芯片的上表面的上述栅电极和上述源电极被串联直线配置，上述源电极形成为长方形状。
并且，优选，在该半导体模块中，上述第一源电极用铜连接器沿着上述形成为长方形状的源电极的短边所延伸的方向引出，并且具备接合部，该接合部具有沿着该源电极的短边及长边的短边及长边且与上述源电极接合的接合面的面积是与上述源电极大致相同的面积。
根据该半导体模块，可以确保相对于栅电极用铜连接器进行180°直线配置的第一源电极用铜连接器和形成在FET裸芯片上表面的源电极之间的接合可靠性。
另外，优选，在该半导体模块中，上述第二源电极用铜连接器沿着上述形成为长方形状的源电极的长边所延伸的方向引出，并且具备接合部，该接合部具有沿着该源电极的长边及短边的长边及短边且与上述源电极接合的接合面的面积与上述源电极大致相同。
根据该半导体模块，可以确保相对于栅电极用铜连接器进行90°直角配置的第二源电极用铜连接器和在FET裸芯片的上表面形成的源电极之间的接合可靠性。
并且，本发明的某个形态的半导体模块的制造方法，其特征在于，包括：在金属制的基板上形成绝缘层的工序；在该绝缘层上形成多个布线图案的工序；在该多个布线图案上涂敷焊锡膏的工序；在涂敷于上述多个布线图案中的一个布线图案上的焊锡膏上搭载晶体管裸芯片的工序；在形成于上述晶体管裸芯片的上表面的电极上涂敷焊锡膏的工序；在涂敷于上述晶体管裸芯片的电极上的焊锡膏上及涂敷于上述多个布线图案中的其他布线图案上的焊锡膏上，搭载由铜板构成的铜连接器而构成半导体模块中间组装体的工序；以及将该半导体模块中间组装体放入回流炉并进行如下的接合的工序，即通过焊锡将上述多个布线图案中的一个布线图案和上述晶体管裸芯片接合、通过焊锡将形成在上述晶体管裸芯片上表面的电极和上述铜连接器接合、以及通过焊锡将上述多个布线图案中的其他布线图案和上述铜连接器接合。
根据该半导体模块的制造方法，与上述的半导体模块同样，对于晶体管裸芯片的电极和基板上的布线图案之间的接合，通过使用由铜板构成的铜连接器，从而能够通过焊锡封装作业进行，所以可以通过与在将晶体管裸芯片或其他表面封装部件封装于基板上的布线图案上时进行的焊锡封装作业相同的工序进行晶体管裸芯片的电极和基板上的布线图案之间的接合。因此，可以缩短半导体模块的制造节拍，并且不需要 线接合的专用设备，可以降低半导体模块的制造成本。
另外，在该半导体模块的制造方法中，上述晶体管裸芯片是在上表面形成有源电极及栅电极的FET裸芯片，上述铜连接器包括源电极用铜连接器和栅电极用铜连接器，该半导体模块的制造方法包括：在金属制的上述基板上形成上述绝缘层的工序；在该绝缘层上形成多个布线图案的工序；在该多个布线图案上涂敷焊锡膏的工序；在涂敷于上述多个布线图案中的一个布线图案上的焊锡膏上搭载上述FET裸芯片的工序；在形成于上述FET裸芯片的上表面的源电极及栅电极上涂敷焊锡膏的工序；在涂敷于上述FET裸芯片的源电极上的焊锡膏上及涂敷于上述多个布线图案中的其他布线图案上的焊锡膏上，搭载上述源电极用铜连接器的工序；在涂敷于上述FET裸芯片的栅电极上的焊锡膏上及涂敷于上述多个布线图案中的另外其他布线图案上的焊锡膏上，搭载上述栅电极用铜连接器而构成半导体模块中间组装体的工序；以及将该半导体模块中间组装体放入回流炉并进行如下的接合的工序，即通过焊锡将上述多个布线图案中的一个布线图案和上述FET裸芯片接合、通过焊锡将形成于上述FET裸芯片的上表面的源电极和上述源电极用铜连接器接合、通过焊锡将上述多个布线图案中的其他布线图案和上述源电极用铜连接器接合、通过焊锡将形成于上述FET裸芯片的上表面的栅电极和上述栅电极用铜连接器接合、以及通过焊锡将上述多个布线图案中的另外其他布线图案和上述栅电极用铜连接器接合。
根据该半导体模块的制造方法，与上述的半导体模块同样，通过对FET裸芯片的源电极和基板上的布线图案之间的接合使用源电极用铜连接器，对FET裸芯片的栅电极和基板上的另外的布线图案之间的接合使用栅电极用铜连接器，从而能够通过焊锡封装作业进行，所以可以通过与在将FET裸芯片或其他表面封装部件封装于基板上的布线图案上时进行的焊锡封装作业相同的工序，进行FET裸芯片的源电极和基板上的布线图案之间的接合及FET裸芯片的栅电极和基板上的另外的布线图案之间的接合。
进而，在该半导体模块的制造方法中，上述栅电极用铜连接器为一种，上述源电极用铜连接器是相对于上述栅电极用铜连接器进行180°直线配置的第一源电极用铜连接器和相对于上述栅电极用铜连接器进行90°直角配置的第二源电极用铜连接器的这两种连接器，可以在一个FET裸芯片中，将上述一种的栅电极用铜连接器和从上述两种连接器即第一源电极用铜连接器及第二源电极用铜连接器中选择的任意一方 的源电极用铜连接器组合进行使用。
根据该半导体模块的制造方法，与上述的半导体模块同样，封装于基板上的晶体管裸芯片的配置上产生自由度，基板上的布线的设计自由度增大，可以使基板上的半导体模块的布局紧凑，并且可以容易地使基板上的三相马达的各相的路径的长度相同。由此，可以容易地使三相马达的各相特性、特别是各相的阻抗特性一致，能够提高转矩和速度等的脉动精度。
另外，本发明的另外的形态的半导体模块，其特征在于，对于晶体管裸芯片的电极和基板上的布线图案之间的接合，通过使用由铜板构成的铜连接器，从而通过焊锡封装作业进行。
另外，本发明的又另外的形态的半导体模块，其特征在于，在一个FET裸芯片中，将一种的栅电极用铜连接器与从相对于栅电极用铜连接器进行180°直线配置的第一源电极用铜连接器和相对于上述栅电极用铜连接器进行90°直角配置的第二源电极用铜连接器这两种连接器的第一源电极用铜连接器及第二源电极用铜连接器中选择的任意一方的源电极用铜连接器组合进行使用，以使得在封装于基板上的晶体管裸芯片的配置上产生自由度，增大基板上的布线的设计自由度，可以使基板上的半导体模块的布局紧凑。
发明效果
根据本发明的半导体模块及半导体模块的制造方法，对于晶体管裸芯片的电极和基板上的布线图案之间的接合，通过使用由铜板构成的铜连接器，从而能够通过焊锡封装作业进行，所以可以通过与在将晶体管裸芯片或其他表面封装部件封装于基板上的布线图案上时进行的焊锡封装作业相同的工序进行晶体管裸芯片的电极和基板上的布线图案之间的接合。因此，可以缩短半导体模块的制造节拍，并且不需要线接合的专用设备，可以降低半导体模块的制造成本。
另外，在该半导体模块及半导体模块的制造方法中，当在一个FET裸芯片中，将一种的栅电极用铜连接器和从两种连接器即第一源电极用铜连接器及第二源电极用铜连接器中选择的任意一方的源电极用铜连接器组合进行使用的情况下，封装于基板上的晶体管裸芯片的配置上产生自由度，基板上的布线的设计自由度增大，可以使基板上的半导体模块的布局紧凑，并且可以容易地使基板上的三相马达的各相的路径的长度相同。由此，可以容易地使三相马达的各相特性、特别是各相的阻抗特性一致， 能够提高转矩和速度等的脉动精度。
附图简要说明
图1是表示使用了本发明的半导体模块的电动助力转向装置的基本结构的图。
图2是表示图1所示的电动助力转向装置的控制器的控制***的方框图。
图3是图1所示的电动助力转向装置的包含半导体模块的控制器的分解立体图。
图4是图3所示的半导体模块的俯视图。
图5是用于说明在图3及图4所示的半导体模块中构成晶体管裸芯片的FET裸芯片的电极和基板上的布线图案之间的接合状态的示意图。
图6是用于说明FET裸芯片的电极和铜连接器之间的接合状态的俯视图，(A)是用于说明将栅电极用铜连接器与FET裸芯片的栅电极接合并且将第一源电极用铜连接器与源电极接合的状态的俯视图，(B)是用于说明将栅电极用铜连接器与FET裸芯片的栅电极接合并且将第二源电极用铜连接器与源电极接合的状态的俯视图。
图7是FET裸芯片的概略俯视图。
图8表示栅电极用铜连接器，(A)是从左侧面斜上方观看到的栅电极用铜连接器的状态的立体图，(B)是从右侧面斜上方观看到的栅电极用铜连接器的状态的立体图。
图9表示栅电极用铜连接器，(A)是俯视图，(B)是主视图，(C)是右侧视图，(D)是左侧视图。
图10是从左侧面斜上方观看到的第一源电极用铜连接器的状态的立体图。
图11表示第一源电极用铜连接器，(A)是俯视图，(B)是主视图，(C)是右侧视图，(D)是左侧视图。
图12是从左侧面斜上方观看到的第二源电极用铜连接器的状态的立体图。
图13表示第二源电极用铜连接器，(A)是俯视图，(B)是主视图，(C)是右侧视图，(D)是左侧视图。
图14是以往的半导体模块的一例的截面示意图。
图15是表示以往的半导体模块的其他例的俯视示意图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。图1是表示使用了本发明的半导体模块的电动助力转向装置的基本结构的图。图2是表示图1所示的电动助力转向装置的控制器的控制***的方框图。图3是图1所示的电动助力转向装置的包含半导体模块的控制器的分解立体图。图4是图3所示的半导体模块的俯视图。图5是用于说明在图3及图4所示的半导体模块中构成晶体管裸芯片的FET裸芯片的电极和基板上的布线图案之间的接合状态的示意图。图6是用于说明FET裸芯片的电极和铜连接器之间的接合状态的俯视图，(A)是用于说明将栅电极用铜连接器与FET裸芯片的栅电极接合并且将第一源电极用铜连接器与源电极接合的状态的俯视图，(B)是用于说明将栅电极用铜连接器与FET裸芯片的栅电极接合并且将第二源电极用铜连接器与源电极接合的状态的俯视图。图7是FET裸芯片的概略俯视图。
图1表示使用了本发明的半导体模块的电动助力转向装置的基本结构，在电动助力转向装置中，转向盘1的柱轴2经减速齿轮3、万向接头4A及4B、齿轮齿条机构5与转向轮的拉紧杆6连结。在柱轴2上设置有对转向盘1的转向转矩进行检测的转矩传感器7，辅助转向盘1的转向力的电动马达8通过减速齿轮3而与柱轴2连结。对控制电动助力转向装置的控制器10，从蓄电池(未图示)供给电力，并且经由点火钥匙(未图示)输入点火钥匙信号IGN(参照图2)。控制器10基于由转矩传感器7检测到的转向转矩TS和由车速传感器9检测到的车速V，进行助推(转向辅助)指令的转向辅助指令值的运算，基于运算出的转向辅助指令值控制向电动马达8供给的电流。
控制器10主要由微型计算机构成，其控制装置的机构及构成，如图2所示。
由转矩传感器7检测到的转向转矩TS及由车速传感器9检测到的车速V输入到作为控制运算部的控制运算装置11，将由控制运算装置11运算出的电流指令值输入到栅极驱动电路12。在栅极驱动电路12中基于电流指令值等形成的栅极驱动信号输入到由FET的桥结构所构成的马达驱动部13，马达驱动部13经由非常停止用的切断装置14驱动由三相无刷马达构成的电动马达8。由电流检测电路15来检测三相无刷马达的各相电流，检测出的三相的马达电流ia～ic作为反馈电流输入到控制运算装置11。另外，三相无刷马达中安装有霍尔传感器等旋转传感器16，来自旋转传感器16的旋转信号RT输入到转子位置检测电路17，检测到的旋转位置θ输入到控制运算装置11。
另外，来自点火钥匙的点火信号IGN输入到点火电压监控部18及电源电路部19，从电源电路部19对控制运算装置11输入电源电压Vdd，并且向控制运算装置11输入装置停止用的复位信号RS。而且，切断装置14由对2相进行切断的继电器触点141及142构成。
另外，若对马达驱动部13的电路构成进行说明，则串联连接的FETTr1及Tr2、FETTr3及Tr4、以及FETTr5及Tr6相对于电源线81并联连接。而且，相对于电源线81并联连接的FETTr1及Tr2、FETTr3及Tr4、以及FETTr5及Tr6与接地线82连接。由此，构成逆变器。在此，FETTr1及Tr2中，FETTr1的源电极S和FETTr2的漏电极D串联连接而构成三相马达的c相臂，通过c相输出线91c输出电流。另外，FETTr3及Tr4中，FETTr3的源电极S和FETTr4的漏电极D串联连接而构成三相马达的a相臂，通过a相输出线91a输出电流。进而，FETTr5及Tr6中，FETTr5的源电极S和FETTr6的漏电极D串联连接而构成三相马达的b相臂，通过b相输出线91b输出电流。
接着，图3是图1所示的电动助力转向装置的包含半导体模块的控制器10的分解立体图，控制器10包括外壳20、作为包含马达驱动部13的功率模块的半导体模块30、散热用薄板39、包含控制运算装置11及栅极驱动电路12的控制电路基板40、电力及信号用连接器50、三相输出用连接器60和盖70。
在此，外壳20包括：形成为大致矩形状并用于放置半导体模块30的平板状的半导体模块载置部21；设置于半导体模块载置部21的长度方向端部并用于封装电力及信号用连接器50的电力及信号用连接器封装部22；以及设置于半导体模块载置部21的宽度方向端部并用于封装三相输出用连接器60的三相输出用连接器封装部23。
而且，在半导体模块载置部21形成有旋进用于安装半导体模块30的安装螺钉38的多个螺钉孔21a。另外，在半导体模块载置部21以及电力及信号用连接器封装部22立设有用于安装控制电路基板40的多个安装柱子24，在各安装柱子24形成有旋进用于安装控制电路基板40的安装螺钉41的螺钉孔24a。进而，在三相输出用连接器封装部23形成有旋进用于安装三相输出用连接器60的安装螺钉61的多个螺钉孔23a。
另外，半导体模块30具有上述的马达驱动部13的电路构成，如图4所示，在基板31上封装有6个FETTr1～Tr6、与电源线81连接的正极端子81a、及与接地线82 连接的负极端子82a。另外，在基板31上封装有三相输出部90，该三相输出部90包括与a相输出线91a连接的a相输出端子92a、与b相输出线91b连接的b相输出端子92b以及与c相输出线91c连接的c相输出端子92c。另外，在基板31上封装有包含电容的其他表面封装部件37。并且，在半导体模块30的基板31设置有用于安装半导体模块30的安装螺钉38进行插通的多个贯通孔31a。
在此，对在该半导体模块30中向基板31上封装6个FETTr1～Tr6进行说明。各FETTr1～Tr6由FET裸芯片(晶体管裸芯片)35构成，如图7所示，在FET裸芯片35上具备源电极S和栅电极G，另外，在FET裸芯片35的下表面具有未图示的漏电极。
如图7所示，形成于该FET裸芯片35的上表面的栅电极G和源电极S沿图7中的上下方向被串联直线配置。栅电极G形成为具有沿图7中的上下方向延伸的短边及与该短边正交的长边的长方形状。另外，源电极S形成为具有沿图7中的上下方向延伸的短边及与该短边正交的长边的长方形状。源电极S的短边及长边比栅电极G的短边及长边大，源电极S的面积比栅电极G的面积大。
如图5所示，半导体模块30具备金属制的基板31，在基板31之上形成有绝缘层32。基板31是铝等金属制。另外，在该绝缘层32上形成有多个布线图案33a～33d。各布线图案33a～33d由铜或铝等金属或包含该金属的合金构成。而且，在多个布线图案33a～33d中的一个布线图案33a上通过焊锡34a封装有构成各FETTr1～Tr6的FET裸芯片35。在FET裸芯片35的下表面所形成的漏电极通过焊锡34a与布线图案33a接合。而且，利用源电极用铜连接器36a分别通过焊锡34e、34b使FET裸芯片35的源电极S上和多个布线图案33a～33d中的其他布线图案33b上接合。另外，利用栅电极用铜连接器36b分别通过焊锡34f、34c使FET裸芯片35的栅电极G上和多个布线图案33a～33d中的另外其他布线图案33c上接合。
在此，栅电极用铜连接器36b为一种，在图4中的FETTr1～Tr6的全部，被向图7所示的箭头A方向引出并接合。该情况示于图6(A)、(B)。
另外，源电极用铜连接器36a有如图6(A)所示那样相对于栅电极用铜连接器36b进行180°直线配置的第一源电极用铜连接器36a1与如图6(B)所示那样相对于栅电极用铜连接器36b进行90°直角配置的第二源电极用铜连接器36a2的这两种连接器。而且，第一源电极用铜连接器36a1在图4的FETTr2、Tr4及Tr6中被向图7所 示的箭头A’方向引出并被接合。另外，第二源电极用铜连接器36a2在图4的FETTr1中被向图7所示的箭头B方向引出并接合，在图4的FETTr3及Tr5中被向图7所示的箭头B’方向引出并接合。
这样，在一个FET裸芯片35中，一种的栅电极用铜连接器36b与从两种连接器即第一源电极用铜连接器36a1及第二源电极用铜连接器36a2中选择的任意一方的源电极用铜连接器组合使用。
由此，封装于基板31上的FET裸芯片35的配置上产生自由度，基板31上的布线的设计自由度增大，可以使基板31上的半导体模块30的布局紧凑。另外，可以容易地使基板31上的三相马达的各相的路径的长度(a相输出线91a的长度、b相输出线91b的长度、及c相输出线91c的长度)相同。由此，可以容易地使三相马达的各相特性、特别是阻抗特性一致，能够提高转矩和速度等脉动精度。
在此，参照图5、图8(A)、(B)及图9(A)、(B)、(C)、(D)具体地对栅电极用铜连接器36b的形状进行说明。
栅电极用铜连接器36b是通过对铜板进行冲压及弯曲加工而形成的，包括平板部36ba、从平板部36ba的一端延伸并通过焊锡34f与FET裸芯片35的栅电极G接合的接合部36bb、和从平板部36ba的另一端延伸并通过焊锡34c与布线图案33c接合的接合部36bc。
栅电极用铜连接器36b的平板部ba构成基于空气的吸附装置的吸附面。因此，可以利用平板部ba进行基于空气的吸附。
另外，栅电极用铜连接器36b的接合部36bb形成为，在从平板部36ba的一端向斜下方延伸的连结片36bd的下端向外侧延伸。该接合部36bb具有沿着栅电极G的短边及长边的短边及长边，与栅电极G接合的接合面的面积具有与栅电极G的面积大致相同的面积。通过将接合部36bb的与栅电极G接合的接合面的面积设为与栅电极G大致相同，可以确保栅电极用铜连接器36b和栅电极G之间的接合可靠性。
进而，栅电极用铜连接器36b的接合部36bc形成为，在从平板部36ba的另一端向斜下方延伸的连结片36be的下端向外侧延伸。接合部36bc位于比接合部36bb靠下方的位置。接合部36bc相对于布线图案33c的接合面的面积比接合部36bb相对于栅电极G的接合面的面积大。
这样，如图9(B)所示，栅电极用铜连接器36b具有平板部36ba、连结片36bd、 接合部36bb、连结片36be及接合部36bc,从正面观看形成为大致左侧U字型，所以在进行软钎焊接时进行后述的回流接合，另外，当由于半导体模块30工作时发热而变成高温时，可以有效地缓和热应力。
另外，参照图5、图10及图11(A)、(B)、(C)、(D)对源电极用铜连接器36a中的相对于栅电极用铜连接器36b进行180°直线配置的第一源电极用铜连接器36a1的形状具体地进行说明。
第一源电极用铜连接器36a1是通过对铜板进行冲压及弯曲加工而形成的，包括平板部36aa、从平板部36aa的一端延伸并通过焊锡34e与FET裸芯片35的源电极S接合的接合部36ab、以及从平板部36aa的另一端延伸并通过焊锡34b与布线图案33b接合的接合部36ac。
第一源电极用铜连接器36a1的平板部36aa构成基于空气的吸附装置的吸附面。因此，可以利用平板部aa进行基于空气的吸附。在该平板部36aa形成有用于对第二源电极用铜连接器36a2进行识别的识别用孔36af。
另外，第一源电极用铜连接器36a1沿着形成为长方形状的源电极S的短边所延伸的方向(图7中的箭头A’方向)引出。而且，第一源电极用铜连接器36a1的触点部36ab形成为，在从平板部36aa的一端向斜下方延伸的连结片36ad的下端向外侧延伸。该触点部36ab具有沿着该源电极S的短边及长边的短边及长边，与源电极S接合的接合面的面积具有与源电极S大致相同的面积。通过将接合部36ab的与源电极S接合的接合面的面积设为与长方形状的源电极S大致相同的面积，可以确保相对于栅电极用铜连接器36b进行180°直线配置的第一源电极用铜连接器36a1和形成于FET裸芯片35的上表面的源电极S之间的接合可靠性。
并且，第一源电极用铜连接器36a1的接合部36ac形成为，在从平板部36aa的另一端向斜下方延伸的连结片36ae的下端向外侧延伸。接合部36ac位于比接合部36ab靠下方的位置。接合部36ac相对于布线图案33b的接合面的面积，与接合部36ab相对于源电极S的接合面的面积大致相同。
这样，第一源电极用铜连接器36a1如图11(B)所示那样，具有平板部36aa、连结片36ad、接合部36ab、连结片36ae、以及接合部36ac，从正面观看形成为大致左侧U字型，所以在进行软钎焊接时进行后述的回流接合，另外，当由于在半导体模块30工作时发热而变成高温时，可以有效地缓和热应力。
另外，参照图5、图12、及图13(A)、(B)、(C)、(D)对源电极用铜连接器36a中的相对于栅电极用铜连接器36b进行90°直角配置的第二源电极用铜连接器36a2的形状具体地进行说明。
第二源电极用铜连接器36a2是通过对铜板进行冲压及弯曲加工而形成的，包括平板部36aa、从平板部36aa的一端延伸并通过焊锡34e与FET裸芯片35的源电极S接合的接合部36ab、以及从平板部36aa的另一端延伸并通过焊锡34b与布线图案33b接合的接合部36ac。
第二源电极用铜连接器36a2的平板部36aa构成基于空气的吸附装置的吸附面。因此，可以利用平板部aa进行基于空气的吸附。
另外，第二源电极用铜连接器36a2被沿着形成为长方形状的源电极S的长边所延伸的方向(图7中的箭头B或者B‘方向)引出。而且，第二源电极用铜连接器36a2的接合部36ab形成为，在从平板部36aa的一端向斜下方延伸的连结片36ad的下端向外侧延伸。该接合部36ab具有沿着该源电极S的长边及短边的短边及长边，与源电极S接合的接合面的面积具有与源电极S大致相同的面积。通过将接合部36ab的与源电极S接合的接合面的面积设为与长方形状的源电极S大致相同的面积，可以确保相对于栅电极用铜连接器36b进行90°直角配置的第二源电极用铜连接器36a2和形成于FET裸芯片35的上表面的源电极S之间的接合可靠性。
并且，第二源电极用铜连接器36a2的接合部36ac形成为，在从平板部36aa的另一端向斜下方延伸的连结片36ae的下端向外侧延伸。接合部36ac位于比接合部36ab靠下方的位置。接合部36ac相对于布线图案33b的接合面的面积与接合部36ab相对于源电极S的接合面的面积大致相同。
这样，第二源电极用铜连接器36a2如图13(B)所示，具有平板部36aa、连结片36ad、接合部36ab、连结片36ae及接合部36ac，从正面观看形成为大致左侧U字型，所以在进行软钎焊接时进行后述的回流接合，另外，当由于半导体模块30工作时发热而变成高温时，可以有效地缓和热应力。
此外，在图5所示的半导体模块30中，通过焊锡34d在形成于绝缘层32上的多个布线图案33a～33d中的另外一个其他布线图案33d上封装有电容等其他表面封装器件37。
如图3所示，这样构成的半导体模块30通过多个安装螺钉38被安装于外壳20 的半导体模块载置部21上。在半导体模块30的基板31形成有安装螺钉38进行插通的多个贯通孔31a。
此外，在将半导体模块30安装于半导体模块载置部21上时，将散热用薄板39安装于半导体模块载置部21上，从该散热用薄板39之上安装半导体模块30。利用该散热用薄板39，将半导体模块30产生的热量通过散热用薄板39向外壳20散热。
另外，控制电路基板40用于将多个电子器件封装于基板上而构成包含控制运算装置11及栅极驱动电路12的控制电路。在将半导体模块30安装于半导体模块载置部21上后，利用多个安装螺钉41在从半导体模块30的上方立设于半导体模块载置部21以及电力及信号用连接器封装部22的多个安装柱子24上安装控制电路基板40。在控制电路基板40上形成有安装螺钉41进行插通的多个贯通孔40a。
另外，电力及信号用连接器50用于将来自蓄电池(未图示)的直流电源输入到半导体模块30，将包含来自转矩传感器12和车速传感器9的信号的各种信号输入到控制电路基板40。利用多个安装螺钉51在设置于半导体模块载置部21的电力及信号用连接器封装部22上安装电力及信号用连接器50。
而且，三相输出用连接器60用于输出来自a相输出端子92a、b相输出端子92b及c相输出端子92c的电流。利用多个安装螺钉61在设置于半导体模块载置部21的宽度方向端部的三相输出用连接器封装部23安装三相输出用连接器60。在三相输出连接器60形成有安装螺钉61进行插通的多个贯通孔60a。
并且，相对于安装有半导体模块30、控制电路基板40、电力及信号用连接器50及三相输出用连接器60的外壳20，以从控制电路基板40的上方覆盖该控制电路基板40的方式安装盖70。
接着，参照图5对半导体模块30的制造方法进行说明。
在制造半导体模块30时，首先，在金属制的基板31的一方的主面上形成绝缘层32(绝缘层形成工序)。
接着，在绝缘层32上形成多个布线图案33a～33d(布线图案形成工序)。
之后，在多个布线图案33a～33d上分别涂敷焊锡膏(焊锡34a～34d)(焊锡膏涂敷工序)。
而且，在多个布线图案33a～33d中的一个布线图案33a上所涂敷的焊锡膏(焊锡33a)上搭载一个FET裸芯片35(FET裸芯片搭载工序)，在其他布线图案33d上 所涂敷的焊锡膏(焊锡34d)上搭载其他表面封装部件37。即使对于其他FET裸芯片35，也将其搭载于与布线图案33a相同的或者另外的布线图案上。
接着，在形成于FET裸芯片35的上表面的源电极S及栅电极G上涂敷焊锡膏(焊锡34e，34f)(焊锡膏涂敷工序)。
之后，在涂敷于FET裸芯片35的源电极S上的焊锡膏(焊锡34e)上以及涂敷于多个布线图案33a～33d中的搭载了FET裸芯片35的布线图案33a以外的其他布线图案33b上的焊锡膏(焊锡34b)上，搭载源电极用铜连接器36a(从第一源电极用铜连接器36a1及第二源电极用铜连接器36a2中选择的源电极用铜连接器)(源电极用铜连接器搭载工序)。
另外，在涂敷于FET裸芯片35的栅电极G上的焊锡膏(焊锡34f)上以及涂敷于多个布线图案33a～33d中的搭载了FET裸芯片35的布线图案33a及搭载了源电极用铜连接器36a的布线图案33b以外的另外其他布线图案33c上的焊锡膏(焊锡34c)上，搭载栅电极用铜连接器36b(栅电极用铜连接器搭载工序)。由此，构成半导体模块中间组装体。
而且，将通过以上的工序构成的半导体模块中间组装体放入回流炉(未图示)，集中进行如下的接合(接合工序)，即，通过焊锡34a将多个布线图案33a～33d中的一个布线图案33a和FET裸芯片35接合、通过焊锡34d将布线图案33d和其他表面封装部件37接合、通过焊锡34e将形成在FET裸芯片35上表面的源电极S和源电极用铜连接器36a接合、将多个布线图案33a～33d中的其他布线图案33b和源电极用铜连接器36a接合、通过焊锡34f将形成在FET裸芯片35上表面的栅电极G和栅电极用铜连接器36b接合、以及通过焊锡34c将多个布线图案33a～33d中的另外其他布线图案33c和栅电极用铜连接器26b接合。
由此，完成半导体模块30。
在此，通过对FET裸芯片35的源电极S和基板31上的布线图案33b之间的接合使用源电极用铜连接器36a，对FET裸芯片35的栅电极G和基板31上的另外的布线图案33c之间的接合使用栅电极用铜连接器36b，从而可以通过焊锡封装作业进行，所以可以通过与在将FET裸芯片35或其他表面封装部件37封装于基板31上的布线图案33a、33d上时进行的焊锡封装作业相同的工序，进行FET裸芯片35的源电极S和基板31上的布线图案33b之间的接合以及FET裸芯片35的栅电极G和基 板31上的另外的布线图案33c之间的接合。因此，可以缩短半导体模块30的制造节拍，并且不需要线接合的专用设备，可以降低半导体模块30的制造成本。
以上，对本发明的实施方式逐步进行了说明，但本发明不限定于此，可以进行各种变更、改进。
例如，在半导体模块30中使用了FET裸芯片35，但不限于FET裸芯片35，也可以使用IGBT裸芯片等其他的晶体管裸芯片。而且，在使用其他晶体管裸芯片的情况下，只要利用铜连接器，通过焊锡使形成于晶体管裸芯片的上表面的电极上和多个布线图案中的接合了晶体管裸芯片的布线图案以外的其他布线图案上接合即可。由此，可以通过与在将晶体管裸芯片或其他表面封装部件封装于基板上的布线图案上时进行的焊锡封装作业相同的工序进行晶体管裸芯片的电极和基板上的布线图案之间的接合。
而且，在作为晶体管裸芯片使用IGBT裸芯片的情况下，优选，使用铜连接器通过焊锡分别将形成于IGBT裸芯片上的发射极电极及栅电极接合于基板上的布线图案。
这样，当使用IGBT裸芯片并分别使用铜连接器将在IGBT裸芯片上形成的发射极电极及栅电极通过焊锡与基板上的布线图案接合的情况下，可以通过与在将IGBT裸芯片或其他表面封装部件封装于基板上的布线图案上时进行的焊锡封装作业相同的工序进行IGBT裸芯片的发射极电极和基板上的布线图案之间的接合及IGBT裸芯片的栅电极和基板上的另外的布线图案之间的接合。
另外，形成在FET裸芯片35上表面的源电极S形成为长方形状，但也可以以正方形状形成。在这种情况下，可以使与源电极S接合的第一源电极用连接器36a1及第二源电极用铜连接器36a2的形状相同而共同化。
此外，在图4所示的半导体模块30中，对a相输出线91a、b相输出线91b及c相输出线91c，使用了共同的铜连接器36c作为跨接线。由此，可以使a相输出线91a、b相输出线91b及c相输出线91c的路径的长度相同。
符号说明
1 转向盘
2 柱轴
3 减速齿轮3
4A、4B 万向接头
5 齿轮齿条机构
6 拉紧杆
7 转矩传感器
8 电动马达
9 车速传感器
10 控制器
11 控制运算装置
12 栅极驱动电路
13 马达驱动部
14 非常停止用的切断装置
15 电流检测电路
16 旋转传感器
17 转子位置检测电路
18 IGN电压监控部
19 电源电路部
20 外壳
21 半导体模块载置部
21a 螺钉孔
22 电力及信号用连接器封装部
23 三相输出用连接器封装部
23a 螺钉孔
24 安装柱子
24a 螺钉孔
30 半导体模块
31 基板
31a 贯通孔
32 绝缘层
33a～33d 布线图案
34a～34d 焊锡
35 FET裸芯片(晶体管裸芯片)
36a 源电极用铜连接器
36a1 第一源电极用铜连接器
36a2 第二源电极用连接器
36c 铜连接器
36aa 平板部
36ab 接合部
36ac 接合部
36ad 连结部
36ae 连结部
36af 识别用孔
36b 栅电极用铜连接器
36ba 平板部
36bb 接合部
36bc 接合部
36bd 连结部
36be 连结部
37 表面封装部件
38 安装螺钉
39 散热用薄板
40 控制电路基板
40a 贯通孔
41 安装螺钉
50 电力及信号用连接器
51 安装螺钉
60 三相输出用连接器
60a 贯通孔
61 安装螺钉
70 盖
81 电源线
81a 正极端子
82 接地线
82a 负极端子
90 三相输出部
91a a相输出线
91b b相输出线
91c c相输出线
G 栅电极(电极)
S 源电极(电极)

Claims (2)

1.一种半导体模块，其特征在于，
包括：金属制的基板；形成于该基板之上的绝缘层；形成于该绝缘层上的多个布线图案；通过焊锡封装于该多个布线图案中的一个布线图案上的晶体管裸芯片；以及用于通过焊锡将形成于该晶体管裸芯片的上表面的电极和上述多个布线图案中的其他布线图案进行接合的、由铜板构成的铜连接器，
上述晶体管裸芯片是在上表面形成有源电极及栅电极的FET裸芯片，上述铜连接器包括源电极用铜连接器和栅电极用铜连接器，利用上述源电极用铜连接器通过焊锡使上述FET裸芯片的源电极上和上述多个布线图案中的其他布线图案上接合，利用上述栅电极用铜连接器通过焊锡使上述FET裸芯片的栅电极上和上述多个布线图案中的另外其他布线图案上接合，
上述栅电极用铜连接器为一种，上述源电极用铜连接器是相对于上述栅电极用铜连接器进行180°直线配置的第一源电极用铜连接器和相对于上述栅电极用铜连接器进行90°直角配置的第二源电极用铜连接器的两种，在一个FET裸芯片中，将上述一种的栅电极用铜连接器和从上述两种的第一源电极用铜连接器及第二源电极用铜连接器中选择的任意一方的源电极用铜连接器组合进行使用，
形成于上述FET裸芯片的上表面的上述栅电极和上述源电极被串联直线配置，上述源电极形成为长方形状，
上述第一源电极用铜连接器沿着上述形成为长方形状的源电极的短边所延伸的方向引出，并且具备接合部，该接合部具有沿着该源电极的短边及长边的短边及长边且与上述源电极接合的接合面的面积是与上述源电极大致相同的面积。
2.一种半导体模块，其特征在于，
包括：金属制的基板；形成于该基板之上的绝缘层；形成于该绝缘层上的多个布线图案；通过焊锡封装于该多个布线图案中的一个布线图案上的晶体管裸芯片；以及用于通过焊锡将形成于该晶体管裸芯片的上表面的电极和上述多个布线图案中的其他布线图案进行接合的、由铜板构成的铜连接器，
上述晶体管裸芯片是在上表面形成有源电极及栅电极的FET裸芯片，上述铜连接器包括源电极用铜连接器和栅电极用铜连接器，利用上述源电极用铜连接器通过焊锡使上述FET裸芯片的源电极上和上述多个布线图案中的其他布线图案上接合，利用上述栅电极用铜连接器通过焊锡使上述FET裸芯片的栅电极上和上述多个布线图案中的另外其他布线图案上接合，
上述栅电极用铜连接器为一种，上述源电极用铜连接器是相对于上述栅电极用铜连接器进行180°直线配置的第一源电极用铜连接器和相对于上述栅电极用铜连接器进行90°直角配置的第二源电极用铜连接器的两种，在一个FET裸芯片中，将上述一种的栅电极用铜连接器和从上述两种的第一源电极用铜连接器及第二源电极用铜连接器中选择的任意一方的源电极用铜连接器组合进行使用，
形成于上述FET裸芯片的上表面的上述栅电极和上述源电极被串联直线配置，上述源电极形成为长方形状，
上述第二源电极用铜连接器沿着上述形成为长方形状的源电极的长边所延伸的方向引出，并且具备接合部，该接合部具有沿着该源电极的长边及短边的长边及短边且与上述源电极接合的接合面的面积是与上述源电极大致相同的面积。
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US5872403A (en) * 1997-01-02 1999-02-16 Lucent Technologies, Inc. Package for a power semiconductor die and power supply employing the same
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JP2002217416A (ja) * 2001-01-16 2002-08-02 Hitachi Ltd 半導体装置
JP2003023137A (ja) * 2001-07-09 2003-01-24 Sansha Electric Mfg Co Ltd 電力用半導体モジュール
JP4074991B2 (ja) * 2003-03-18 2008-04-16 富士電機ホールディングス株式会社 交流−交流電力変換装置
JP4075992B2 (ja) 2003-05-07 2008-04-16 トヨタ自動車株式会社 半導体モジュールの製造方法、半導体モジュール、それを用いた一体型モータおよび一体型モータを備える自動車
JP4764692B2 (ja) 2005-09-29 2011-09-07 日立オートモティブシステムズ株式会社 半導体モジュール
JP5152619B2 (ja) * 2006-02-09 2013-02-27 ダイヤモンド電機株式会社 半導体モジュール及びこれを備える半導体装置、並びに、半導体モジュールの製造方法
US8786072B2 (en) * 2007-02-27 2014-07-22 International Rectifier Corporation Semiconductor package
JP5098440B2 (ja) * 2007-05-25 2012-12-12 三菱電機株式会社 電力半導体装置の製造方法
JP2009021395A (ja) * 2007-07-12 2009-01-29 Panasonic Corp 半導体装置
JP5029900B2 (ja) * 2007-11-20 2012-09-19 アイシン・エィ・ダブリュ株式会社 モータの制御装置
JP2009231805A (ja) * 2008-02-29 2009-10-08 Renesas Technology Corp 半導体装置
JP2010034350A (ja) * 2008-07-30 2010-02-12 Sanyo Electric Co Ltd 半導体装置
JP5285348B2 (ja) * 2008-07-30 2013-09-11 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 回路装置
JP5384913B2 (ja) * 2008-11-18 2014-01-08 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
DE102008054735A1 (de) * 2008-12-16 2010-06-17 Robert Bosch Gmbh Leadless-Gehäusepackung
JP5625242B2 (ja) 2009-02-25 2014-11-19 日本精工株式会社 電動パワーステアリング装置、制御ユニットおよび車両
JP5388661B2 (ja) * 2009-04-03 2014-01-15 三菱電機株式会社 半導体装置およびその製造方法
JP2011014890A (ja) * 2009-06-02 2011-01-20 Mitsubishi Chemicals Corp 金属基板及び光源装置
JP2011204886A (ja) * 2010-03-25 2011-10-13 Panasonic Corp 半導体装置及びその製造方法
JP5383621B2 (ja) * 2010-10-20 2014-01-08 三菱電機株式会社 パワー半導体装置
KR101204187B1 (ko) * 2010-11-02 2012-11-23 삼성전기주식회사 소성 접합을 이용한 파워 모듈 및 그 제조 방법
JP2012212713A (ja) * 2011-03-30 2012-11-01 Toshiba Corp 半導体装置の実装構造
JP6043049B2 (ja) * 2011-03-30 2016-12-14 株式会社東芝 半導体装置の実装構造及び半導体装置の実装方法
JP5388235B2 (ja) * 2011-04-08 2014-01-15 ルネサスエレクトロニクス株式会社 半導体装置
US8399997B2 (en) * 2011-06-10 2013-03-19 Shanghai Kalhong Electronic Company Limited Power package including multiple semiconductor devices
EP2916348B1 (en) * 2012-11-05 2020-05-13 NSK Ltd. Semiconductor module

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101030570A (zh) * 2006-03-03 2007-09-05 三菱电机株式会社 半导体装置

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