JP5388235B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5388235B2 JP5388235B2 JP2011086201A JP2011086201A JP5388235B2 JP 5388235 B2 JP5388235 B2 JP 5388235B2 JP 2011086201 A JP2011086201 A JP 2011086201A JP 2011086201 A JP2011086201 A JP 2011086201A JP 5388235 B2 JP5388235 B2 JP 5388235B2
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- Prior art keywords
- lead
- electrode pad
- source
- semiconductor chip
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
本発明の一つの目的は、支持基板上により大きいサイズの半導体チップを固定できる半導体装置を提供することにある。
本発明の一つの目的は、電気的信頼性の高い半導体装置の製造方法を提供することにある。
(1)低オン抵抗の半導体装置を提供することができる。
(2)支持基板上により大きいサイズの半導体チップを固定できる半導体装置を提供することができ、高出力の半導体装置を提供することができる。
(実施形態1)
図1乃至図8は本発明の一実施形態(実施形態1)である半導体装置に係わる図である。図1は樹脂封止体を取り除いた半導体装置の模式的平面図、図2は半導体装置の断面図、図3は半導体装置に組み込まれる半導体チップの模式的平面図、図4は図3のA−A線に沿う断面図、図5はゲート電極パッドをチップのコーナに配置した状態を示すチップの一部を示す平面図、図6はゲート電極パッドをチップの辺の途中に配置した状態を示すチップの一部を示す平面図である。
本実施形態1では、本発明を縦型パワートランジスタ(半導体装置)1に適用した例について説明する。即ち、第1電極としてドレイン(D)電極、第2電極としてソース(S)電極、制御電極としてゲート(G)電極となる電界効果トランジスタを組み込んだ半導体チップが、半導体装置1に組み込まれている。
本実施形態1によれば、以下の効果を奏する。
図9は本発明の他の実施形態(実施形態2)である半導体装置の樹脂封止体を取り除いた模式的平面図、図10は半導体装置の断面図である。
図11は本発明の他の実施形態(実施形態3)である半導体装置の樹脂封止体を取り除いた模式的平面図、図12は半導体装置の断面図である。
図13は本発明の他の実施形態(実施形態4)である半導体装置の樹脂封止体を取り除いた模式的平面図である。
図14は本発明の他の実施形態(実施形態5)である半導体装置の樹脂封止体を取り除いた模式的平面図、図15は半導体装置の断面図、図16は半導体装置の製造で使用するリードフレームの平面図である。
図17は本発明の他の実施形態(実施形態6)である半導体装置の樹脂封止体を取り除いた模式的平面図、図18は半導体装置の断面図である。
図19は本発明の他の実施形態(実施形態7)である半導体装置の樹脂封止体を取り除いた模式的平面図、図20は半導体装置の断面図である。
図21は本発明の他の実施形態(実施形態8)である半導体装置の樹脂封止体を取り除いた模式的平面図である。
図22は本発明の他の実施形態(実施形態9)である半導体装置の模式的断面図である。本実施形態9は、実施形態1のパワートランジスタ1において、封止体2の端面から突出するドレインリード4,ソースリード5,ゲートリード6の3本のリードを、途中で折れ曲がるように成形し、先端は支持基板3の下面と略同じ高さに位置させて延在させた構造になっている。この先端の延在部分60は、パワートランジスタ1を実装基板等に支持基板3を固定する際、3本のリードの先端の延在部分60は実装基板に設けた配線との接続部分になる。実施形態9のパワートランジスタ1は面実装構造になっている。なお、ドレインリード4は支持基板3と同じ電位になることから、封止体2から突出する付け根部分で切断して実装基板には接続しない構造としてもよい。本実施形態8のパワートランジスタ1も実施形態1のパワートランジスタ1と同様の効果を有する。
Claims (9)
- MOSFETを含み、前記MOSFETのゲート電極パッドおよびソース電極パッドが形成された表面と、前記表面とは反対側に位置し、前記MOSFETのドレイン電極が形成された裏面と、を有する半導体チップと、
前記半導体チップが搭載された上面と、前記上面とは反対側に位置する下面と、を有するヘッダと、
前記ヘッダと電気的に接続されたドレインリードと、
前記半導体チップの前記ゲート電極パッドと電気的に接続されたゲートリードと、
前記半導体チップの前記ソース電極パッドと電気的に接続されたソースリードと、
前記半導体チップの前記ゲート電極パッドと前記ゲートリードとを電気的に接続する第1導電性ワイヤと、
前記半導体チップの前記ソース電極パッドと前記ソースリードとを電気的に接続する複数の第2導電性ワイヤと、
前記半導体チップ、前記ヘッダの一部、前記ドレインリードの一部、前記ゲートリードの一部、前記ソースリードの一部、前記第1導電性ワイヤ、および前記複数の第2導電性ワイヤを封止する封止体と、を有し、
前記半導体チップの裏面と前記ヘッダの上面とが対向するように前記半導体チップが前記ヘッダの上面に搭載されていることにより、前記半導体チップの前記ドレイン電極と前記ヘッダとは電気的に接続されており、
平面視において、前記ソース電極パッドの一部が前記ゲート電極パッドと前記ソースリードとの間に位置するように前記ソース電極パッドは前記半導体チップの前記表面に配置されており、
前記ゲート電極パッドと前記第1導電性ワイヤとが接続している部分は、前記ソース電極パッドと前記複数の第2導電性ワイヤとが接続しているそれぞれの部分よりも前記ソースリードから遠い位置にあることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記複数の第2導電性ワイヤは、第1ワイヤと第2ワイヤとを含み、
平面視において、前記ソース電極パッドと前記第1ワイヤとが接続している部分は、前記ソース電極パッドと前記第2ワイヤとが接続している部分よりも前記ゲート電極パッドと前記第1導電ワイヤとが接続している部分に近い位置にあることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記ソースリードは、前記ゲートリードと前記ドレインリードとの間に配置されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記ドレインリードは、前記ゲートリードと前記ソースリードとの間に配置されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記半導体チップの表面の一部には絶縁膜が形成され、平面視において前記ゲートおよびソース電極パッド上に位置する部分がそれぞれ開口されており、前記第1導電性ワイヤおよび前記複数の第2導電性ワイヤのそれぞれは、前記絶縁膜の前記開口している部分を介して前記ゲートおよびソース電極パッドのそれぞれに電気的に接続されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記半導体チップは矩形状であって、
前記ゲート電極パッドは、前記半導体チップの中心よりも角部に近くなるように配置されていることを特徴とする半導体装置。 - 請求項6に記載の半導体装置において、
前記角部は、前記ソースリードから最も遠い位置にある角部であることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記ゲートリードは、前記第1導電性ワイヤが接続されるゲートリードポスト部を有し、
前記ソースリードは、前記複数の第2導電性ワイヤがそれぞれ接続されるソースリードポスト部を有し、
前記ソースリードポスト部の前記ソースリードが延びる方向と直交する方向の幅は、前記ゲートリードポスト部の前記ゲートリードが延びる方向と直交する方向の幅よりも広いことを特徴とする半導体装置。 - MOSFETを含み、前記MOSFETのゲート電極パッドおよびソース電極パッドが形成された表面と、前記表面とは反対側に位置し、前記MOSFETのドレイン電極が形成された裏面と、を有する半導体チップと、
前記半導体チップが搭載された上面と、前記上面とは反対側に位置する下面と、を有するヘッダと、
前記ヘッダと電気的に接続されたドレインリードと、
前記半導体チップの前記ゲート電極パッドと電気的に接続されたゲートリードと、
前記半導体チップの前記ソース電極パッドと電気的に接続されたソースリードと、
前記半導体チップの前記ゲート電極パッドと前記ゲートリードとを電気的に接続する導電性ワイヤと、
前記半導体チップの前記ソース電極パッドと前記ソースリードとを電気的に接続する金属板と、
前記半導体チップ、前記ヘッダの一部、前記ドレインリードの一部、前記ゲートリードの一部、前記ソースリードの一部、前記導電性ワイヤ、および前記金属板を封止する封止体と、を有し、
前記半導体チップの裏面と前記ヘッダの上面とが対向するように前記半導体チップが前記ヘッダの前記上面に搭載されていることにより、前記半導体チップの前記ドレイン電極と前記ヘッダとは電気的に接続されており、
平面視において、前記ソース電極パッドの一部が前記ゲート電極パッドと前記ソースリードとの間に位置するように前記ソース電極パッドは前記半導体チップの前記表面に配置されており、
前記ゲート電極パッドと前記導電性ワイヤとが接続している部分は、前記ソース電極パッドと前記金属板とが接続している部分よりも前記ソースリードから遠い位置にあることを特徴とする半導体装置。
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