CN103915379A - 一种氧化物薄膜晶体管阵列基板的制造方法 - Google Patents
一种氧化物薄膜晶体管阵列基板的制造方法 Download PDFInfo
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Abstract
本发明涉及液晶显示技术领域,公开了一种氧化物薄膜晶体管阵列基板的制造方法。该方法通过形成沟道区域上保留有光刻胶的氧化物半导体层图案,从而在氧化物半导体层图案上形成源电极和漏电极的构图工艺中,沟道区域上保留的光刻胶能够保护该沟道区域不被源漏金属刻蚀液刻蚀,保证薄膜晶体管的半导体特性不受影响。
Description
技术领域
本发明涉及液晶显示技术领域,特别是涉及一种氧化物薄膜晶体管阵列基板的制造方法。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display,TFT-LCD)具有体积小、功耗低、无辐射等特点,在当前的平板显示器市场中占据了主导地位。TFT-LCD的主体结构是对盒设置的阵列基板和彩膜基板,以及填充在阵列基板和彩膜基板之间的液晶分子层。现有技术中,根据沟道材料的不同,TFT主要有氧化物半导体TFT(简称氧化物TFT)和非晶硅TFT两种。氧化物TFT因其具有更大的开关电流比,即打开时电流更大,充电时间更短;关断时,漏电流更小,不容易漏电,使其更适合制作高分辨率(高清晰度)、高刷新率(动态画面更流畅)的高端显示产品。
图1所示为现有技术中氧化物TFT阵列基板的另外一种结构示意图,其中,氧化物TFT为背沟道刻蚀结构(BCE,Back Channel Etch),其结构相对简单,从下至上分别为:栅电极2、栅绝缘层7、氧化物半导体层图案5、源电极3和漏电极4,然后上面覆盖上保护层8,源电极3和漏电极4直接与氧化物半导体层图案5搭接,氧化物半导体层图案5位于源电极3和漏电极4之间的部分为沟道区域,当TFT打开时,所述氧化物半导体层图案5的沟道区域形成TFT的导电沟道。这样的TFT结构,工艺更加简化,尺寸也更小,寄生电容也更小。但是在完成氧化物半导体层图案5的制作后,再接着进行源漏金属成膜,然后光刻胶涂覆、曝光、显影,当进行源漏金属刻蚀时,需要刻蚀掉源电极3和漏电极4之间的源漏金属,这时刻蚀液会对氧化物半导体层图案5的沟道区域有明显的腐蚀作用。针对于这一问题,有人提出了以下的改进方案:
图2所示为现有技术中氧化物TFT阵列基板的一种结构示意图,从下至上分别为:栅电极2、栅绝缘层7、氧化物半导体层图案5、刻蚀阻挡层9及刻蚀阻挡层过孔、源电极3和漏电极4,然后上面覆盖保护层8,源电极3和漏电极4通过刻蚀阻挡层过孔与氧化物半导体层图案5连接,氧化物半导体层图案5位于源电极3和漏电极4之间的部分为沟道区域,当TFT打开时,所述氧化物半导体层图案5的沟道区域形成TFT的导电沟道。其中,在形成源电极3和漏电极4的刻蚀工艺中,刻蚀阻挡层9可以保护氧化物半导体层图案5的沟道区域不被刻蚀。但是,这样的TFT结构,虽然能够保护在形成源电极3与漏电极4的时候保护氧化物半导体层图案5的沟道区域不被腐蚀,但是增加了刻蚀阻挡层9,却导致工艺复杂,尺寸增加,引入了源电极3、漏电极4与氧化物半导体层图案5之间的寄生电容。
发明内容
本发明提供一种氧化物薄膜晶体管阵列基板的制造方法,用以解决在形成BCE TFT的源电极和漏电极的刻蚀工艺中,既可以防止刻蚀液对氧化物半导体层图案的沟道区域造成腐蚀,同时又可以减少工艺步骤的问题。
为解决上述技术问题,本发明提供一种氧化物薄膜晶体管阵列基板的制造方法,包括在一基板上形成薄膜晶体管的步骤,其中,所述形成薄膜晶体管的步骤包括:
在所述基板上形成沟道区域上保留有光刻胶的氧化物半导体层图案;
在所述氧化物半导体层图案上形成源漏金属层,通过刻蚀工艺形成包括源电极、漏电极的图形,剥离氧化物半导体层图案的沟道区域上保留的光刻胶。
本发明的上述技术方案的有益效果如下:
上述技术方案中,通过形成沟道区域上保留有光刻胶的氧化物半导体层图案,从而在氧化物半导体层图案上形成源电极和漏电极的构图工艺中,沟道区域上保留的光刻胶能够保护该沟道区域不被源漏金属刻蚀液刻蚀,保证薄膜晶体管的半导体特性不受影响。同时在该构图工艺中,通过剥离沟道上的光刻胶形成薄膜晶体管的沟道。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。
图1表示现有技术中氧化物TFT阵列基板的结构示意图一;
图2表示现有技术中氧化物TFT阵列基板的结构示意图二;
图3表示本发明实施例中氧化物TFT阵列基板的制造方法流程图;
图4-图5表示本发明实施例中氧化物TFT阵列基板的氧化物半导体层图案的制备过程;
图6-图7表示本发明实施例中氧化物TFT阵列基板的源电极和漏电极的制备过程一;
图8-图11表示本发明实施例中氧化物TFT阵列基板的源电极和漏电极的制备过程二;
图12表示本发明实施例中氧化物TFT阵列基板的结构示意图。
具体实施方式
现有技术中氧化物TFT阵列基板的TFT为背沟道刻蚀结构时,在完成氧化物半导体层图案的制作后,再进行源电极和漏电极(由源漏金属形成)的制作,其中,氧化物半导体层图案位于源电极和漏电极之间的部分为沟道区域,当TFT打开时,所述氧化物半导体层图案的沟道区域形成薄膜晶体管的导电沟道。这种结构导致源电极和漏电极的制作工艺中,源漏金属刻蚀液会刻蚀氧化物半导体层图案的沟道区域,影响TFT的半导体特性。本发明针对上述技术问题,提供一种氧化物TFT阵列基板的制造方法,该方法通过形成沟道区域上保留有光刻胶的氧化物半导体层图案,从而在氧化物半导体层图案上形成源电极和漏电极的构图工艺中,沟道区域上保留的光刻胶能够保护该沟道区域不被源漏金属刻蚀液刻蚀,保证薄膜晶体管的半导体特性不受影响。
如图3所示,本发明实施例中,氧化物薄膜晶体管阵列基板的制造方法包括在一基板上形成薄膜晶体管的步骤,其中,所述形成薄膜晶体管的步骤包括:
步骤S1、在所述基板上形成沟道区域上保留有光刻胶的氧化物半导体层图案;
步骤S2、在所述氧化物半导体层图案上形成源漏金属层,通过刻蚀工艺形成包括源电极、漏电极的图形,剥离氧化物半导体层图案的沟道区域上保留的光刻胶。
上述技术方案,通过形成沟道区域上保留有光刻胶的氧化物半导体层图案,从而在氧化物半导体层图案上形成源电极和漏电极的构图工艺中,沟道区域上保留的光刻胶能够保护该沟道区域不被源漏金属刻蚀液刻蚀,保证薄膜晶体管的半导体特性不受影响。
下面将结合附图和实施例,对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明,但不用来限制本发明的范围。
结合图4和图5所示,其中,在基板1上形成沟道区域上保留有光刻胶的氧化物半导体层图案5的步骤具体包括:
步骤101、在一基板1(透明基板,如:玻璃基板、石英基板)上形成氧化物半导体层(图中未示出);
所述氧化物半导体层的材料可以选择非晶HIZO、ZnO、TiO2、CdSnO、MgZnO、IGO、IZO、ITO或IGZO中的一种或多种。
具体可以采用脉冲激光沉积、磁控溅射等成膜工艺在基板1上形成氧化物半导体层。
步骤102、在所述氧化物半导体层上涂覆光刻胶;
步骤103、结合图4所示,采用半色调或灰色调掩模板对所述光刻胶进行曝光,显影,形成光刻胶完全保留区域100、光刻胶半保留区域101和光刻胶不保留区域102,其中,光刻胶完全保留区域100至少对应氧化物半导体层图案5的沟道区域,光刻胶半保留区域101至少对应氧化物半导体层图案5的其他区域,光刻胶不保留区域102对应其他区域;
其中,光刻胶完全保留区域100的光刻胶厚度为1~4微米,光刻胶半保留区域101的光刻胶厚度为0.5~2微米。
步骤104、如图4所示,刻蚀光刻胶不保留区域102的氧化物半导体层,形成包括氧化物半导体层图案5的图形;
步骤105、通过灰化工艺去除光刻胶半保留区域101的光刻胶,保留光刻胶完全保留区域100的光刻胶,使得半导体层图案5的沟道区域上保留有光刻胶,如图5所示。
其中,灰化工艺的原理为:在密闭的氧气环境中,通过一定温度,让氧气与光刻胶反应,因为光刻胶是有机物很容易通过氧气发生化学反应,从而变成水与二氧化碳,通过精确控制时间、温度、氧气浓度来控制减薄光刻胶的厚度。
灰化工艺会对光刻胶完全保留区域100的光刻胶起到一个减薄作用,灰化工艺后光刻胶完全保留区域100的光刻胶厚度为0.5~2微米。
需要说明的是,形成沟道区域上保留有光刻胶的氧化物半导体层图案5的方式并不局限于上述步骤,还可以在形成氧化物半导体层图案5后,再在氧化物半导体层图案5上涂覆光刻胶,通过曝光和显影工艺,只保留氧化物半导体层图案5的沟道区域上的光刻胶。
在形成沟道区域上保留有光刻胶的氧化物半导体层图案5后,即可进行源电极和漏电极的制备,由于沟道区域上保留有光刻胶,则形成源电极和漏电极图形的刻蚀工艺中,源漏金属刻蚀液就不会再刻蚀氧化物半导体层图案5的沟道区域。
结合图6和图7所示,在一个具体的实施方式中,通过以下步骤形成TFT的源电极、漏电极和沟道,即步骤S2具体包括:
步骤201、在氧化物半导体层图案5上形成源漏金属层(图中未示出);
具体可以采用磁控溅射、热蒸发或其它成膜工艺形成源漏金属层,源漏金属层可以是Cu,Al,Ag,Mo,Cr,Nd,Ni,Mn,Ti,Ta,W等金属以及这些金属的合金。源漏金属层可以是单层结构或者多层结构,多层结构比如Cu\Mo,Ti\Cu\Ti,Mo\Al\Mo等。
步骤202、在所述源漏金属层上涂覆光刻胶;
步骤203、如图6所示,采用普通掩膜板对所述光刻胶进行曝光,显影,形成光刻胶保留区域200和光刻胶不保留区域201,其中,光刻胶保留区域200至少对应氧化物半导体层图案5的沟道区域,以及源电极3和漏电极4所在的区域,光刻胶不保留区域201对应其他区域;
步骤204、如图6所示,刻蚀掉光刻胶不保留区域201的源漏金属层;
步骤205、如图7所示,剥离光刻胶保留区域200的光刻胶,以及氧化物半导体层图案5的沟道区域上保留的光刻胶,形成源电极3和漏电极4,其中,源电极3和漏电极4搭接在氧化物半导体层图案5上,氧化物半导体层图案5位于源电极3和漏电极4之间的部分为沟道区域11,当TFT打开时,氧化物半导体层图案5的沟道区域11形成薄膜晶体管的导电沟道。
其中,剥离光刻胶工艺的原理是:通过碱性溶液将光刻胶完全溶化掉,然后清洗,从而对其他膜层的图案不会产生影响。
结合图8-图11所示,在另一个具体的实施方式中,通过以下步骤形成TFT的源电极、漏电极和沟道,即步骤S2具体包括:
步骤301、如图8所示,在氧化物半导体层图案5上形成源漏金属层10;
步骤302、如图9所示,剥离氧化物半导体层图案5的沟道区域上保留的光刻胶,形成氧化物半导体层图案5的沟道区域11;
步骤303、在源漏金属层10和沟道区域11上涂覆光刻胶;
步骤304、如图10所示,采用普通掩膜板对所述光刻胶进行曝光,显影,形成光刻胶保留区域300和光刻胶不保留区域301,其中,光刻胶保留区域300至少对应氧化物半导体层图案5的沟道区域11,以及源电极3和漏电极4所在的区域,光刻胶不保留区域301对应其他区域;
步骤305、结合图10和图11所示,刻蚀掉光刻胶不保留区域301的源漏金属层;
步骤306、结合图10和图11所示,剥离光刻胶保留区域300的光刻胶,形成源电极3和漏电极4,源电极3和漏电极4搭接在氧化物半导体层图案5上,沟道区域11位于源电极3和漏电极4之间。
步骤301-步骤306中,使用了两次剥离光刻胶工艺,这样可以有效的防止在步骤302中的第一次剥离工艺中,光刻胶剥离不完全的情况。
本发明实施例中,为了避免剥离光刻胶工艺中残留光刻胶,可以使用分子链较短的光刻胶,更加利于剥离工艺,防止光刻胶的残留。另外,也可以通过提高光刻胶厚度的方式,防止步骤302中源漏极金属层10上方不需要剥离光刻胶的位置与需要剥离光刻胶的位置粘连,并且侧面光刻胶与剥离液的接触面积更大,从而防止光刻胶剥离不干净,形成残留。
TFT除了源电极、漏电极,以及位于源电极和漏电极之间的沟道之外,还包括栅电极和像素电极。
结合图4所示,对于底栅型TFT阵列基板,本发明实施例中的制造方法,在基板1上形成氧化物半导体层图案5之前,还包括:
步骤401、在基板1上形成栅电极2;
具体地,可以采用溅射或热蒸发的方法在基板1上形成栅金属层(图中未示出),栅金属层可以是Cu,Al,Ag,Mo,Cr,Nd,Ni,Mn,Ti,Ta,W等金属以及这些金属的合金,栅金属层可以为单层结构或者多层结构,多层结构比如Cu\Mo,Ti\Cu\Ti,Mo\Al\Mo等。然后在栅金属层上涂覆一层光刻胶,采用掩膜板对光刻胶进行曝光,显影,使光刻胶形成光刻胶不保留区域和光刻胶保留区域,其中,光刻胶保留区域对应于栅电极2的所在区域,光刻胶不保留区域对应于其他区域;通过刻蚀工艺完全刻蚀掉光刻胶不保留区域的栅金属层,剥离剩余的光刻胶,形成栅电极2。
步骤402、在栅电极2上方形成栅绝缘层7。
具体地,可以采用等离子体增强化学气相沉积(PECVD)方法,在经过形成栅电极2的基板1上形成栅绝缘层7,其中,栅绝缘层7材料可以选用氧化物、氮化物或者氮氧化物,栅绝缘层20可以为单层、双层或多层结构。具体地,栅绝缘层20可以是SiNx,SiOx或Si(ON)x。
结合图12所示,对于底栅型TFT阵列基板,本发明实施例中的制造方法,在形成源电极3和漏电极4之后,还包括:
步骤501、在源电极3、漏电极4和氧化物半导体层图案5的沟道区域11的上方形成钝化层8;
具体地,可以采用磁控溅射、热蒸发、PECVD或其它成膜工艺在基板1上形成钝化层8,其中,钝化层8的材料可以选用氧化物、氮化物或氮氧化物,具体地,钝化层8可以是SiNx,SiOx或Si(ON)x。钝化层8可以是单层结构,也可以是采用氮化硅和氧化硅构成的两层结构。
步骤502、对钝化层8进行构图工艺,在漏电极4的上方形成钝化层过孔12的图案;
具体为,在钝化层8上涂敷一层光刻胶;采用掩膜板对光刻胶进行曝光,显影,使光刻胶形成光刻胶不保留区域和光刻胶保留区域,其中,光刻胶不保留区域对应于钝化层过孔12所在区域,光刻胶保留区域对应于其他区域;通过刻蚀工艺完全刻蚀掉光刻胶不保留区域的钝化层,形成钝化层过孔12,剥离剩余的光刻胶。
步骤503、在钝化层8上方形成像素电极9,像素电极9通过钝化层过孔12与漏电极4电性连接。
具体地,在形成钝化层8的基板1上采用磁控溅射、热蒸发或其它成膜工艺形成透明导电层,透明导电层可以是ITO或IZO。在透明导电层上涂敷一层光刻胶;采用掩膜板对光刻胶进行曝光,显影,使光刻胶形成光刻胶不保留区域和光刻胶保留区域,其中,光刻胶保留区域对应于像素电极9所在区域,光刻胶不保留区域对应于其他区域;通过刻蚀工艺完全刻蚀掉光刻胶不保留区域的透明导电层,剥离剩余的光刻胶,形成像素电极9,像素电极9通过钝化层过孔12与漏电极4电性连接。
本发明提供一种氧化物薄膜晶体管阵列基板的制造方法,在形成BCE TFT的源电极和漏电极的刻蚀工艺中,既可以防止刻蚀液对氧化物半导体层图案的沟道区域造成腐蚀,同时又可以减少工艺步骤。
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明技术原理的前提下,还可以做出若干改进和替换,这些改进和替换也应视为本发明的保护范围。
Claims (6)
1.一种氧化物薄膜晶体管阵列基板的制造方法,包括在一基板上形成薄膜晶体管的步骤,其特征在于,所述形成薄膜晶体管的步骤包括:
在所述基板上形成沟道区域上保留有光刻胶的氧化物半导体层图案;
在所述氧化物半导体层图案上形成源漏金属层,通过刻蚀工艺形成包括源电极、漏电极的图形,剥离氧化物半导体层图案的沟道区域上保留的光刻胶。
2.根据权利要求1所述的制造方法,其特征在于,所述在所述基板上形成沟道区域上保留有光刻胶的氧化物半导体层图案的步骤包括:
在所述基板上形成氧化物半导体层;
在所述氧化物半导体层上涂覆光刻胶;
采用半色调或灰色调掩模板对所述光刻胶进行曝光,显影,形成光刻胶完全保留区域、光刻胶半保留区域和光刻胶不保留区域,其中,所述光刻胶完全保留区域至少对应氧化物半导体层图案的沟道区域,所述光刻胶半保留区域至少对应氧化物半导体层图案的其他区域,所述光刻胶不保留区域对应其他区域;
刻蚀光刻胶不保留区域的氧化物半导体层,形成包括氧化物半导体层图案的图形;
通过灰化工艺去除光刻胶半保留区域的光刻胶,保留氧化物半导体层图案的沟道区域上的光刻胶。
3.根据权利要求1或2所述的制造方法,其特征在于,所述在所述氧化物半导体层图案上形成源漏金属层,通过刻蚀工艺形成包括源电极、漏电极的图形,剥离氧化物半导体层图案的沟道区域上保留的光刻胶的步骤包括:
在所述氧化物半导体层图案上形成源漏金属层;
在所述源漏金属层上涂覆光刻胶;
对所述光刻胶进行曝光,显影,形成光刻胶保留区域和光刻胶不保留区域,其中,所述光刻胶保留区域至少对应氧化物半导体层图案的沟道区域,以及源电极和漏电极所在的区域,所述光刻胶不保留区域对应其他区域;
刻蚀掉光刻胶不保留区域的源漏金属层;
剥离光刻胶保留区域的光刻胶,以及氧化物半导体层图案的沟道区域上保留的光刻胶,形成源电极和漏电极。
4.根据权利要求1或2所述的制造方法,其特征在于,所述在所述氧化物半导体层图案上形成源漏金属层,通过刻蚀工艺形成包括源电极、漏电极的图形,剥离氧化物半导体层图案的沟道区域上的光刻胶的步骤包括:
在所述氧化物半导体层图案上形成源漏金属层;
剥离氧化物半导体层图案的沟道区域上保留的光刻胶;
在所述源漏金属层和氧化物半导体层图案的沟道区域上涂覆光刻胶;
对所述光刻胶进行曝光,显影,形成光刻胶保留区域和光刻胶不保留区域,其中,所述光刻胶保留区域至少对应氧化物半导体层图案的沟道区域,以及源电极和漏电极所在的区域,所述光刻胶不保留区域对应其他区域;
刻蚀掉光刻胶不保留区域的源漏金属层;
剥离光刻胶保留区域的光刻胶,形成源电极和漏电极。
5.根据权利要求1或2所述的制造方法,其特征在于,所述在所述基板上形成沟道上保留有光刻胶的氧化物半导体层图案的步骤之前还包括:
在所述基板上形成栅电极;
在栅电极上方形成栅绝缘层。
6.根据权利要求1或2所述的制造方法,其特征在于,所述在所述氧化物半导体层图案上形成源漏金属层,通过刻蚀工艺形成包括源电极、漏电极的图形,剥离氧化物半导体层图案的沟道区域上的光刻胶的步骤之后还包括:
在源电极、漏电极和氧化物半导体层图案的沟道区域的上方形成钝化层;
对所述钝化层进行构图工艺,在漏电极的上方形成钝化层过孔的图案;
在所述钝化层上方形成像素电极,通过所述钝化层过孔与漏电极电性连接。
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