CN104409413A - 阵列基板制备方法 - Google Patents
阵列基板制备方法 Download PDFInfo
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- CN104409413A CN104409413A CN201410643661.6A CN201410643661A CN104409413A CN 104409413 A CN104409413 A CN 104409413A CN 201410643661 A CN201410643661 A CN 201410643661A CN 104409413 A CN104409413 A CN 104409413A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 51
- 239000000758 substrate Substances 0.000 title claims abstract description 47
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 119
- 238000000034 method Methods 0.000 claims abstract description 55
- 239000000463 material Substances 0.000 claims abstract description 48
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 239000010409 thin film Substances 0.000 claims abstract description 22
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 14
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 14
- 230000008569 process Effects 0.000 claims description 39
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 238000000059 patterning Methods 0.000 claims description 19
- 239000004020 conductor Substances 0.000 claims description 18
- 238000001259 photo etching Methods 0.000 claims description 17
- 238000009413 insulation Methods 0.000 claims description 11
- 230000005611 electricity Effects 0.000 claims description 9
- 238000007687 exposure technique Methods 0.000 claims description 4
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 7
- 238000000206 photolithography Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 194
- 238000002161 passivation Methods 0.000 description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 238000010586 diagram Methods 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 11
- 238000000137 annealing Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- 238000000576 coating method Methods 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 5
- 239000011733 molybdenum Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 229910052758 niobium Inorganic materials 0.000 description 4
- 239000010955 niobium Substances 0.000 description 4
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 229910003437 indium oxide Inorganic materials 0.000 description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 3
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910052725 zinc Inorganic materials 0.000 description 3
- 239000011701 zinc Substances 0.000 description 3
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- GRPQBOKWXNIQMF-UHFFFAOYSA-N indium(3+) oxygen(2-) tin(4+) Chemical class [Sn+4].[O-2].[In+3] GRPQBOKWXNIQMF-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910001182 Mo alloy Inorganic materials 0.000 description 1
- 229910001257 Nb alloy Inorganic materials 0.000 description 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000010009 beating Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- DTSBBUTWIOVIBV-UHFFFAOYSA-N molybdenum niobium Chemical compound [Nb].[Mo] DTSBBUTWIOVIBV-UHFFFAOYSA-N 0.000 description 1
- ZPZCREMGFMRIRR-UHFFFAOYSA-N molybdenum titanium Chemical compound [Ti].[Mo] ZPZCREMGFMRIRR-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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Abstract
本发明提供一种阵列基板制备方法,属于液晶显示技术领域,其可解决现有的液晶显示的阵列基板制备工艺复杂的问题。本发明的阵列基板制备方法包括:S1、在基底上依次形成半导体材料层和第一光刻胶层,通过光刻工艺形成包括有源区的图形,至少在有源区用于在薄膜晶体管导通时导电的区域上剩余有第一光刻胶层;S2、在完成前述步骤的基底上形成第一材料层,通过光刻工艺用第一材料层形成包括第一结构的图形。本发明特别适于制备使用金属氧化物薄膜晶体管的阵列基板。
Description
技术领域
本发明属于液晶显示技术领域,具体涉及一种阵列基板制备方法。
背景技术
阵列基板是液晶显示装置的重要组件,其中包括大量的薄膜晶体管(TFT)。传统薄膜晶体管的有源区由多晶硅、非晶硅等材料制成,而与硅材质有源区相比,金属氧化物半导体(如IGZO,氧化铟镓锌;或ITZO,氧化铟锡锌)具有迁移率高、均一性好、透明等诸多优点,因此使用金属氧化物半导体作为有源区的薄膜晶体管(金属氧化物薄膜晶体管)获得了越来越广泛的应用。
但由于金属氧化物的刻蚀特性与作为源漏极的金属、作为像素电极的氧化铟锡(ITO)等比较类似,故其在源漏极、像素电极等的制备过程中可能被损坏,为此,需要在有源层上(至少是有源层用于在薄膜晶体管导通时导电的区域上)形成由氮化硅、氧化硅等制成的刻蚀阻挡层(ESL,Etch Stop Layer),以防止有源层在后续工艺中被损坏。而为形成刻蚀阻挡层需要额外增加一次构图(mask)步骤,这导致使用金属氧化物薄膜晶体管的阵列基板制备步骤多、工艺复杂(通常需要6~7mask)。
发明内容
本发明所要解决的技术问题包括,针对现有的液晶显示的阵列基板制备工艺复杂的问题,提供一种制备工艺简单的阵列基板。
解决本发明技术问题所采用的技术方案是一种阵列基板制备方法,其包括:
S1、在基底上依次形成半导体材料层和第一光刻胶层,通过光刻工艺形成包括有源区的图形,至少在有源区用于在薄膜晶体管导通时导电的区域上剩余有第一光刻胶层;
S2、在完成前述步骤的基底上形成第一材料层,通过光刻工艺用第一材料层形成包括第一结构的图形。
在本发明中,“构图工艺”是指通过去除材料层的一部分使剩余材料层形成所需图形的步骤,其包括“形成材料层-涂布光刻胶-曝光-显影-刻蚀-光刻胶剥离”等步骤中的一步或多步。
在本发明中,“光刻工艺”是指在形成材料层和涂布光刻胶之后,通过“曝光-显影-刻蚀”的步骤使剩余材料层形成所需图形的步骤,但其并不包括涂布光刻胶和光刻胶剥离步骤。
在本发明的阵列基板制备方法中,在形成有源区的步骤中保留了部分第一光刻胶层,该剩余的第一光刻胶层可在后续步骤中起到保护有源区的作用,或者说起到类似刻蚀阻挡层的作用;同时,该剩余的第一光刻胶层是在常规构图工艺中也会形成的,本发明中只要暂不将其剥离即可;故本发明的制备方法不需要增加额外步骤(实际还少了一次光刻胶剥离步骤),而且减少了一次构图步骤(形成刻蚀阻挡层的步骤),可简化阵列基板的制备方法。
优选的是,所述半导体材料层为金属氧化物半导体材料层。
优选的是,所述第一材料层为透明导电材料层;所述第一结构为像素电极或公共电极。
进一步优选的是,在所述步骤S1之前,还包括:在基底上通过构图工艺形成包括源极、漏极的图形;所述步骤S1中剩余的第一光刻胶层与有源区重叠。
进一步优选的是,在所述通过构图工艺形成包括源极、漏极的图形步骤之前,还包括:在基底上通过构图工艺形成包括栅极、栅线的图形;在完成前述步骤的基底上形成栅绝缘层。
进一步优选的是,所述步骤S2包括:
S21、在完成前述步骤的基底上依次形成透明导电材料层和第二光刻胶层;
S22、通过光刻工艺用透明导电材料层形成包括像素电极或公共电极的图形;
S23、剥离剩余的第一光刻胶层和第二光刻胶层。
优选的是,所述第一材料层为金属层;所述第一结构为源极和漏极。
进一步优选的是,在所述步骤S1中剩余的第一光刻胶层位于有源区用于在薄膜晶体管导通时导电的区域上,有源区用于与源漏极接触的区域无第一光刻胶层剩余。
进一步优选的是,所述步骤S1包括:
S11、在基底上依次形成半导体材料层和第一光刻胶层;
S12、通过梯度曝光工艺对第一光刻胶层进行曝光、显影,使对应有源区与源漏极接触区域的位置保留第一厚度的第一光刻胶层,对应有源区用于在薄膜晶体管导通时导电区域的位置保留第二厚度的第一光刻胶层,其余位置不保留第一光刻胶层,所述第一厚度小于第二厚度;
S13、除去无第一光刻胶层覆盖的半导体材料层,形成包括有源区的图形,并减薄剩余的第一光刻胶层,使所述第一厚度的第一光刻胶层被除去,所述第二厚度的第一光刻胶层减薄,在有源区用于在薄膜晶体管导通时导电的区域上剩余第一光刻胶层。
进一步优选的是,所述步骤S2包括:
S21、在完成前述步骤的基底上依次形成金属层和第二光刻胶层;
S22、通过光刻工艺用金属层形成包括源极和漏极的图形;
S23、除去剩余的第二光刻胶层和第一光刻胶层。
进一步优选的是,所述步骤S1之前,还包括:在基底上通过构图工艺形成包括栅极、栅线的图形;在完成前述步骤的基底上形成栅绝缘层。
本发明特别适于制备使用金属氧化物薄膜晶体管的阵列基板。
附图说明
图1为本发明的实施例2的阵列基板制备方法在形成源极、漏极后的剖面结构示意框图;
图2为本发明的实施例2的阵列基板制备方法在形成有源区后的剖面结构示意框图;
图3为本发明的实施例2的阵列基板制备方法在形成透明导电材料层后的剖面结构示意框图;
图4为本发明的实施例2的阵列基板制备方法在形成像素电极后的剖面结构示意框图;
图5为本发明的实施例2的阵列基板制备方法在剥离第一光刻胶层和第二光刻胶层后的剖面结构示意框图;
图6为本发明的实施例2的阵列基板制备方法所制备的阵列基板的剖面结构示意框图;
图7为本发明的实施例3的阵列基板制备方法在形成半导体材料层后的剖面结构示意框图;
图8为本发明的实施例3的阵列基板制备方法在对第一光刻胶层进行显影后的剖面结构示意框图;
图9为本发明的实施例3的阵列基板制备方法在形成有源区后的剖面结构示意框图;
图10为本发明的实施例3的阵列基板制备方法在形成金属层后的剖面结构示意框图;
图11为本发明的实施例3的阵列基板制备方法在形成源极和漏极后的剖面结构示意框图;
图12为本发明的实施例3的阵列基板制备方法在剥离第一光刻胶层和第二光刻胶层后的剖面结构示意框图;
图13为本发明的实施例3的阵列基板制备方法所制备的阵列基板的剖面结构示意框图;
其中附图标记为:1、基底;2、栅极;3、有源区;31、半导体材料层;4、金属层;41、源极;42、漏极;5、像素电极;51、透明导电材料层;6、公共电极;81、栅绝缘层;82、钝化层;83、第一钝化层;84、第二钝化层;89、平坦化层;91、第一光刻胶层;92、第二光刻胶层。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案,下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1:
本实施例提供一种阵列基板制备方法,其包括:
S101、在基底上依次形成半导体材料层和第一光刻胶层,通过光刻工艺形成包括有源区的图形,至少在有源区用于在薄膜晶体管导通时导电的区域上剩余有第一光刻胶层;
S102、在完成前述步骤的基底上形成第一材料层,通过光刻工艺用第一材料层形成包括第一结构的图形。
在本实施例的阵列基板制备方法中,在形成有源区的步骤中保留了部分第一光刻胶层,该剩余的第一光刻胶层可在后续步骤中起到保护有源区的作用,或者说起到类似刻蚀阻挡层的作用;同时,该剩余的第一光刻胶层是在常规构图工艺中也会形成的,本实施例中只要暂不将其剥离即可;故本实施例的制备方法不需要增加额外步骤(实际还少了一次光刻胶剥离步骤),而且减少了一次构图步骤(形成刻蚀阻挡层的步骤),可简化阵列基板的制备方法。
实施例2:
如图1至图6所示,本实施例提供一种阵列基板(具体为液晶显示的阵列基板)制备方法,其与实施例1的方法类似,其中第一材料层为透明导电材料层51,而第一结构为像素电极5或公共电极6,本实施例中主要以第一结构为像素电极5为例进行描述。
具体的,本实施例的阵列基板制备方法包括以下步骤:
S201、优选的,在基底1上通过构图工艺形成包括栅极2、栅线的图形。
也就是说,本实施例制备的阵列基板为底栅型结构,从而需要先形成栅极2、栅线等;当然,在形成栅极2、栅线的同时,还可形成公共电极线(图中未示出)。
其中,栅极2、栅线可通过溅射工艺等形成,通常厚度在200~300nm,可由钼、铌、铝、钨等金属或它们的合金制造,或者也可主体由铜制造,且在铜层的一侧或两侧设有钼铌合金、钼钛合金、钼钨合金等缓冲层(厚度为20~30nm),从而形成双层或三层结构。
当然,在本步骤之前,还可包括形成缓冲层等其他常规步骤。同时,如果本实施例制备的阵列基板为顶栅型结构,则本步骤也可在之后进行。
S202、在完成前述步骤的基底1上形成栅绝缘层81(GI)。
其中,栅绝缘层81可通过等离子增强化学气相沉积(PECVD)等工艺形成,厚度通常在150~300nm,可由氧化硅、氮化硅、氮氧化硅等材质构成,可为单层结构,也可为多层结构;但优选的,其最上层(即与有源层接触的层)最好为二氧化硅,因为二氧化硅中氢含量比较小,可提高有源层性能。
S203、在完成前述步骤的基底1上通过构图工艺形成包括源极41、漏极42的图形,从而得到如图1所示的结构。
其中,源极41、漏极42可由金属形成,其厚度可在200~300nm,可为与上述栅极2类似的铜、钼、铌、铝、钨等金属或合金的单层或多层结构。
当然,在本步骤中,还可同时形成数据线等其他已知结构。
S204、在完成前述步骤的基底1上依次形成半导体材料层和第一光刻胶层91,通过光刻工艺形成包括有源区3(与源极41、漏极42接触)的图形,且保留光刻后剩余的第一光刻胶层91,该剩余的第一光刻胶层91与有源区3重叠,从而得到如图2所示的结构。
也就是说,按常规的光刻工艺形成有源区3,但在形成有源区3后,不将有源区3上剩余的第一光刻胶层91剥离,而是在保留该层的情况下进行后续步骤。
其中,半导体材料层可通过溅射工艺形成,厚度通常在40~50nm。
优选的,该半导体材料层可为金属氧化物半导体材料,例如氧化铟镓锌或者氧化铟锡锌等,即该阵列基板上的薄膜晶体管为金属氧化物薄膜晶体管。由于金属氧化物半导体容易在后续步骤中损伤,故本实施例的方法特别适用于金属氧化物半导体的有源层,当然,对于硅系有源层等,也可采取本实施例的方法。
S205、在完成前述步骤的基底1上依次形成透明导电材料层51和第二光刻胶层92。
也就是说,通过溅射工艺形成氧化铟锡等用作像素电极5的透明导电材料层51(厚度可在30~50nm),由于此时有源区3上剩余有第一光刻胶层91,故透明导电材料层51与有源区3间被第一光刻胶层91分开,并不接触,得到如图3所示的结构;之后继续涂布第二光刻胶层92。
S206、通过光刻工艺用透明导电材料层51形成包括像素电极5的图形,得到如图4所示的结构。
也就是说,按常规工艺对第二光刻胶层92进行曝光、显影,之后对暴露的透明导电材料层51进行湿法刻蚀,形成与漏极42接触的像素电极5,而此时剩余的第一光刻胶层91上的透明导电材料层51被除去,故第一光刻胶层91出来,得到如图4所示的结构。
可见,在S205和S206步骤中,剩余的第一光刻胶层91一直覆盖有源区3,起到了保护有源区3的作用;且该剩余的第一光刻胶层91是在有源区3形成过程中剩余下来的,只要减少一次光刻胶剥离即可得到,而不必新增构图步骤,从而简化了阵列基板的制备工艺。
显然,在本步骤中是以用透明导电材料层51形成像素电极5作为例子;但实际上,本步骤中形成的也可以是公共电极6,其与像素电极5的区别在于公共电极6不与漏极42接触,而是通过栅绝缘层81中的过孔与公共电极线(可与栅极2同步形成)接触。总之,不论此时形成的像素电极5还是公共电极6,其区别仅在于电极具体图形不同,而剩余的第一光刻胶层91的作用是相同的。
S207、剥离剩余的第一光刻胶层91和第二光刻胶层92,得到如图5所示的结构。
也就是说,将全部剩余的光刻胶层剥离,以便进行后续步骤。
S208、优选的,对完成前述步骤的基底1进行退火处理。
本步骤的退火可提高有源区3的稳定性,同时也可降低像素电极5的方块电阻,其具体可为在200~300℃的温度下加热0.5~1.5小时。
S209、在完成前述步骤的基底1上形成钝化层82(PVX),优选进行再次退火。
该钝化层82可为氧化硅、氮化硅、氮氧化硅等的单层或多层结构,可由化学气相沉积法形成,作用是保护有源区3、像素电极5等,并用于将素电极与公共电极6隔开;同时,钝化层82中还应形成有用于使公共电极6与公共电极线相连的过孔。
要注意的是,在本步骤中形成钝化层82的沉积温度优选控制在200℃以下,以免其对有源层、像素电极5等产生破坏。
为改善器件的稳定性,在形成钝化层82后还可进行再次退火,其退火温度可控制在250~350℃,时间0.5~1.5小时。
S210、通过构图工艺形成包括公共电极6的图形,得到如图6所示的结构。
也就是说,通过溅射工艺形成氧化铟锡层(厚度可在30~50nm),并对其进行光刻,从而形成狭缝电极形式的公共电极6(公共电极6通过钝化层82、栅绝缘层81中的过孔与公共电极线相连)。
显然,在本步骤中是以形成公共电极6作为例子(因步骤S206中形成的是像素电极5);但若在步骤S206中已经形成了公共电极6,则本步骤中也可形成像素电极5,此时该像素电极5可通过钝化层82中的过孔与漏极42相连。
S211、优选的,进行最终退火,得到高级超维场转换模式(ADvanced Super Dimension Switch,SADS,简称ADS)的阵列基板。
最终退火可提高器件的稳定性,并降低公共电极6的电阻,其退火温度可在250~300℃,时间0.5~1.5小时。
当然,应当理解,本实施例制备的阵列基板的形式还可进行许多变化,例如,也可不进行形成公共电极的步骤,即公共电极可形成在彩膜基板上,从而本实施例的方法制备的是扭曲向列模式模式(TN)的阵列基板。
实施例3:
如图7至图13所示,本实施例提供一种阵列基板(具体为液晶显示的阵列基板)制备方法,其与实施例1的方法类似,其中第一材料层为金属层4,而第一结构为源极41和漏极42。
具体的,本实施例的阵列基板制备方法包括以下步骤:
S301、优选的,在基底1上通过构图工艺形成包括栅极2、栅线的图形。
也就是说,本实施例制备的阵列基板为底栅型结构,从而需要先形成栅极2、栅线等;当然,在形成栅极2、栅线的同时,还可形成公共电极线(图中未示出)的图形。
其中,栅极2、栅线可通过溅射工艺等形成,通常厚度在200~300nm,可由钼、铌、铝、钨等金属或它们的合金制造,可为双层或三层结构。
当然,在本步骤之前,还可包括形成缓冲层等其他常规步骤。同时,如果本实施例制备的阵列基板为顶栅型结构,则本步骤也可在之后进行。
S302、在完成前述步骤的基底1上形成栅绝缘层81。
其中,栅绝缘层81可通过等离子增强化学气相沉积形成,厚度通常在150~300nm,可由氧化硅、氮化硅、氮氧化硅等构成,可为单层或多层结构。
S303、在完成前述步骤的基底1上依次形成半导体材料层31和第一光刻胶层91。
其中,先通过溅射工艺形成半导体材料层31,半导体材料层31厚度通常在40~50nm;之后在半导体材料层31上涂布第一光刻胶层91,得到如图7所示的结构。
优选的,该半导体材料层31可为金属氧化物半导体材料,例如氧化铟镓锌或者氧化铟锡锌等。
S304、通过梯度曝光工艺对第一光刻胶层91进行曝光、显影,使对应有源区3与源漏极接触区域的位置处保留第一厚度的第一光刻胶层91,对应有源区3用于在薄膜晶体管导通时导电区域的位置处保留第二厚度的第一光刻胶层91,其余位置不保留第一光刻胶层91,第一厚度小于第二厚度。
其中,所述“梯度曝光工艺”是指通过灰阶掩膜版、半色调掩膜版等对第一光刻胶层91进行阶梯曝光,使第一光刻胶层91不同位置的曝光程度不同;这样,在显影后,大部分位置的第一光刻胶层91被除去,而在有源区3用于与源漏极接触的区域保留较薄的第一光刻胶层91,在有源区3用于在薄膜晶体管导通时导电的区域(即“沟道”区域)则保留较厚的第一光刻胶层91,即得到如图8所示的结构。
S305、除去无第一光刻胶层91覆盖的半导体材料层31,形成包括有源区3的图形,并减薄剩余的第一光刻胶层91,使第一厚度的第一光刻胶层91被除去,第二厚度的第一光刻胶层91减薄,得到如图9所示的结构。
也就是说,通过湿法刻蚀除去暴露的半导体材料层31,从而形成有源区3,之后对剩余的第一光刻胶层91进行灰化(Ashing)减薄,使有源区3用于与源漏极接触的区域的第一光刻胶层91被彻底除去,而“沟道”区域的第一光刻胶层91厚度减薄,但仍保留一定厚度(如第二厚度减去第一厚度)的第一光刻胶层91。
S306、优选的,进行等离子处理。
也就是说,用含氟气体(如四氟化碳)对基底1进行等离子处理,从而改善有源区3暴露部分(即用于与源漏极接触的部分)的性能,降低其与源漏极接触后的欧姆电阻。
S307、在完成前述步骤的基底1上依次形成金属层4和第二光刻胶层92。
也就是说,通过溅射等方法沉积用于形成源漏极的金属层4,得到如图10所示的图形,其中,该金属层4厚度在200~300nm,可为与上述栅极2类似的铜、钼、铌、铝、钨等金属或合金的单层或多层结构;之后继续在在金属层4上涂布第二光刻胶层92。
由于此时有源区3的“沟道”区域上具有第一光刻胶层91,故金属层4只与有源区3用于与连接源漏极的区域接触,而与“沟道”区域间则隔有第一光刻胶层91。
S308、通过光刻工艺用金属层4形成包括源极41和漏极42的图形,得到如图11所示的结构。
也就是说,对第二光刻胶层92依次进行曝光、显影,然后对暴露的金属层4进行刻蚀,用其形成源极41、漏极42(还可同时形成数据线),该源极41、漏极42自然与有源区3的暴露区域接触。
S307和S308步骤中,剩余的第一光刻胶层91一直覆盖有源区3的“沟道”区域,起到了保护有源区3的“沟道”区域作用;且该剩余的第一光刻胶层91是在有源区3形成过程中剩余下来的,只要减少一次光刻胶剥离即可得到,而不必新增构图步骤,从而简化了阵列基板的制备工艺。
S309、除去剩余的第二光刻胶层92和第一光刻胶层91,得到如图12所示的结构。
可见,此时剩余的第一光刻胶层91和第二光刻胶层92均已暴露,故可将它们除去以进行后续步骤。
其中,具体的除去光刻胶的工艺可为先用氧气的等离子体进行干法刻蚀,之后再进行湿法刻蚀,从而彻底除去残留的光刻胶层;之所以采用两次刻蚀,是因为此时残留的第一光刻胶层91经过形成金属层4步骤中的高温,较难除去。当然,只要最终剩余的第二光刻胶层92和第一光刻胶层91全部被除去,也可采取其他的方法。
S310、在完成前述步骤的基底1上形成第一钝化层83,优选的,对基底1进行退火处理。
第一钝化层83可为氧化硅、氮化硅、氮氧化硅等的单层或多层结构,可由化学气相沉积等方法形成,作用是保护有源区3等;同时,第一钝化层83中还应形成有过孔,例如用于连接像素电极5和漏极42的过孔,以及用于连接公共电极6和公共电极线(可与栅极2同时形成)的过孔。
要注意的是,在本步骤中形成第一钝化层83的沉积温度优选控制在200℃以下,以免其对有源层产生破坏。
为了改善器件的稳定性,在形成第一钝化层83之后,还可进行退火,具体可为在250~350℃的温度下加热0.5~1.5小时。
S311、优选的,在完成前述步骤的基底1上形成平坦化层89。
平坦化层89可由树脂材料经曝光、烘干(烘干温度220~250℃)等步骤形成,之后还可进行干刻,从而在平坦化层89和第一钝化层83中形成过孔,例如用于连接像素电极5和漏极42的过孔,以及用于连接公共电极6和公共电极线的过孔。
S312、通过构图工艺形成包括像素电极5的图形。
用氧化铟锡等透明导电材料形成厚度30~50nm的像素电极5层,该像素电极5层可为板状,并通过平坦化层89和第一钝化层83中的过孔与漏极42相连。
S313、在完成前述步骤的基底1上形成第二钝化层84。
形成由氧化硅、氮化硅、氮氧化硅等构成的第二钝化层84,该第二钝化层84中可形成有用于连接公共电极6和公共电极线的过孔。
其中,第二钝化层84的沉积温度优选不超过平坦化层89的烘干温度。
S314、通过构图工艺形成包括公共电极6的图形,其结构如图13所示。
用氧化铟锡等透明导电材料形成厚度30~50nm的公共电极6层,该公共电极6层可为狭缝电极形式,并通过第二钝化层84、平坦化层89、第一钝化层83中的过孔与公共电极线相连。
S315、优选的,进行最终退火处理,得到高级超维场转换模式的阵列基板。
最终退火可提高器件的稳定性,并降低公共电极6的电阻,其温度优选不超过平坦化层89的烘干温度,一般在在200~250℃之间。
当然,应当理解,本实施例的具体方法可以是多样的;例如,其可先形成像素电极再形成公共电极;但也可先形成公共电极再形成像素电极(相应的过孔位置不同);或者,也可只形成像素电极,即本实施例的方法制备的也可以是扭曲向列模式模式的阵列基板。
可以理解的是,以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式,然而本发明并不局限于此。对于本领域内的普通技术人员而言,在不脱离本发明的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本发明的保护范围。
Claims (11)
1.一种阵列基板制备方法,其特征在于,包括:
S1、在基底上依次形成半导体材料层和第一光刻胶层,通过光刻工艺形成包括有源区的图形,至少在有源区用于在薄膜晶体管导通时导电的区域上剩余有第一光刻胶层;
S2、在完成前述步骤的基底上形成第一材料层,通过光刻工艺用第一材料层形成包括第一结构的图形。
2.根据权利要求1所述的阵列基板制备方法,其特征在于,
所述半导体材料层为金属氧化物半导体材料层。
3.根据权利要求1或2所述的阵列基板制备方法,其特征在于,
所述第一材料层为透明导电材料层;
所述第一结构为像素电极或公共电极。
4.根据权利要求3所述的阵列基板制备方法,其特征在于,
在所述步骤S1之前,还包括:在基底上通过构图工艺形成包括源极、漏极的图形;
所述步骤S1中剩余的第一光刻胶层与有源区重叠。
5.根据权利要求4所述的阵列基板制备方法,其特征在于,在所述通过构图工艺形成包括源极、漏极的图形步骤之前,还包括:
在基底上通过构图工艺形成包括栅极、栅线的图形;
在完成前述步骤的基底上形成栅绝缘层。
6.根据权利要求3所述的阵列基板制备方法,其特征在于,所述步骤S2包括:
S21、在完成前述步骤的基底上依次形成透明导电材料层和第二光刻胶层;
S22、通过光刻工艺用透明导电材料层形成包括像素电极或公共电极的图形;
S23、剥离剩余的第一光刻胶层和第二光刻胶层。
7.根据权利要求1或2所述的阵列基板制备方法,其特征在于,
所述第一材料层为金属层;
所述第一结构为源极和漏极。
8.根据权利要求7所述的阵列基板制备方法,其特征在于,在所述步骤S1中剩余的第一光刻胶层位于有源区用于在薄膜晶体管导通时导电的区域上,有源区用于与源漏极接触的区域无第一光刻胶层剩余。
9.根据权利要求8所述的阵列基板制备方法,其特征在于,所述步骤S1包括:
S11、在基底上依次形成半导体材料层和第一光刻胶层;
S12、通过梯度曝光工艺对第一光刻胶层进行曝光、显影,使对应有源区与源漏极接触区域的位置保留第一厚度的第一光刻胶层,对应有源区用于在薄膜晶体管导通时导电区域的位置保留第二厚度的第一光刻胶层,其余位置不保留第一光刻胶层,所述第一厚度小于第二厚度;
S13、除去无第一光刻胶层覆盖的半导体材料层,形成包括有源区的图形,并减薄剩余的第一光刻胶层,使所述第一厚度的第一光刻胶层被除去,所述第二厚度的第一光刻胶层减薄,在有源区用于在薄膜晶体管导通时导电的区域上剩余第一光刻胶层。
10.根据权利要求8所述的阵列基板制备方法,其特征在于,所述步骤S2包括:
S21、在完成前述步骤的基底上依次形成金属层和第二光刻胶层;
S22、通过光刻工艺用金属层形成包括源极和漏极的图形;
S23、除去剩余的第二光刻胶层和第一光刻胶层。
11.根据权利要求7所述的阵列基板制备方法,其特征在于,所述步骤S1之前,还包括:
在基底上通过构图工艺形成包括栅极、栅线的图形;
在完成前述步骤的基底上形成栅绝缘层。
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WO2016070581A1 (zh) * | 2014-11-06 | 2016-05-12 | 京东方科技集团股份有限公司 | 阵列基板制备方法 |
US9741751B2 (en) | 2014-11-06 | 2017-08-22 | Boe Technology Group Co., Ltd. | Array substrate fabricating method |
CN104810376A (zh) * | 2015-04-29 | 2015-07-29 | 京东方科技集团股份有限公司 | 像素单元、阵列基板及其制作方法、显示面板及显示装置 |
US10446586B2 (en) | 2015-04-29 | 2019-10-15 | Boe Technology Group Co., Ltd. | Pixel unit, array substrate and manufacturing method therefor, display panel and display device |
CN105116589A (zh) * | 2015-09-25 | 2015-12-02 | 深圳市华星光电技术有限公司 | 阵列基板、透光钝化膜及液晶显示面板的制造方法 |
WO2017049802A1 (zh) * | 2015-09-25 | 2017-03-30 | 深圳市华星光电技术有限公司 | 阵列基板、透光钝化膜及液晶显示面板的制造方法 |
WO2017177498A1 (zh) * | 2016-04-13 | 2017-10-19 | 武汉华星光电技术有限公司 | Tft基板及其制作方法 |
CN107402485A (zh) * | 2017-08-31 | 2017-11-28 | 合肥京东方显示技术有限公司 | 阵列基板及其制作方法、液晶显示设备及其制作方法 |
CN107706115A (zh) * | 2017-10-09 | 2018-02-16 | 深圳市华星光电半导体显示技术有限公司 | 一种薄膜晶体管及其制作方法 |
CN110875335A (zh) * | 2018-08-13 | 2020-03-10 | 三星显示有限公司 | 有机发光二极管显示装置 |
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CN104409413B (zh) | 2017-12-08 |
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