CN103748700B - 用于led封装的带有凹坑和通孔的基板 - Google Patents
用于led封装的带有凹坑和通孔的基板 Download PDFInfo
- Publication number
- CN103748700B CN103748700B CN201280025715.1A CN201280025715A CN103748700B CN 103748700 B CN103748700 B CN 103748700B CN 201280025715 A CN201280025715 A CN 201280025715A CN 103748700 B CN103748700 B CN 103748700B
- Authority
- CN
- China
- Prior art keywords
- substrate
- hole
- pit
- led chip
- led
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 80
- 238000005538 encapsulation Methods 0.000 title description 12
- 238000000034 method Methods 0.000 claims abstract description 53
- 239000002184 metal Substances 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 36
- 229910000679 solder Inorganic materials 0.000 claims description 19
- 239000000565 sealant Substances 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 13
- 239000012530 fluid Substances 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 7
- 238000011049 filling Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 239000000945 filler Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 description 8
- 239000000843 powder Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- -1 pottery Substances 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/50—Wavelength conversion elements
- H01L33/501—Wavelength conversion elements characterised by the materials, e.g. binder
- H01L33/502—Wavelength conversion materials
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Led Device Packages (AREA)
Abstract
本发明提供了含有多个发光二极管(LED)基板的晶圆以及制作LED基板的方法。晶圆的多个LED基板中的每个基板包括:衬底(201),包括通孔(203a);LED芯片(208),安装在衬底(201)的第一侧的凹坑(204)中并且连接至通孔(203a);再布线层(205a),附接至衬底(201)的第二侧并且通过通孔(203a)连接至LED芯片(208)。所述方法包括提供晶圆作为衬底(201);在衬底(201)的第一侧在衬底(201)中提供凹坑(204);在衬底(201)中提供通孔(203a),在衬底(201)的第二侧提供再布线层(205a),以及将LED(208)安装在凹坑(204)中,其中LED芯片(208)通过通孔(203a)连接至再布线层(205a)。
Description
相关申请的交叉引用
本申请要求于2011年6月1日提交的美国临时专利申请No.61/457,774的优先权,其以引用方式并入本文。
技术领域
本发明涉及发光二极管,更具体地讲,涉及封装发光二极管的结构及方法。
背景技术
LED(发光二极管)具有功耗低、寿命长、体积小、反应快等优点,有望取代传统白炽灯及荧光灯作为未来的主要光源。目前常用荧光粉转换的方法来制得白光LED,为荧光粉转换LED(pc-LED),即在蓝色LED芯片上覆盖黄色荧光粉,通过蓝光激发黄光并最终混合成白光。相比其他方法,如RGB三色LED或者紫外线LED转换,这种方法由于结构简单、成本相对低廉而大量被采用。
据估计未来5-10年LED将会大范围取代白炽灯及荧光灯。影响HB-LED(高亮度LED)在SSL(固态照明)方面的推广应用有两大主要因素:发光效率以及成本。这两个因素都与LED封装有密切的关系。然而,大部分传统LED封装方法都需要采用模具及***部件来实现荧光粉涂覆或者透镜成型,其成本及散热都有待改进。另外,为了获得高功率LED,需要改进热性能。因此,市场需要一种简单而高效的方法来对LED进行封装以在达到良好的光效率和热管理的同时实现较低成本制造。
图1是传统LED封装100的截面图。在这种封装结构中,LED芯片113通过焊点115以倒装芯片方式被焊至包含了金属电路(未示出)的平面硅基板117,所述金属电路用于在LED芯片113和基板117之间建立电连接。与LED芯片113焊接在一起的基板117通过粘合剂119被粘接至散热片101上。而且,LED封装100包括引线107,其被塑料外壳105保持并且通过导线103焊接至硅基板117,以实现电连接。然后,预制的透镜(密封胶)111盖住LED芯片113、导线103及基板117。整个封装最后被贴至板109(例如,印刷电路版(PCB))上以实现电气互联和散热。
图1所示的这种制造LED封装100的工艺成本高。而且,传统LED芯片都是单独封装,因此不适用于高密度及低成本的大规模生产。
发明内容
在一个实施例中,本发明提供了一种晶圆,其具有多个发光二极管(LED)基板。晶圆的多个LED基板中的每个基板上含有:衬底,包括通孔;LED芯片,其安装在衬底第一侧的凹坑内并且连接至通孔;以及再布线层,其附接至基板第二侧并且通过通孔连接至LED芯片。
在另一个实施例中,本发明提供一种制造发光二极管(LED)基板的方法。该方法包括提供晶圆作为衬底;在衬底第一侧衬底中形成凹坑;在衬底中形成通孔;在衬底第二侧形成再布线层;以及将LED芯片安装在凹坑内,其中LED芯片通过通孔与再布线层相连。形成通孔的制程包括在衬底第二侧在衬底中形成盲孔;用金属填充盲孔;以及对衬底进行蚀刻,以在凹坑中暴露盲孔中的金属以形成通孔。形成再布线层的步骤包括:在衬底第二侧上形成金属层;以及图案化金属层以形成再布线层。
附图说明
尽管所附权利要求具体阐述了本发明的特征,但是根据以下结合附图的详细描述能够更好地理解本发明及其目的和优点:
图1是传统LED封装的示例的示意图;
图2是示出本发明的LED基板的部件的示意图;
图3(a)至图3(h)显示了本发明的LED基板制作的各个步骤的示意图;
图4显示了根据本发明的带有透明或半透明盖板的LED基板的示意图;
图5显示了根据本发明的具有透明或半透明盖板和混合有荧光粉的密封胶层的LED基板的示意图;以及
图6显示了根据本发明的LED基板的凹坑设置的反射层的示意图。
具体实施方式
本发明的实施例描述了用于LED封装的具有凹坑和通孔的基板的结构和制造方法。在一个实施例中,该方法开始于在基板背面制作盲孔并且在正面制作凹坑。基板的材料可以并不限于硅、PCB、MCPCB、BT、玻璃、陶瓷、塑料、金属或由其他材料制备。应当理解,在整个说明书中,“盲孔”指没有穿透整个基板的小孔。制作在衬底背面的盲孔可以通过例如电镀的方法填充金属,例如铜,该电镀方法还可以在基板背面覆盖金属。然后,将正面的凹坑进一步向下蚀刻以暴露出金属,形成通孔(也被称作“硅通孔”(TSV)),其将基板正面和基板底面连接。还应当理解的是,LED芯片被安装在凹坑内(如以下参照附图3(g)进一步描述)。然后,对基板背面的金属层进行图案化,使其具有期望电路。
该工艺产生的通孔结构可以实现基板正面到背面的三维(3D)连接,这样一来,电气连接不仅可以在基板的正面和反面上各自实现(即,“水平连接”),而且可以透过通孔实现基板的正面和反面之间的互联(即,“垂直连接”)。正面的凹坑可以实现通过印刷或者注入方法进行密封胶填充,从而不必使用模具来涂覆LED芯片。密封胶可以与荧光粉混合来保护LED芯片并且将蓝光转换成黄光并最终形成白光。应当理解,该制程解决了传统LED封装工艺中难以在基板正面凹坑底部进行金属布线的问题。
将参照图2至图6更详细描述本发明的实施例。参照图2,显示了根据一个实施例的LED封装结构中的基板200的横截面的示意图。该封装结构包含核心衬底201、绝缘层202a和202b、衬底背面的通孔203a、衬底正面的凹坑204、衬底背面的再布线层205a、将凹坑204底部与基板背面连接的金属柱206、焊料凸块207、LED芯片208、和混合了荧光粉的密封胶209。
应当理解,图2至图6中展示的基板是包括大量这种基板的一片晶圆上的其中一个基板,例如,数万个这种单元。以下参照图3(a)至图3(h)和图4至图6描述的制程将在晶圆上同时制作出多个LED封装。以下描述的制作完毕之后,再将晶圆分割以形成单独的封装。
参照图3(a)到图3(h),显示了根据本发明一个实施例的制作LED封装结构的整个方法的各个步骤中的LED封装结构的截面图。首先,如图3(a),在核心衬底201上通过诸如沉积、扩散、印刷等工艺制作绝缘层202a和202b。通过诸如蚀刻或机械钻孔等工艺在背面制作盲孔203和在正面制作凹坑204。对于蚀刻工艺,绝缘层202a和202b可以作为正面及背面的蚀刻掩膜。设置盲孔203及凹坑204之后,绝缘层202a可能需要通过进一步沉积、扩散或印刷等工艺重新制作或延伸以覆盖盲孔203的侧壁。
如图3(b)所示,在盲孔203内部填充金属以形成金属柱206。可以采用电镀工艺实现填充。覆盖在衬底201背面的金属层205可以在填充盲孔203形成金属柱206的制程中同时制得,也可以在后续工序中制得(例如,在以下参照图3(c)描述的进一步加深凹坑204之后)。例如,可以通过溅射或蒸镀等其他工艺制得金属层205和金属柱206。
如图3(c),可以通过诸如蚀刻、机械研磨的方式将正面凹坑204变深,以暴露出金属柱206。金属柱206顶端暴露之后,盲孔203将变成连接基板正面和基板底面的通孔203a。
如图3(d)所示,焊料207a被电镀至金属柱206顶端。该工艺可以通过电镀实现。在一个实施例中,通过以下步骤来执行电镀:将晶圆的金属层连接至阴极(如图3(d)中的电极221a和221b所示)并且将焊料板连接至阳极(未示出)以及将二者浸入电镀液,从而当施加电流时,焊料离子从焊料盘释放出来溶解在电镀液中。这些离子沉积在连接至阴极的金属柱206的暴露的金属表面上,从而在金属柱206顶端形成焊料207a。各个金属柱206通过背面的金属层205连接起来,金属层205被绝缘层220覆盖以防止金属层205被电镀有焊料。在电镀工艺结束并且获得焊料207a之后,去除绝缘层220,而金属层205应当保持附着。在一个示例中,绝缘层220是通过热扩散或化学气相沉积工艺附着而通过有机溶剂去除的光刻胶。应当理解,图3(d)所示的电极221a和221b并不需要连接至晶圆上的每个基板,这是因为在制造工艺的这步骤中每个基板之间的金属层是相互连接的。因此,可以执行电镀,只要电极221a和221b接触晶圆的金属层的每个区域即可。
如图3(e)所示,整片基板通过回流焊工艺,形成焊料凸块207。在一个示例中,所使用的回流焊炉包含有若干加热区及传送带。包含了一个或若干个基板的晶圆被放在传送带上通过不同的加热区。晶圆在受控回流温度曲线下在焊炉中被加热及冷却。在此过程中,通过首先在腔室内熔化焊料207a然后将其冷却再次凝固,从而在表面张力作用下使得焊料207a变成球状(焊料凸块207)。
如图3(f)所示,在基板背面金属层205通过图形化制程形成再布线层205a,将金属柱206互相连接形成所需的电路图形。在一个示例中,实现图形化制程的工艺可以采用例如光刻工艺。在安装了LED之后,两个或多个电路轨迹连接至每个LED芯片的阳极和阴极,以使得直流通过该器件并且点亮LED。
如图3(g)所示,LED芯片208被安装至凹坑204中焊料凸块207上。在一个示例中,这可以利用回流焊炉通过使用传统倒装芯片安装技术来实现。应当理解,单个凹坑204可以包含不止一个LED芯片,这取决于设计需要。例如,在另一个实施例中,凹坑204包含三个LED芯片,其中含有红、绿、蓝光LED芯片,所有LED芯片均安装在同一凹坑内。在另一个实施例中,凹坑包含四个LED芯片,其中包括一个红光LED芯片、一个蓝光LED芯片和两个绿光LED芯片。不同LED芯片可以通过连接到各自LED芯片的电路进行独立控制。
如图3(h)所示,例如通过针分配或者丝网印刷,密封胶209被填充至凹坑204内。通过固化工艺使密封胶凝固以保护LED芯片208。用于密封胶209的材料可以是硅胶或者树脂,可以是透明或者半透明,或者可以混合荧光粉以用于转换LED发出的光(例如,从蓝光转换为白光)。在图3(h)中,密封胶209填充凹坑204并且给LED封装结构正面形成一个平坦的水平面。应当理解,在其他实施例中,密封胶209可以具有其他形状,例如超出凹坑204尺寸的圆屋顶形。
图4显示了本发明的另一个实施例。该基板的制作工艺与之前参照图3(a)到图3(h)描述的工艺类似,进一步地,在基板上表面覆盖了一层透明或者半透明盖板210。在一个示例中,通过晶圆焊接来增加盖板210。荧光粉层可以涂覆在盖板210上,如图5所示,以避免荧光粉层与LED芯片直接接触(该结构通常被称为远程荧光粉结构)。该结构有助于避免荧光粉被加热,从而能够提高LED性能。
图5显示了本发明的另一个实施例。基板的制作工艺与之前参照图3(a)到图3(h)及图4描述的工艺类似,进一步地,如图所示,混合有荧光粉的密封胶209被涂覆在盖板210上。凹坑204可以填充另一种类型的密封胶,或者不填充。在一个示例中,同样类型的密封胶209可以被用于填充凹坑204也可用于涂覆在盖板210上。
图6显示了本发明的另一个实施例,其中,在制造工艺期间,在凹坑204表面可以通过诸如印刷、沉积、扩散、或溅射等方法形成反光层230以增强从LED芯片208发出的光的反射,如图6所示。在一个示例中,通过溅射或蒸发工艺来产生该层。
传统工艺对LED芯片进行单独封装并需要模具来制作透镜,应当理解,本发明的实施例提出了允许例如使用硅晶圆作为衬底的多个LED的晶圆级封装(WLP)的工艺及结构,可以同时在同一片晶圆上对大量LED芯片进行封装。WLP提供了批量制造和元件集成的优点,这可以通过用“通孔”结构进行三维互连和高效散热来实现。另外,本发明实施例提供了用于光反射的凹坑结构并且能够实现无需模具的荧光粉涂覆及密封工艺。
在此引用的包括出版物、专利申请和专利的所有参考文献以引用方式整体并入本文,其程度与单独和明确指示将每个参考文献并入的相同。
描述本发明的上下文中(尤其是在随附的权利要求书的上下文中)使用的术语“一个”、“一种”、“该”和“所述”应当被理解为包括单数形式和复数形式,除非明确指出或者通过上下文理解存在明显的矛盾。术语“包括”、“具有”、“包含”等应当被理解为开放性术语(即,意味着“包括,但不限于”),除非另外明确指出。本文中的数值范围的描述仅仅用作单独引用落入该范围内的每个单独值的快速方法,除非另外明确指出,并且每个单独的值以其被单独描述一样包含于本发明说明书中。本文描述的所有方法可以以任意合适顺序执行,除非另外明确指出或者通过上下文理解存在明显的矛盾。本文中的任何和所有示例或者示例性语言(例如,“诸如”)的使用仅仅用于更好地描述本发明而不是限制本发明的保护范围,除非另外明确指出。说明书中的语言都不应当解释为对实施本发明而言必不可少的任何未要求保护的要素。
在此描述了本发明的优选实施例,其中包括发明人已知的实现本发明的最佳方式。对于所属领域技术人员而言,通过阅读以上描述,这些优选实施例的变型将变得显而易见。发明人希望所属领域的技术人员能够适当地采用这些变型,发明人希望本发明能被实施,而不是仅仅在此进行描述。因此,本发明包括使用法律所允许的所附权利要求中阐述的主题的所有变型和等价物。而且,上述要素的任何可能变型的任意组合都应当包含在本发明的范围内,除非本文明确指出或者通过上下文分析存在明显的矛盾。
Claims (8)
1.一种制作LED基板的方法,包括:
提供晶圆作为衬底;
在衬底第一侧的衬底中设置凹坑;
在衬底中设置通孔,其中设置通孔还包括:
在衬底第二侧的衬底中设置盲孔;
在盲孔内填充金属;以及
从第一侧,蚀刻衬底以在凹坑中暴露盲孔中的金属从而产生通孔;
在衬底第二侧上设置再布线层,其中设置再布线层还包括:
在衬底的第二侧上设置金属层;以及
将金属层图形化以产生再布线层;
在凹坑内安装LED芯片,其中LED芯片通过通孔与再布线层相连。
2.权利要求1所述的方法,其中LED芯片安装在凹坑内焊料凸块上,所述焊料凸块接触LED芯片和通孔,所述方法进一步包括:
给凹坑内暴露的通孔内的金属镀焊料;以及
处理焊料以形成焊料凸块。
3.权利要求1所述的方法,进一步包括:
在基板的第一侧上形成第一绝缘层;
在基板的第二侧上形成第二绝缘层,其位于基板与再布线层之间;以及
使通孔内的金属和基板绝缘。
4.权利要求1所述的方法,进一步包括:
在凹坑内填充密封胶。
5.权利要求1所述的方法,其中LED芯片是蓝光LED芯片,并且密封胶混合有荧光粉从而在LED芯片启动时发出白光。
6.权利要求1所述的方法,进一步包括:
在基板第一侧附着透明或半透明盖板。
7.权利要求6所述的方法,进一步包括:
在透明或半透明盖板上涂覆混有荧光粉的密封胶层。
8.权利要求1所述的方法,进一步包括:
在凹坑内形成反射层。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201161457774P | 2011-06-01 | 2011-06-01 | |
US61/457,774 | 2011-06-01 | ||
PCT/CN2012/000752 WO2012163086A1 (en) | 2011-06-01 | 2012-06-01 | Submount with cavities and through vias for led packaging |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103748700A CN103748700A (zh) | 2014-04-23 |
CN103748700B true CN103748700B (zh) | 2016-11-16 |
Family
ID=47258346
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201280025715.1A Active CN103748700B (zh) | 2011-06-01 | 2012-06-01 | 用于led封装的带有凹坑和通孔的基板 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9431592B2 (zh) |
CN (1) | CN103748700B (zh) |
WO (1) | WO2012163086A1 (zh) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9502612B2 (en) * | 2009-09-20 | 2016-11-22 | Viagan Ltd. | Light emitting diode package with enhanced heat conduction |
US9620436B2 (en) | 2014-04-09 | 2017-04-11 | Invensas Corporation | Light emitting diode device with reconstituted LED components on substrate |
JP2016081959A (ja) * | 2014-10-10 | 2016-05-16 | シチズン電子株式会社 | 発光装置及びその製造方法 |
CN104638091B (zh) * | 2014-12-18 | 2017-10-24 | 上海大学 | Led玻璃基板 |
CN104600039B (zh) * | 2014-12-26 | 2018-01-16 | 通富微电子股份有限公司 | 双面互联扇出工艺 |
CN104701437A (zh) * | 2015-03-09 | 2015-06-10 | 武汉大学 | 一种三维led发光器件 |
CN104659178A (zh) * | 2015-03-09 | 2015-05-27 | 武汉大学 | 一种功率型三维led发光器件及其制造方法 |
US9847230B2 (en) * | 2015-06-09 | 2017-12-19 | The Charles Stark Draper Laboratory, Inc. | Method and apparatus for using universal cavity wafer in wafer level packaging |
JP6711568B2 (ja) * | 2015-07-29 | 2020-06-17 | ローム株式会社 | 半導体装置 |
US10483253B1 (en) | 2015-09-24 | 2019-11-19 | Apple Inc. | Display with embedded pixel driver chips |
US10665578B2 (en) | 2015-09-24 | 2020-05-26 | Apple Inc. | Display with embedded pixel driver chips |
CN105575956B (zh) * | 2015-12-31 | 2017-11-17 | 中国科学院半导体研究所 | Led芯片集成封装模块和封装方法 |
JP2017175000A (ja) * | 2016-03-24 | 2017-09-28 | ローム株式会社 | 電子部品およびその製造方法、ならびに、インターポーザ |
JP6748501B2 (ja) * | 2016-07-14 | 2020-09-02 | ローム株式会社 | 電子部品およびその製造方法 |
KR20190140352A (ko) * | 2018-06-11 | 2019-12-19 | 서울반도체 주식회사 | 발광 다이오드 패키지 |
WO2020037677A1 (zh) * | 2018-08-24 | 2020-02-27 | 深圳市汇顶科技股份有限公司 | 发光器件的封装方法、封装结构及电子设备 |
DE102018122166A1 (de) * | 2018-09-11 | 2020-03-12 | Osram Opto Semiconductors Gmbh | Optoelektronische halbleitervorrichtung mit einem trägerelement und einem elektrischen kontaktelement, optoelektronisches bauelement sowie verfahren zur herstellung der optoelektronischen halbleitervorrichtung |
US10957832B2 (en) * | 2018-10-22 | 2021-03-23 | General Electric Company | Electronics package for light emitting semiconductor devices and method of manufacturing thereof |
CN109786540B (zh) * | 2019-01-24 | 2021-07-23 | 南通沃特光电科技有限公司 | 一种led封装结构及其封装方法 |
CN109683396A (zh) * | 2019-01-30 | 2019-04-26 | 厦门天马微电子有限公司 | 背光模组、显示面板、显示装置及背光模组的制作方法 |
KR20210087751A (ko) * | 2020-01-03 | 2021-07-13 | 삼성전자주식회사 | 반도체 패키지 |
CN111883494B (zh) * | 2020-07-21 | 2022-11-29 | 联合微电子中心有限责任公司 | 功率mosfet器件及其形成方法 |
WO2023177719A1 (en) * | 2022-03-16 | 2023-09-21 | Uviquity, Inc. | Micro-leds configured for operation at wavelengths in the far-uvc spectrum |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN201804913U (zh) * | 2010-09-30 | 2011-04-20 | 江阴长电先进封装有限公司 | 圆片级led封装结构 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6632892B2 (en) * | 2001-08-21 | 2003-10-14 | General Electric Company | Composition comprising silicone epoxy resin, hydroxyl compound, anhydride and curing catalyst |
JP4754850B2 (ja) | 2004-03-26 | 2011-08-24 | パナソニック株式会社 | Led実装用モジュールの製造方法及びledモジュールの製造方法 |
KR100623024B1 (ko) | 2004-06-10 | 2006-09-19 | 엘지전자 주식회사 | 고출력 led 패키지 |
US7745832B2 (en) * | 2004-09-24 | 2010-06-29 | Epistar Corporation | Semiconductor light-emitting element assembly with a composite substrate |
KR100782798B1 (ko) | 2006-02-22 | 2007-12-05 | 삼성전기주식회사 | 기판 패키지 및 그 제조 방법 |
US7808004B2 (en) | 2006-03-17 | 2010-10-05 | Edison Opto Corporation | Light emitting diode package structure and method of manufacturing the same |
US8969908B2 (en) | 2006-04-04 | 2015-03-03 | Cree, Inc. | Uniform emission LED package |
US20080179618A1 (en) | 2007-01-26 | 2008-07-31 | Ching-Tai Cheng | Ceramic led package |
KR20100022960A (ko) * | 2007-04-27 | 2010-03-03 | 스미토모 베이클리트 컴퍼니 리미티드 | 반도체 웨이퍼의 접합 방법 및 반도체 장치의 제조 방법 |
JP4809308B2 (ja) * | 2007-09-21 | 2011-11-09 | 新光電気工業株式会社 | 基板の製造方法 |
US20090121252A1 (en) * | 2007-11-14 | 2009-05-14 | Hung-Tsung Hsu | Method for manufacturing flip-chip light emitting diode package |
US8093711B2 (en) * | 2009-02-02 | 2012-01-10 | Infineon Technologies Ag | Semiconductor device |
US8552563B2 (en) * | 2009-04-07 | 2013-10-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional semiconductor architecture |
US8742591B2 (en) * | 2011-12-21 | 2014-06-03 | Stats Chippac, Ltd. | Semiconductor device and method of forming insulating layer in notches around conductive TSV for stress relief |
-
2012
- 2012-06-01 US US14/122,929 patent/US9431592B2/en active Active
- 2012-06-01 WO PCT/CN2012/000752 patent/WO2012163086A1/en active Application Filing
- 2012-06-01 CN CN201280025715.1A patent/CN103748700B/zh active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN201804913U (zh) * | 2010-09-30 | 2011-04-20 | 江阴长电先进封装有限公司 | 圆片级led封装结构 |
Also Published As
Publication number | Publication date |
---|---|
US20140110728A1 (en) | 2014-04-24 |
US9431592B2 (en) | 2016-08-30 |
WO2012163086A1 (en) | 2012-12-06 |
CN103748700A (zh) | 2014-04-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103748700B (zh) | 用于led封装的带有凹坑和通孔的基板 | |
CN100539218C (zh) | 用于安装发光器件的辅助底座和发光器件封装 | |
CN104078551B (zh) | 发光装置及其制造方法 | |
CN104854716B (zh) | Led装置及其制造方法 | |
CN104956500B (zh) | 无次基台的发光二极管(led)部件及其制作方法 | |
US8053259B2 (en) | Manufacturing method of light emitting diode | |
US20090114937A1 (en) | Resin-sealed light emitting device and its manufacturing method | |
CN102263194A (zh) | 半导体封装与制造半导体封装的方法 | |
CN102176504B (zh) | 发光器件封装件及制造其方法 | |
CN102610599B (zh) | 发光器件封装件及其制造方法 | |
CN101578712A (zh) | 发光装置及其制造方法和安装基板 | |
CN101997074A (zh) | 一种基于硅基板的led表面贴片式封装结构及其封装方法 | |
US20110101392A1 (en) | Package substrate for optical element and method of manufacturing the same | |
CN101388426B (zh) | 一种发光半导体晶片和发光半导体组件的制造方法 | |
CN104969368B (zh) | 基于基板的表面贴装器件(smd)发光组件以及方法 | |
CN101126485A (zh) | 具发光二极管的光源模块及其形成方法 | |
JP4593201B2 (ja) | チップ部品型発光装置及びそのための配線基板 | |
CN205863219U (zh) | 一种多管芯的led封装 | |
CN105304791A (zh) | 表面安装发光器件 | |
CN102104105A (zh) | 用于光学元件的封装基板及其制备方法 | |
CN107534076B (zh) | Led封装体、发光装置以及led封装体的制造方法 | |
CN105789389B (zh) | Led芯片的模组化封装方法 | |
CN103972223A (zh) | Led多杯集成一体化cob光源及其封装方法 | |
CN106025047A (zh) | 一种led的封装及其封装方法 | |
CN104538529A (zh) | 一种低成本的led封装结构及其晶圆级封装方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |