CN104600039B - 双面互联扇出工艺 - Google Patents

双面互联扇出工艺 Download PDF

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CN104600039B
CN104600039B CN201410831056.1A CN201410831056A CN104600039B CN 104600039 B CN104600039 B CN 104600039B CN 201410831056 A CN201410831056 A CN 201410831056A CN 104600039 B CN104600039 B CN 104600039B
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丁万春
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Tongfu Microelectronics Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
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    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof

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Abstract

本发明涉及一种双面互联扇出工艺,在晶圆的顶面开设多个盲孔;在盲孔内形成第一导电柱及再造的芯片;在晶圆的顶面上形成塑封层,塑封层暴露出第一导电柱及第二导电柱的顶面;在塑封层上形成第一再布线金属层;在第一再布线金属层上形成第一钝化层,第一钝化层形成第一开口;在第一开口处形成上凸点;减薄晶圆,直至露出第一导电柱的底面;在晶圆的底面形成第二钝化层,第二钝化层设置有暴露第一导电柱底面及芯片顶面的第二开口;在第二开口处形成背部接电结构。采用该工艺形成的芯片,可以进行堆叠封装。同时背部接电结构会在第二开口处形成金属层,可用于对芯片进行散热,降低热阻,特别是对于高功耗的芯片,其能更好的保证芯片的正常工作。

Description

双面互联扇出工艺
技术领域
本发明涉及半导体封装技术领域,尤其涉及一种双面互联扇出工艺。
背景技术
目前,在半导体加工的扇出工艺中,通常采用单面层积的工艺进行加工,在用此种加工工艺,可以实现将单个芯片进行放大,或者实现多个芯片进行并排连接。但是,不能实现芯片的堆叠封装。
发明内容
在下文中给出关于本发明的简要概述,以便提供关于本发明的某些方面的基本理解。应当理解,这个概述并不是关于本发明的穷举性概述。它并不是意图确定本发明的关键或重要部分,也不是意图限定本发明的范围。其目的仅仅是以简化的形式给出某些概念,以此作为稍后论述的更详细描述的前序。
本发明的目的在于提供一种双面互联扇出工艺。本发明提供一种双面互联扇出工艺,包括以下步骤:
在晶圆的顶面上开设多个盲孔;
在所述盲孔内形成第一导电柱,并且以倒置的方式安放至少一个芯片,所述芯片的焊垫上形成有第二导电柱,所述第一导电柱的顶部及所述第二导电柱的顶部均高于所述晶圆的顶面;
在所述晶圆的顶面上形成塑封层,所述塑封层暴露出所述第一导电柱及所述第二导电柱的顶面;
在所述塑封层上形成与所述第一导电柱及所述第二导电柱相连接的第一再布线金属层;
在所述第一再布线金属层上形成第一钝化层,所述第一钝化层形成有暴露所述第一再布线金属层的第一开口;
在所述第一开口处形成与所述第一再布线金属层连接的上凸点;
对所述晶圆的底部进行减薄,直至露出所述第一导电柱的底面;
在减薄后的所述晶圆的底面形成第二钝化层,所述第二钝化层设置有暴露所述第一导电柱底面及所述芯片顶面的第二开口;
在所述第二开口处形成背部接电结构。
采用本发明工艺形成的芯片,在顶部和底部均形成了接电的结构,使得使用本发明工艺形成的芯片可以进行芯片的堆叠封装。另外,在形成背部接电结构时,同时会在第二钝化层暴露芯片顶部的第二开口处形成金属层,该金属层可用于对芯片进行散热,降低热阻,特别是对于高功耗的芯片,其能更好的保证芯片的正常工作。
附图说明
参照下面结合附图对本发明实施例的说明,会更加容易地理解本发明的以上和其它目的、特点和优点。附图中的部件只是为了示出本发明的原理。在附图中,相同的或类似的技术特征或部件将采用相同或类似的附图标记来表示。
图1为本发明实施例提供的双面互联扇出工艺的流程图。
图2a-图2o为实施本发明实施例提供的双面互联扇出工艺各步骤所形成的结构示意图。
具体实施方式
下面参照附图来说明本发明的实施例。在本发明的一个附图或一种实施方式中描述的元素和特征可以与一个或更多个其它附图或实施方式中示出的元素和特征相结合。应当注意,为了清楚的目的,附图和说明中省略了与本发明无关的、本领域普通技术人员已知的部件和处理的表示和描述。
图1为本发明实施例提供的双面互联扇出工艺的流程图。如图1所示,本发明实施例提供的双面互联扇出工艺,包括以下步骤:
S101:在晶圆的顶面上开设多个盲孔;
S102:在所述盲孔内形成第一导电柱,并且以倒置的方式安放至少一个芯片,所述芯片的焊垫上形成有第二导电柱,所述第一导电柱的顶部及所述第二导电柱的顶部均高于所述晶圆的顶面;
S103:在所述晶圆的顶面上形成塑封层,所述塑封层暴露出所述第一导电柱及所述第二导电柱的顶面;
S104:在所述塑封层上形成与所述第一导电柱及所述第二导电柱相连接的第一再布线金属层;
S105:在所述第一再布线金属层上形成第一钝化层,所述第一钝化层形成有暴露所述第一再布线金属层的第一开口;
S106:在所述第一开口处形成与所述第一再布线金属层连接的上凸点;
S107:对所述晶圆的底部进行减薄,直至露出所述第一导电柱的底面;
S108:在减薄后的所述晶圆的底面形成第二钝化层,所述第二钝化层设置有暴露所述第一导电柱底面及所述芯片顶面的第二开口;
S109:在所述第二开口处形成背部接电结构。
采用本发明工艺形成的芯片,在顶部和底部均形成了接电的结构,使得使用本发明工艺形成的芯片可以进行芯片的堆叠封装。另外,在形成背部接电结构时,同时会在第二钝化层暴露芯片顶部的第二开口处形成金属层,该金属层可用于对芯片进行散热,降低热阻,特别是对于高功耗的芯片,其能更好的保证芯片的正常工作。
实施本发明实施例提供的双面互联扇出工艺,具体地,如图2a所示,提供一晶圆1,在晶圆1的顶面镭射刻蚀标记。如图2b所示,在晶圆1的顶面上对应于刻蚀标记的位置处形成多个盲孔2。多个盲孔2可以通过刻蚀的方式加工。如图2c所示,在盲孔2内形成第一导电柱3,第一导电柱3的设置位置及设置数量根据实际需要确定。第一导电柱3的顶部高于晶圆1的顶面。作为一种可实现方式,第一导电柱3可以采用铜柱。如图2d所示,在盲孔内以倒置的形式放置至少一个芯片,芯片位于第一导电柱之间。每个盲孔2内可以设置一个或多个芯片4,芯片4的设置数量根据实际需要确定。需要说明的是,再将芯片放置于盲孔内之前,首先对芯片进行再造,也即在芯片的焊垫上形成第二导电柱,第二导电柱可以是铜柱。如图2e所示,在晶圆1的顶部形成塑封层5,塑封层5包覆第一导电柱3及芯片4上的第二导电柱6顶部。如图2f所示,打磨所述塑封层5的顶部,直至所述第一导电柱3及所述第二导电柱6的顶面露出所述塑封层的顶面,且所述第一导电柱3及所述第二导电柱的顶面与所述塑封层的顶面平齐。如图2g所示,在塑封层5上形成与所述第一导电柱3及所述第二导电柱6相连接的第一再布线金属层7。如图2h所示,在第一再布线金属层7上形成第一钝化层8,第一钝化层8形成有暴露第一再布线金属层7的第一开口9。如图2i所示,在第一开口处9形成与第一再布线金属层7连接的上凸点10。如图2j所示,在第一钝化层8上形成包覆上凸点10的封胶层11,通过封胶层11将形成上凸点后的晶圆结构粘接到载具12上。如图2k所示,对晶圆1的底部进行减薄,直至露出第一导电柱3的底面及芯片4的底面。可以通过打磨的方式来对晶圆1进行减薄操作。如图2l所示,在减薄后的晶圆的底面形成第二钝化层13,第二钝化层13设置有暴露第一导电柱3底面及芯片4顶面的第二开口14。在第二开口14处形成背部接电结构。背部接电结构可以根据需要,设计成多种结构形式,例如,如图2m所示,接电结构可以是在第二钝化层13上形成第二再布线金属层15,及在第二再布线金属层上形成焊盘16。当然,接电结构还可以是形成在第二钝化层上的下凸点,或者是形成在第二钝化层上的第二再布线金属层,及在第二再布线金属层上形成的下凸点。如图2n所示,自第二钝化层切割至封胶层,在相邻的封装间形成切割槽17。如图2o所示,去除封胶层,形成多个双面互联的封装芯片18。
在本发明的设备和方法中,显然,各部件或各步骤是可以分解、组合和/或分解后重新组合的。这些分解和/或重新组合应视为本发明的等效方案。还需要指出的是,执行上述系列处理的步骤可以自然地按照说明的顺序按时间顺序执行,但是并不需要一定按照时间顺序执行。某些步骤可以并行或彼此独立地执行。同时,在上面对本发明具体实施例的描述中,针对一种实施方式描述和/或示出的特征可以以相同或类似的方式在一个或更多个其它实施方式中使用,与其它实施方式中的特征相组合,或替代其它实施方式中的特征。

Claims (5)

1.一种双面互联扇出工艺,其特征在于,包括以下步骤:
在晶圆的顶面上开设多个盲孔;
在所述盲孔内形成第一导电柱,并且以倒置的方式安放至少一个芯片,所述芯片的焊垫上形成有第二导电柱,所述第一导电柱的顶部及所述第二导电柱的顶部均高于所述晶圆的顶面;
在所述晶圆的顶面上形成塑封层,所述塑封层暴露出所述第一导电柱及所述第二导电柱的顶面;
在所述塑封层上形成与所述第一导电柱及所述第二导电柱相连接的第一再布线金属层;
在所述第一再布线金属层上形成第一钝化层,所述第一钝化层形成有暴露所述第一再布线金属层的第一开口;
在所述第一开口处形成与所述第一再布线金属层连接的上凸点;
对所述晶圆的底部进行减薄,直至露出所述第一导电柱的底面;
在减薄后的所述晶圆的底面形成第二钝化层,所述第二钝化层设置有暴露所述第一导电柱底面及所述芯片顶面的第二开口;
在所述第二开口处形成背部接电结构,具体为:在所述第二钝化层上形成第二再布线金属层,所述第二再布线金属层分别与所述第一导电柱的底面及所述芯片的顶面连接,在所述第二再布线金属层上形成下凸点;或者,
在所述第二钝化层上形成第二再布线金属层,所述第二再布线金属层分别与所述第一导电柱的底面及所述芯片的顶面连接,在所述第二再布线金属层上形成焊盘。
2.如权利要求1所述的双面互联扇出工艺,其特征在于,所述在所述晶圆的顶面上形成塑封层,所述塑封层暴露出所述第一导电柱及所述第二导电柱的顶面,具体为:
在所述晶圆的顶面上形成塑封层,所述塑封层包覆所述第一导电柱及所述第二导电柱的顶部,减薄所述塑封层的顶部,直至所述第一导电柱及所述第二导电柱的顶面露出所述塑封层的顶面,且所述第一导电柱及所述第二导电柱的顶面与所述塑封层的顶面平齐。
3.如权利要求1所述的双面互联扇出工艺,其特征在于,所述在所述第一开口处形成与所述第一再布线金属层连接的上凸点之后,还包括:
在所述第一钝化层上形成包覆所述上凸点的封胶层,通过所述封胶层将形成上凸点后的晶圆结构粘接到载具上。
4.如权利要求3所述的双面互联扇出工艺,其特征在于,自所述第二钝化层切割至所述封胶层,去除所述封胶层,形成多个双面互联的芯片。
5.如权利要求1-3任一项所述的双面互联扇出工艺,其特征在于,所述第一导电柱及所述第二导电柱均为铜柱。
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