CN103715184A - 基于柔性基板的三维多芯片存储***封装结构及制作方法 - Google Patents

基于柔性基板的三维多芯片存储***封装结构及制作方法 Download PDF

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CN103715184A
CN103715184A CN201310721105.1A CN201310721105A CN103715184A CN 103715184 A CN103715184 A CN 103715184A CN 201310721105 A CN201310721105 A CN 201310721105A CN 103715184 A CN103715184 A CN 103715184A
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flexible base
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徐健
陆原
孙鹏
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National Center for Advanced Packaging Co Ltd
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Abstract

本发明提供了一种基于柔性基板的三维多芯片存储***封装结构，有效保证高速信号线的信号完整性，同时大大降低了晶片材料和封装的成本，从而提高了市场竞争能力，其包括柔性基板，所述柔性基板上设置有第一芯片、第二芯片、电容或者电阻，所述第一芯片和所述第二芯片分别通过金属引线连接所述柔性基板背面，其特征在于：所述柔性基板弯曲成型，所述第一芯片连接所述第二芯片，成型所述第一芯片和所述第二芯片的叠加，所述第一芯片和所述第二芯片与所述柔性基板间的空隙处设置有灌封料，本发明同时还提供了一种基于柔性基板的三维多芯片存储***封装结构的制造方法。

Description

基于柔性基板的三维多芯片存储***封装结构及制作方法
技术领域
本发明涉及微电子行业基板封装技术领域，具体涉及一种基于柔性基板的三维多芯片存储***封装结构及其制作方法。
背景技术
随着微电子技术的发展，微电子处理功能的复杂、多样化，使得微电子中基板中的电子元件的集成密度越来越大，势必增加微组装密度和集成度的骤然提高，在有限的空间内成倍提高封装密度，或实现电子设计功能，解决空间、互连受限问题，是当前封装的主流。在成本允许的条件下，采用SIP的封装技术可以提升存储容量，或者拓展产品的内存位宽，适应新一代高位宽、高速、大容量存储芯片的需求。
    各种器件如Flash，CPU等与DRAM相配合后形成的多晶片SIP的封装形式，其单颗器件就独立构成一个***，如MCP，eMCP。这样的***，其发展主要是朝着满足高容量和高效能两个方向，封装形式一般采用FBGA或者PBGA形式。而在有限的空间实现高容量的要求，业界对其内部结构发展出各种堆叠技术，比如，引线键合（Stack by wire bond）、层叠封装（Package-on-package）、线路重布技术（RDL-Wire bond），垂直式连接工艺技术(Vertical interconnection process)，金线-金线内连接技术(Gold to Gold interconnection; GGI)与PIP(Package in  Package)工艺技术。这些技术虽然在空间上提高了封装体的容量或功能，但是对产品的成本和信号方面产生了较大的影响。往往会发现某些产品的封装成本高居不下，而产品的信号完整性也得不到保证，严重影响产品的性能及可靠性。
因此，SIP产品的封装结构设计，对整个产品制造成本、性能、可靠性等各个方面都具有举足轻重的作用，从而决定了产品的市场竞争力。
一般基于多晶片封装存储***，采用的是FBGA的封装形式。 见图1，以eMCP的封装外形结构为例：
其内部结构包括LPDDR2晶片1，闪存晶片2和控制晶片3以及若干颗电阻电容4。将晶片依次堆叠在PCB板子5上，通过引线6和PCB板将信号连接到封装体外面的锡球7上面。
现有技术方案的缺点：
1）.封装加工成本高：
FBGA封装由于采用在PCB单面打线，且堆叠层数较多，线弧的跨度比较大，导致金线用量比较大，且在塑封的时候，线弧之间容易发生短路，增加了加工成本。
2）.信号网络数量多，基板设计困难且成本高，信号完整性不理想 ：
***在信号网络较多的时候，各个网络之间的走线相对较密，传统的FBGA由于在结构上的限制，往往封装基板需要设计4层以上，其成本会大大增加。且由于信号过密，信号之间容易发生串扰，影响信号的完整性，特别对于高速信号。 
另外传统的WB工艺，为提高产品制成能力，需要对基板进行电镀处理，基板上面需要有电镀导线来导通电流进行电镀。而传统FBGA封装，由于结构上的限制，拉出电镀导线比较困难，所以往往需要采用NPL工艺，导致封装基板成本的进一步上升。
发明内容
针对上述问题，本发明提供了一种基于柔性基板的三维多芯片存储***封装结构，有效保证高速信号线的信号完整性，同时大大降低了晶片材料和封装的成本，从而提高了市场竞争能力。本发明同时还提供了一种基于柔性基板的三维多芯片存储***封装结构的制造方法。
其技术方案如下： 
一种基于柔性基板的三维多芯片存储***封装结构，其包括柔性基板，所述柔性基板上连接第一芯片、第二芯片、电容或者电阻，所述第一芯片和所述第二芯片分别通过金属引线连接所述柔性基板背面，其特征在于：所述柔性基板弯曲成型，所述第一芯片连接所述第二芯片，成型所述第一芯片和所述第二芯片的叠加，所述第一芯片和所述第二芯片与所述柔性基板间的空隙处设置有灌封料。
其进一步地：所述第一芯片和所述第二芯片与所述柔性基板通过焊接连接，所述第一芯片通过焊接连接所述第二芯片；所述柔性基板上设置有植球；所述柔性基板上对应所述第一芯片和所述第二芯片分别设置有开槽口，所述金属引线一端分别通过所述开槽口连接所述第一芯片和所述第二芯片上的焊盘（pad），所述金属引线另一端分别连接所述柔性基板。
一种基于柔性基板的三维多芯片存储***封装结构的制造方法，包括以下步骤：
（1）、在柔性基板设计制造中预先制作多个开槽口；
（2）、将电阻电容与柔性基板上面的焊盘互联，以达到信号联通，将多块芯片的焊盘（pad）面对准柔性基板的开槽口，并将芯片与柔性基板进行物理焊接在一起；
（3）、将芯片的焊盘（pad）和柔性基板的背面进行金属引线连接；
（4）、将柔性基板折弯使芯片接触并将芯片背面与相应的芯片连接在一起；
（5）、塑封整个模块，形成芯片环境保护；
其进一步地还包括以下步骤：在柔性基板上植球，形成信号通路；
其更进一步地在于，步骤（2）中，所述芯片与所述柔性基板进行物理焊接在一起；步骤（3）中，所述金属引线与所述芯片的焊盘（pad）和所述柔性基板的背面进行焊接连接；步骤（4）中的所述芯片间通过焊接连接。
     采用本发明是的上述结构中，由于基于柔性基板的制造和折弯技术，在满足器件功能基础上，采用基于传统WBGA工艺的多芯片WBGA的封装结构来实现产品的外观结构，信号线也可进行包地处理，电镀线也可以从开槽口中拉出，在提高产品的运行速度的同时保证了器件的信号完整性要求，同时芯片与基板上的连接点距离近，金线用量少，大大降低了封装成本。
附图说明
图1为现有的多晶片封装结构截面示意图；
图2为本发明基于柔性基板的三维多芯片存储***封装结构示意图；
图3为本发明基于柔性基板的三维多芯片存储***封装结构的制造方法示意图。
具体实施方式
见图2，一种基于柔性基板的三维多芯片存储***封装结构，其包括柔性基板1，柔性基板1上焊接第一芯片2、第二芯片3、电容或者电阻4，柔性基板1上对应第一芯片2和第二芯片3分别设置有开槽口5，第一芯片2和第二芯片3分别通过金属引线6焊接连接柔性基板1背面，金属引线6一端分别通过开槽口5连接第一芯片2和第二芯片3上的焊盘7（pad），金属引线6另一端分别连接柔性基板1，柔性基板弯曲成型第一芯片2和第二芯片3的叠加，第一芯片2和第二芯片3通过焊接连接，第一芯片2和第二芯片3与柔性基板1间的空隙处设置有灌封料8，柔性基板上设置有植球9，形成信号通路。
由于基于柔性基板的制造和折弯技术，在满足器件功能基础上，采用基于传统WBGA工艺的多芯片WBGA的封装结构来实现产品的外观结构，信号线也可进行包地处理，电镀线也可以从开槽口中拉出，在提高产品的运行速度的同时保证了器件的信号完整性要求，同时芯片与基板上的连接点距离近，金线用量少，大大降低了封装成本。
见图3，本发明还提供了一种基于柔性基板的三维多芯片存储***封装结构的制造方法，其特征在于：其包括以下步骤：
（1）、基板结构，在柔性基板1设计制造中预先制作多个开槽口5；
（2）、芯片贴装，完成第一芯片2和第二芯片3以及电容电阻4与柔性基板1之间的连接。将电阻电容4与柔性基板1上面的焊盘互联，以达到信号联通。 对于第一芯片2和第二芯片3，将第一芯片2和第二芯片3的焊盘7（pad）面向下对准柔性基板1上的开槽口，并将第一芯片2和第二芯片3与柔性基板1进行物理焊接在一起。 
       （3）、将第一芯片2、第二芯片3的焊盘7（pad）和柔性基板1的背面进行金属引线6焊接，达到信号联通的目的；
（4）、将柔性基板1折弯并将第一芯片2背面与相应的第二芯片3焊接在一起。
（5）、塑封整个模块，在第一芯片和第二芯片与柔性基板间的空隙处（包括开槽口）设置有灌封料8，进行灌封处理，形成芯片环境保护；
（6）、在柔性基板1上植锡球9，形成信号通路。
本方案基于柔性基板的制造和折弯技术，在满足器件功能基础上，采用基于传统WBGA工艺的多芯片WBGA的封装结构来实现产品的外观结构。 在提高产品的运行速度的同时保证了器件的信号完整性要求。另外，此设计有效的提到了产品的可制造性，降低了晶片材料和封装的成本，从而提高了市场竞争能力。
 其优势如下：
1）、此方案采用3D封装结构，封装后结构尺寸小，封装密度高。
2）、本发明中芯片上面的pad与基板上的连接点距离近，金线用量少，成本低。  
3）、传统FBGA的封装形式，在设计的时候内部走线较为困难，很难保证高速信号线的信号完整性。 而本发明的结构，容易进行内部走线设计，信号线也可进行包地处理，电镀线也可以从开槽口中拉出，极大的提高了整个产品的信号完整性。

Claims (9)

1.一种基于柔性基板的三维多芯片存储***封装结构，其包括柔性基板，所述柔性基板上设置第一芯片、第二芯片、电容或者电阻，所述第一芯片和所述第二芯片分别通过金属引线连接所述柔性基板背面，其特征在于：所述柔性基板弯曲成型，所述第一芯片连接所述第二芯片，成型所述第一芯片和所述第二芯片的叠加，所述第一芯片和所述第二芯片与所述柔性基板间的空隙处设置有灌封料。
2.根据权利要求1所述的一种基于柔性基板的三维多芯片存储***封装结构，其特征在于：所述柔性基板上设置有植球。
3.根据权利要求1所述的一种基于柔性基板的三维多芯片存储***封装结构，其特征在于：所述第一芯片和所述第二芯片与所述柔性基板通过焊接连接，所述第一芯片通过焊接连接所述第二芯片。
4.根据权利要求1-3任何所述的一种基于柔性基板的三维多芯片存储***封装结构，其特征在于：所述柔性基板上对应所述第一芯片和所述第二芯片分别设置有开槽口，所述金属引线一端分别通过所述开槽口连接所述第一芯片和所述第二芯片上的焊盘（pad），所述金属引线另一端分别连接所述柔性基板。
5.一种基于柔性基板的三维多芯片存储***封装结构的制造方法，其特征在于：其包括以下步骤：
（1）、在柔性基板设计制造中预先制作多个开槽口；
（2）、将电阻电容与柔性基板上面的焊盘互联，以达到信号联通，将多块芯片的焊盘（pad）面对准柔性基板的开槽口，并将芯片与柔性基板进行物理连接在一起；
（3）、将芯片的焊盘（pad）和柔性基板的背面进行金属引线连接；
（4）、将柔性基板折弯使芯片接触并将芯片背面与相应的芯片连接在一起；
（5）、塑封整个模块，形成芯片环境保护。
6.根据权利要求5所述的一种基于柔性基板的三维多芯片存储***封装结构的制造方法，其特征在于：步骤（2）中，所述芯片与所述柔性基板进行物理焊接在一起。
7.根据权利要求5所述的一种基于柔性基板的三维多芯片存储***封装结构的制造方法，其特征在于：步骤（3）中，所述金属引线与所述芯片的焊盘（pad）和所述柔性基板的背面进行焊接连接。
8.根据权利要求5所述的一种基于柔性基板的三维多芯片存储***封装结构的制造方法，其特征在于：步骤（4）中的所述芯片间通过焊接连接。
9.根据权利要求5所述的一种基于柔性基板的三维多芯片存储***封装结构的制造方法，其特征在于：其还包括以下步骤：在柔性基板上植球，形成信号通路。
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