CN103543441B - Based on the digital correlator of FPGA nanosecond programmable time delay circuit - Google Patents

Based on the digital correlator of FPGA nanosecond programmable time delay circuit Download PDF

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CN103543441B
CN103543441B CN201310496588.XA CN201310496588A CN103543441B CN 103543441 B CN103543441 B CN 103543441B CN 201310496588 A CN201310496588 A CN 201310496588A CN 103543441 B CN103543441 B CN 103543441B
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delay
signal sequence
target echo
time
echo signal
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CN103543441A (en
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李洪涛
陈恒明
顾陈
朱晓华
马义耕
胡恒
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Nanjing University of Science and Technology
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Nanjing University of Science and Technology
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/41—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00 using analysis of echo signal for target characterisation; Target signature; Target cross-section
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
    • G01S13/02—Systems using reflection of radio waves, e.g. primary radar systems; Analogous systems
    • G01S13/06—Systems determining position data of a target
    • G01S13/08—Systems for measuring distance only

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  • Engineering & Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

The present invention proposes a kind of digital correlator based on FPGA nanosecond programmable time delay circuit, comprise programmable delay module, target echo signal shift register sequential machine, reference signal sequence shift register and related process module, reference signal sequence is stored in described reference signal sequence shift register after the delay process of described programmable delay module, target echo signal is stored in target echo signal shift register sequential machine, described related process module is used for carrying out cross-correlation calculation to the reference signal sequence under target echo signal sequence and different delayed time, export the cross correlation results under different delayed time, described programmable delay module constrains in the inner longitudinally adjacent look-up table unit of FPGA by placement-and-routing's mode, realized by FPGA internal resource.Digital correlator of the present invention can reach the programmable delay of nanosecond to reference signal sequence, the high precision distance realizing aim in short distance detects, and delay time is controlled, delay precision is high.

Description

Based on the digital correlator of FPGA nanosecond programmable time delay circuit
Technical field
The invention belongs to digital correlator technical field, particularly a kind of digital correlator based on FPGA nanosecond programmable time delay circuit.
Background technology
Delay circuit, owing to can carry out time delay to input signal, is therefore widely used in the simulation of clock phase modulation, parallel signal timing alignment and target echo.The phase place of delay circuit adjustable clock, makes clock signal and is sampled signal to meet sampling phase relation, can adjust equally, to calibrate the phase deviation in parallel signal transmitting procedure to parallel signal.In target echo simulator, delay circuit can be applicable to the continuous echo of simulating moving-target.
Current delay circuit is mainly divided into analog delay circuit and digital delay circuit, and analog delay circuit produces time delay owing to utilizing analog device, has that delay time yardstick is large, delay time is fixed and the shortcoming such as delay precision difference, thus limits its application.Digital delay circuit has the advantages such as delay precision is high, the time is able to programme, but can only realize with special chip at present, but Special Purpose Programmable delay chip price general charged costly, and has more pin, brings great inconvenience to circuit design.
Summary of the invention
For solving defect or the deficiency of prior art existence, the present invention aims to provide a kind of digital correlator based on FPGA nanosecond programmable time delay circuit, can reach the programmable delay of nanosecond to reference signal sequence, and the high precision distance realizing aim in short distance detects.
The technical solution realizing the object of the invention is:
A kind of digital correlator, comprise programmable delay module, target echo signal shift register sequential machine, reference sequences shift register and related process module, reference signal sequence is stored in described reference sequences shift register after the delay process of described programmable delay module, target echo signal is stored in target echo signal shift register sequential machine, described related process module is used for carrying out cross-correlation calculation to the reference signal sequence under target echo signal sequence and different delayed time, export the cross correlation results under different delayed time, wherein:
Described programmable delay module comprises a programmable delay unit, described programmable delay unit is in series successively by alternative selector switch and longitudinal delay unit, described longitudinal delay unit is formed by multiple basic delay unit cascade, one of described alternative selector switch select the output terminal of the longitudinal delay unit of input termination and its another select input end to be connected with the input end of longitudinal delay unit, described programmable delay module is constrained in the inner longitudinally adjacent look-up table unit of FPGA by placement-and-routing's mode, is realized by FPGA internal resource;
In the following way cross-correlation calculation is carried out to the reference signal sequence under target echo signal sequence and different delayed time in described related process module and cross correlation results under exporting different delayed time:
A) the target echo signal sequence be stored in described target echo signal shift register sequential machine is designated as x (n), the reference signal sequence be stored in described reference sequences shift register is designated as y (n), x (n) and y (n) signal length are N, wherein n=1,2,3...N, expression is the sequence number of burst sampled point; m 1for reference signal sequence compares the sampling number of target echo signal sequence time delay, calculate the cross correlation function result K of the reference signal sequence after target echo signal sequence and displacement according to formula (1) 1, formula (1) is expressed as follows:
R xy ( m ) = Σ n = 1 N x ( n ) y ( n + m ) - - - ( 1 )
Utilize the R of above-mentioned formulae discovery gained xy(m 1) be cross correlation function result K now 1;
B) by programming to described programmable delay module, realizing the time delay different to described reference signal sequence y (n), making the sampled point of time delay be respectively m 2, m 3, m 4, obtain the cross correlation function result under different delayed time according to described formula (1) double counting, be respectively K 2, K 3, K 4
C) the cross correlation function result K obtained in described step a and b is contrasted 1, K 2, K 3, K 4, wherein the time delay corresponding to maximal value of cross correlation function result is the time delay of reference signal sequence, is also the delay time of target echo signal.
Further, described alternative selector switch constrains in a look-up table unit of described FPGA inside by placement-and-routing's mode, A1, A2 end of this look-up table unit is signal input part, A3 end is signal behavior control end, signal A1 being inputted by the input of control A3 signal that is effective or A2 input is effective, from the O end output signal of look-up table unit.
Further, described basic delay unit constrains in a look-up table unit of described FPGA inside by placement-and-routing's mode, A0, A1, A2 end of this look-up table unit is input as 0, and input signal inputs from A3 end, the minimum delay time t of time delay after this look-up table unit 0, from the O end output signal of look-up table unit.
Further, the minimum delay time of the system of described FPGA is 1ns.
Further, described target echo signal is the discrete digital signal sequence obtained after analog to digital conversion by Radar Analog Echo signal, and described reference signal is the discrete digital signal sequence obtained after analog to digital conversion by radar emission signal.
Further, described related process module is realized by the internal resource of FPGA.
Compared with prior art, its remarkable advantage is the programmable delay that can realize reference signal sequence nanosecond in the present invention, and the high precision distance realizing aim in short distance detects, and has the advantages such as delay time is controlled, delay precision is high, the time is able to programme.Programmable delay circuit in the present invention can be expanded, and the delay circuit after expansion can realize random time delay circuit, can meet various latency requirement, and the high precision distance of realize target detects, and has higher applicability and versatility.
Below in conjunction with accompanying drawing, the present invention is described in further detail.
Accompanying drawing explanation
Fig. 1 is the principle assumption diagram of the digital correlator based on FPGA programmable delay circuit.
Fig. 2 is the principle schematic of programmable delay unit.
Fig. 3 is the principle schematic of the alternative selector switch realized in look-up table unit.
Fig. 4 is the principle schematic of the basic delay unit realized in look-up table unit.
Fig. 5 is the principle schematic of the longitudinal delay unit realized in look-up table unit.
Fig. 6 is the realization flow schematic diagram of relevant treatment.
Fig. 7 is the expansion structure schematic diagram of programmable delay module.
Embodiment
Shown in figure 1-Fig. 6, according to preferred embodiment of the present invention, based on the digital correlator of FPGA programmable delay circuit, comprise programmable delay module, target echo signal shift register sequential machine, reference sequences shift register and related process module.Wherein, reference signal sequence is stored in described reference sequences shift register after the delay process of described programmable delay module, target echo signal is stored in target echo signal shift register sequential machine, described related process module is used for carrying out cross-correlation calculation to the reference signal sequence under target echo signal sequence and different delayed time, exports the cross correlation results under different delayed time.
In the present embodiment, described target echo signal is the discrete digital signal sequence obtained after analog to digital conversion by Radar Analog Echo signal, and described reference signal is the discrete digital signal sequence obtained after analog to digital conversion by radar emission signal.
With reference to figure 2, described programmable delay module comprises a programmable delay unit, shown in composition graphs 3-5, described programmable delay unit is in series successively by alternative selector switch and longitudinal delay unit, described longitudinal delay unit is formed by multiple basic delay unit cascade, one of described alternative selector switch select the output terminal of the longitudinal delay unit of input termination and its another select input end to be connected with the input end of longitudinal delay unit.
Described programmable delay module is constrained in the inner longitudinally adjacent look-up table unit of FPGA by placement-and-routing's mode, is realized, make delay precision controlled by the resource (such as look-up table unit and interconnection resource) of FPGA inside.
As shown in Figure 3, described alternative selector switch constrains in a look-up table unit of described FPGA inside by placement-and-routing's mode, A1, A2 end of this look-up table unit is signal input part, input needs the signal of time delay and the signal not needing time delay respectively, A3 end is signal behavior control end, signal A1 being inputted by the input of control A3 signal that is effective or A2 input is effective, from the O end output signal of look-up table unit.
As shown in Figure 4 and Figure 5, described basic delay unit constrains in a look-up table unit of described FPGA inside by placement-and-routing's mode, A0, A1, A2 end of this look-up table unit is input as 0, and input signal inputs from A3 end, the minimum delay time t of time delay after this look-up table unit 0, from the O end output signal of look-up table unit.
The fpga chip of different model, the minimum delay time t of its system delay 0difference, therefore according to the actual needs of time delay, can select suitable fpga chip, thus realize different time delays.In the present embodiment, preferably, the minimum delay time of the system of FPGA is 1ns.
With reference to the exemplary schematic representation shown in figure 5, longitudinal delay unit is formed by multiple basic delay unit cascade, and signal, from input end input programmable delay unit, exports from output end, often will the minimum delay time t of time delay through a basic delay unit 0, continuing through n basic delay unit will time delay n minimum delay time t 0.With minimum delay time t 0fPGA for 1ns is example, by the selection to n value, can realize the time delay of the multiple needs to signal respectively.
Shown in figure 5, at longitudinal delay unit cascade n basic delay unit, whole longitudinal delay unit can realize corresponding n*t 0delay time, by the selection to n value, the time delay of the multiple needs to signal can be realized respectively, the time delays such as such as 1ns, 2ns, 2ns, 4ns, 10ns, 20ns, 20ns, 40ns, the time that time delay is corresponding.Shown in figure 3, by programming gating alternative selector switch, the selection to signal whether time delay can be realized, correspondingly, select longitudinal delay unit if such as only set by No. 2 alternative selector switchs, other alternative selector switchs then select signal directly to pass through, then signal after input input through programmable delay unit corresponding to No. 2 alternative selector switchs, the time that time delay is corresponding, the number of the basic delay unit namely comprised in this longitudinal delay unit and minimum delay time t 0product.
With reference to shown in figure 1 composition graphs 6, in the following way cross-correlation calculation is carried out to the reference signal sequence under target echo signal sequence and different delayed time in described related process module and cross correlation results under exporting different delayed time:
A) the target echo signal sequence be stored in described target echo signal shift register sequential machine is designated as x (n), the reference signal sequence be stored in described reference sequences shift register is designated as y (n), x (n) and y (n) signal length are N, wherein n=1,2,3...N, expression be the sequence number of burst sampled point; m 1for reference signal sequence compares the sampling number of target echo signal sequence time delay, calculate the cross correlation function result K of the reference signal sequence after target echo signal sequence and displacement according to formula (1) 1, formula (1) is expressed as follows:
R xy ( m 1 ) = Σ n = 1 N x ( n ) y ( n + m ) - - - ( 1 )
This formula shows: count as cross correlation function result of calculation during m equals that target echo signal sequence x (n) is motionless and reference signal sequence y (n) moves to left that m latter two sequence pair of sampled point should be multiplied is added the result of summation again in time delay.
Utilize the R of above-mentioned formulae discovery gained xy(m 1) be cross correlation function result K now 1.
It is worth mentioning that, cross correlation function reflects target echo signal sequence and has made the similarity degree of the reference signal sequence after certain time-delay, when the time delay of reference signal sequence is identical with the time delay of target echo signal, the result exported is maximum, now can judge that the time delay of target echo signal is m.
B) by programming to described programmable delay unit, realizing the time delay different to described reference signal sequence y (n), making the sampled point of time delay be respectively m 2, m 3, m 4, obtain the cross correlation function result under different delayed time according to described formula (1) double counting, be respectively K 2, K 3, K 4and
C) the cross correlation function result K obtained in described step a and b is contrasted 1, K 2, K 3, K 4, wherein the time delay corresponding to maximal value of cross correlation function result is the time delay of reference signal sequence, is also the delay time of target echo signal.
In the present embodiment, preferably, described related process module is realized by the internal resource of FPGA.
As shown in Figure 7, in certain embodiments, also described programmable delay module can be expanded, namely described programmable delay unit is expanded, increase the number of alternative selector switch, and increase longitudinal delay unit in proportion, the time delay of random time can be realized.
Such as, if target echo signal time delay is 58ns, then in time reference signal sequence being realized to 58ns time delay, namely corresponding alternative selector switch in programmable delay module is made in Fig. 1,2 to select longitudinal delay unit by programming, other alternative selector switchs then select signal directly to pass through, in this case, signal is the input of input end from Fig. 2, at corresponding alternative selector switch place by corresponding longitudinal delay unit, export from output after the time delay corresponding time, then can realize the time delay of 58ns.Now, there is maximum correlation peak in the associated processing outcomes that correspondence obtains, and therefore the time delay of target echo signal is 58ns, and the distance of corresponding target is 58ns*3*10 8m/s=17.4m, can reach the accuracy of detection of nanosecond.

Claims (6)

1. a digital correlator, it is characterized in that, comprise programmable delay module, target echo signal shift register sequential machine, reference sequences shift register and related process module, reference signal sequence is stored in described reference sequences shift register after the delay process of described programmable delay module, target echo signal is stored in target echo signal shift register sequential machine, described related process module is used for carrying out cross-correlation calculation to the reference signal sequence under target echo signal sequence and different delayed time, export the cross correlation results under different delayed time, wherein:
Described programmable delay module comprises a programmable delay unit, described programmable delay unit is in series successively by alternative selector switch and longitudinal delay unit, described longitudinal delay unit is formed by multiple basic delay unit cascade, one of described alternative selector switch select the output terminal of the longitudinal delay unit of input termination and its another select input end to be connected with the input end of longitudinal delay unit, described programmable delay module is constrained in the inner longitudinally adjacent look-up table unit of FPGA by placement-and-routing's mode, is realized by FPGA internal resource;
In the following way cross-correlation calculation is carried out to the reference signal sequence under target echo signal sequence and different delayed time in described related process module and cross correlation results under exporting different delayed time:
A) the target echo signal sequence be stored in described target echo signal shift register sequential machine is designated as x (n), the reference signal sequence be stored in described reference sequences shift register is designated as y (n), x (n) and y (n) signal length are N, wherein n=1,2,3...N, expression is the sequence number of burst sampled point; m 1for reference signal sequence compares the sampling number of target echo signal sequence time delay, calculate the cross correlation function result K of the reference signal sequence after target echo signal sequence and displacement according to formula (1) 1, formula (1) is expressed as follows:
R xy ( m ) = Σ n = 1 N x ( n ) y ( n + m ) - - - ( 1 )
Utilize the R of above-mentioned formulae discovery gained xy(m 1) be cross correlation function result K now 1;
B) by programming to described programmable delay module, realizing the time delay different to described reference signal sequence y (n), making the sampled point of time delay be respectively m 2, m 3, m 4, obtain the cross correlation function result under different delayed time according to described formula (1) double counting, be respectively K 2, K 3, K 4
C) the cross correlation function result K obtained in described step a and b is contrasted 1, K 2, K 3, K 4, wherein the time delay corresponding to maximal value of cross correlation function result is the time delay of reference signal sequence, is also the delay time of target echo signal.
2. digital correlator according to claim 1, it is characterized in that, described alternative selector switch constrains in a look-up table unit of described FPGA inside by placement-and-routing's mode, A1, A2 end of this look-up table unit is signal input part, A3 end is signal behavior control end, signal A1 being inputted by the input of control A3 signal that is effective or A2 input is effective, from the O end output signal of look-up table unit.
3. digital correlator according to claim 1, it is characterized in that, described basic delay unit constrains in a look-up table unit of described FPGA inside by placement-and-routing's mode, A0, A1, A2 end of this look-up table unit is input as 0, input signal inputs from A3 end, the minimum delay time t of time delay after this look-up table unit 0, from the O end output signal of look-up table unit.
4. digital correlator according to claim 1, is characterized in that, the minimum delay time of system of described FPGA is 1ns.
5. digital correlator according to claim 1, it is characterized in that, described target echo signal is the discrete digital signal sequence obtained after analog to digital conversion by Radar Analog Echo signal, and described reference signal is the discrete digital signal sequence obtained after analog to digital conversion by radar emission signal.
6. digital correlator according to claim 1, is characterized in that, described related process module is realized by the internal resource of FPGA.
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