CN101621288B - Circuit for converting PWM output mode into PFM output mode - Google Patents
Circuit for converting PWM output mode into PFM output mode Download PDFInfo
- Publication number
- CN101621288B CN101621288B CN2009101832216A CN200910183221A CN101621288B CN 101621288 B CN101621288 B CN 101621288B CN 2009101832216 A CN2009101832216 A CN 2009101832216A CN 200910183221 A CN200910183221 A CN 200910183221A CN 101621288 B CN101621288 B CN 101621288B
- Authority
- CN
- China
- Prior art keywords
- pwm
- output mode
- circuit
- comparator
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000008676 import Effects 0.000 claims 1
- 230000000295 complement effect Effects 0.000 abstract 1
- 238000006243 chemical reaction Methods 0.000 description 16
- 230000000630 rising effect Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000000306 component Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 241000220317 Rosa Species 0.000 description 1
- 210000001367 artery Anatomy 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000001208 nuclear magnetic resonance pulse sequence Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 210000003462 vein Anatomy 0.000 description 1
Images
Landscapes
- Dc-Dc Converters (AREA)
Abstract
The invention discloses a circuit for converting a PWM output mode into a PFM output mode and belongs to a power supply control circuit. The circuit consists of a PWM comparator, an oscillator circuit, a variable frequency clock pulse generating circuit consisting of a comparator and a clock pulse generating circuit and a logic gate circuit. An input voltage signal is crossed and compared with a sawtooth wave to generate a PWM pulse, and meanwhile, the input voltage signal and the clock pulse generating circuit generate a clock pulse at the tail end of the PWM pulse through the comparator; the clock pulse resets an oscillator and participates in the logic operation of the logic gate circuit, thereby outputting a pulse with a certain frequency, which has the duty ratio tending to 1 after a dead zone is removed or the duty ratio tending to 0.5 after a pair of complementary dead zones is removed; and the frequency of the pulse and the input voltage change proportionally, thereby the PWM output mode is converted into the PFM output mode.
Description
Technical field
The present invention relates to frequency conversion class control circuit system, especially frequency conversion class power control circuit system.
Background technology
Application of frequency conversion technique more and more widely, especially in power control system, that converter technique has is energy-conservation, long service life, interference is low, antijamming capability is strong and advantage such as environmental protection.In frequency-converting power supply, frequency conversion class control chip is a core component, it is the heart of control circuit system, it is directly connected to the dynamic property and the steady-state behaviour of control circuit, influences the service behaviour of circuit, but frequency conversion class control chip costs an arm and a leg, also do not popularize and use, exist problems such as some instabilities, The whole control Circuits System cost height, the cost performance of system is low.And PWM (Pulse Width Modulation) class control chip comes the ON time of control switch pipe to finish voltage stabilizing function by using pulse duration.Its price is relatively cheap many, that has passed through people uses and tests improvement for a long time, the integrated technique function admirable, and obtain easily, if realize the circuit function of PFM (Pulse Frequency Modulation) frequency conversion class output mode by PWM class control chip and necessary external circuit thereof, so just can reduce the cost of frequency conversion Qatput mode circuit, thereby reduce the cost of frequency conversion control circuit system greatly, improve the cost performance of system.
Summary of the invention
Goal of the invention: the circuit that the objective of the invention is PWM class output mode is changed into frequency conversion PFM class output mode, reduce the cost of frequency conversion PFM Qatput mode circuit, thereby reduce the cost of frequency conversion PFM class control circuit system, improve the cost performance of The whole control Circuits System.
Technical scheme: for solving the problems of the technologies described above, the present invention adopts following technical scheme:
Comprise:
One oscillator is used for producing sawtooth waveforms;
One PWM comparator makes input voltage signal and sawtooth waveforms intersect knot relatively, produces pwm pulse;
The variable frequency clock pulse generation circuit that one comparator and clock pulse generating circuit are formed produces the variable frequency clock pulse, and this pulse resets to the oscillator that can be reset, and supplies with output logic gate circuit participation logical operation;
One logic gates cooperates with clock Clock pulsion phase, pwm pulse is carried out duty ratio trends towards 1 variable-frequency pulse after the dead band is removed in one of output after the logical operation;
Input voltage signal u wherein
iImport the in-phase input end of PWM comparator, the inverting input of comparator respectively, be connected with the input of oscillator, the first input end of logic gates respectively behind the output serial connection clock pulse generating circuit of comparator, the output of oscillator is connected with the in-phase input end of comparator, the inverting input of PWM comparator respectively, the output of PWM comparator links to each other with second input of logic gates, and the output of logic gates is connected with driven switching tube of outside.
PWM output mode of the present invention is converted in the circuit of PFM output mode clock pulse generating circuit by a not gate, an electric capacity and in sequential series the obtaining of Schmidt trigger.
PWM output mode of the present invention is converted into that oscillator can be reset in the circuit of PFM output mode.Reducible oscillator, be after oscillator is accepted clock pulse, the sawtooth waveforms rising edge overturns immediately and is trailing edge, and drop to the sawtooth waveforms minimum point immediately, or to guarantee in clock cycle, to drop to the sawtooth waveforms minimum point at least, after clock pulse withdrawed from, sawtooth waveforms rose along fixed slope automatically, generated next new sawtooth waveforms.
PWM output mode of the present invention is converted in the circuit of PFM output mode, when the semaphore request through logic gates output have remove the dead band after duty ratio when trending towards 0.5 two-way output, can in logic gates, be equipped with phase splitter again and realize.
Beneficial effect:
PWM class output mode of the present invention changes into the circuit of frequency conversion PFM class output mode, its main feature is, input signal hands over knot relatively through PWM comparator and sawtooth waveforms, produce pwm pulse, terminal edge in the PWM output pulse that produces generates a clock pulse signal, with this clock pulse signal oscillator is resetted, and this clock pulse signal is given logic gates simultaneously, after logical operation, convert the PWM output mode to the PFM output mode, this circuit is improved the performance of frequency conversion PFM control circuit system, cost reduces greatly, and cost performance is more excellent.
Description of drawings
Fig. 1 is converted into the electrical schematic diagram of PFM output mode for PWM output mode of the present invention;
Fig. 2 is converted into the structure composition diagram of clock generation circuit in the circuit of PFM output mode for PWM output mode of the present invention.
Fig. 3 is converted into the circuit exemplary operation waveform of PFM output mode for PWM output mode of the present invention.
Embodiment
Below in conjunction with accompanying drawing technical scheme of the present invention is further illustrated:
As depicted in figs. 1 and 2, PWM output mode of the present invention is converted into the electrical schematic diagram of PFM output mode.The circuit of a PWM output mode, its chief component are that PWM comparator 110, the oscillator 120 that produces sawtooth waveforms, logic gates 140 etc. are partly formed.The circuit that this PWM output mode is converted into the PFM output mode comprises a PWM comparator 110, an oscillator 120, comparator 131 and the clock pulse generating circuit 132 common variable frequency clock pulse generation circuits of forming 130, this clock pulse generating circuit 132 is by a not gate 133, an electric capacity 134 and Schmidt trigger 135 in sequential series forming, and a logic gates 140.Input voltage signal u
iConnect the in-phase input end of PWM comparator 110, the output of PWM comparator 110 links to each other with logic gates 140, the end of oppisite phase of PWM comparator 110 links to each other with the oscillator 120 that can produce sawtooth waveforms, the characteristics of this oscillator are and can be reset, promptly when receiving clock Clock pulse signal, the rising edge of sawtooth waveforms overturns immediately and is trailing edge, makes the level of rising edge drop to the minimum point of the trailing edge of sawtooth waveforms in clock Clock pulse, and promptly oscillator is reset.This oscillator links to each other the reverse input end of this comparator and input voltage signal u with the in-phase input end of another comparator 131 simultaneously
iLink to each other, the output of comparator 131 links to each other with clock pulse generating circuit 132, and the output signal of clock pulse generating circuit is the clock pulse signal with frequency conversion character, i.e. clock Clock pulse signal.This output terminal of clock pulse links to each other with logic gates 140 first input ends with oscillator 120 inputs, and logic gates 140 is carried out logical operation and converted the PWM output mode to the PFM output mode, and the gate output links to each other with the driven switching tube in outside.
Referring to Fig. 1, Fig. 2 and Fig. 3, output waveform wherein shown in Figure 3 is the example explanation with two-way variable-frequency pulse output signal.The circuit working principle that this PWM output mode is converted into the PFM output mode is illustrated: the circuit of PWM output mode, its chief component is PWM comparator 110, the oscillator 120 that produces sawtooth waveforms, logic gates 140 and fixing clock pulse signal, and it mainly is according to input voltage signal u
iIntersect knot with sawtooth waveforms and relatively form pulse signal, promptly form the PWM ripple of the fixed frequency of certain duty ratio with certain width.And being converted into the circuit of PFM output mode, this PWM output mode just is being based on that such principle design forms, as input voltage signal u
iThe in-phase input end of input PWM comparator 110, this input voltage signal produces the crossing knot of sawtooth waveforms relatively with the oscillator of input PWM comparator 110 reverse input ends, at PWM output output PWM wave impulse, meanwhile input voltage signal u
iBe input to the reverse input end of another comparator 131, with the input comparator 131 crossing knot comparison of oscillator generation sawtooth waveforms of input in the same way, the comparative voltage signal of comparator 131 outputs output is given clock pulse generating circuit 132, these clock pulse generating circuit 132 these clock pulse generating circuits 132 are by a not gate 133, an electric capacity 134 and Schmidt trigger 135 in sequential series forming, as shown in Figure 2, after the signal of the output of comparator 131 is received not gate 133 negates in the clock pulse generating circuit, output is connected on the electric capacity 134, produce a burst pulse, this burst pulse is through after the shaping of Schmidt trigger, form the burst pulse of a standard rectangular, with this burst pulse as clock pulse signal, the major function of its realization is to generate a burst pulse in the terminal edge of comparator 131 output pulses, be used as clock pulse signal, on this clock Clock pulse sequence corresponding to: behind PWM comparator 110 output pulse terminal edges, generate this clock arteries and veins Clock towards signal, referring to shown in Figure 3.Oscillator 120 and logic gates 140 are meanwhile delivered in this clock clock pulse.After delivering to oscillator 120, oscillator is reset immediately, promptly the rising edge of the sawtooth waveforms that rises along fixed slope overturns immediately and is trailing edge, and the minimum point that the trailing edge of sawtooth waveforms drops in clock clock pulse, after can dropping to minimum point at the trailing edge of sawtooth waveforms, oscillator carries out the generation of next sawtooth waveforms automatically, be that oscillator is after the trailing edge of sawtooth waveforms drops to minimum point, can rise along certain slope automatically, form new sawtooth waveforms rising edge, above-mentioned just such main cause that forms frequency conversion.The clock Clock pulse of being delivered to logic gates 140 simultaneously participates in the logical operation of logic gates, finish the output of variable-frequency pulse, Shu Chu pulse signal is that a duty ratio trends towards 1 variable-frequency pulse signal output after removing the dead band like this, be equipped with phase splitter in case of necessity in logic gates, the duty ratio that can produce the two-way complementation trends towards 0.5 two-way Output1 and the output of Output2 variable-frequency pulse signal.
Different input voltage signal u
iCan be by the clock Clock pulse of comparator 131 and the clock pulse generating circuit 132 common variable frequency clock pulse generation circuits of forming 130 generation different frequencies, the resetting and participate in the computing of logic gates of this clock Clock pulsed oscillator, thereby produce duty ratio and trend towards 1 or 0.5 frequency conversion output pulse, and different input voltage signal u
iCorresponding to different frequency output clock Clock pulses, input voltage signal u
iHave continuity, the variation of respective frequencies also has continuity, and input voltage signal u
iHas corresponding relation with the frequency of output pulse.
In sum, the circuit that this PWM output mode is converted into the PFM output mode has realized that different input voltages produces the output pulse of different frequency, has realized being converted to the PFM output mode from the PWM output mode.
More than PWM output mode of the present invention is converted into the PFM output mode circuit be described in detail, this paper has used specific case principle of the present invention and execution mode has been set forth, the explanation of embodiment just helps to understand method of the present invention and core concept thereof, simultaneously, for one of ordinary skill in the art, according to thought of the present invention, when embodiment and application, all can change to some extent, so equal variation still belongs to the scope that the present invention is contained.
Claims (3)
1.PWM output mode is converted into the circuit of PFM output mode, it is characterized in that: comprise
One oscillator (120) is used for producing sawtooth waveforms;
One PWM comparator (110) makes input voltage signal and sawtooth waveforms intersect knot relatively, produces pwm pulse;
The variable frequency clock pulse generation circuit (130) that one comparator (131) and clock pulse generating circuit (132) are formed produces the variable frequency clock pulse, and this pulse resets to the oscillator that can be reset, and outputs to logic gates participation logical operation;
One logic gates (140) cooperates with the variable frequency clock pulsion phase, pwm pulse is carried out duty ratio trends towards 1 variable-frequency pulse after the dead band is removed in one of output after the logical operation;
Wherein input voltage signal ui imports the in-phase input end of PWM comparator (110) respectively, the inverting input of comparator (131), behind the output termination clock pulse generating circuit (132) of comparator (131) respectively with the input of oscillator (120), the first input end of logic gates (140) connects, the output of oscillator (120) respectively with the in-phase input end of comparator (131), the inverting input of PWM comparator (110) connects, the output of PWM comparator (110) links to each other with second input of logic gates (140), and the output of logic gates (140) is connected with driven external switch pipe.
2. PWM output mode according to claim 1 is converted into the circuit of PFM output mode, it is characterized in that: described clock pulse generating circuit (132) is by a not gate (133), an electric capacity (134) and in sequential series the obtaining of a Schmidt trigger (135).
3. be converted into the circuit of PFM output mode according to the described PWM output mode of claim 1, it is characterized in that: when the semaphore request through logic gates (140) output be a pair of complementation remove that duty ratio trends towards 0.5 two-way output behind the dead band time, in logic gates, be equipped with phase splitter again and realize.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101832216A CN101621288B (en) | 2009-07-29 | 2009-07-29 | Circuit for converting PWM output mode into PFM output mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101832216A CN101621288B (en) | 2009-07-29 | 2009-07-29 | Circuit for converting PWM output mode into PFM output mode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101621288A CN101621288A (en) | 2010-01-06 |
| CN101621288B true CN101621288B (en) | 2011-08-31 |
Family
ID=41514375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101832216A Expired - Fee Related CN101621288B (en) | 2009-07-29 | 2009-07-29 | Circuit for converting PWM output mode into PFM output mode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101621288B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101969303B (en) * | 2010-06-30 | 2013-04-17 | 艾默生网络能源***北美公司 | Resonance circuit output characteristic control method |
| KR101353254B1 (en) * | 2012-06-28 | 2014-01-17 | 삼성전기주식회사 | Circuit, apparatus and method for direct-driving led |
| KR101330513B1 (en) * | 2012-08-29 | 2013-11-18 | 어보브반도체 주식회사 | High resolution pulse width modulated signal generation circuit |
| CN107306126A (en) * | 2016-04-25 | 2017-10-31 | 中兴通讯股份有限公司 | PWM generation circuit |
| CN111257628B (en) * | 2020-03-05 | 2022-05-06 | 成都飞机工业（集团）有限责任公司 | Anti-interference method for converting alternating current signal into pulse signal |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030090244A1 (en) * | 2001-11-05 | 2003-05-15 | Krishna Shenai | Multislice DC-DC converter |
| CN1909351A (en) * | 2006-06-30 | 2007-02-07 | 艾默生网络能源有限公司 | Feedback circuit adapted for series resonance dc-dc converter |
| CN101272136A (en) * | 2007-03-22 | 2008-09-24 | 台湾类比科技股份有限公司 | Switching circuit and its method for pulse frequency modulation and pulse width modulation |
-
2009
- 2009-07-29 CN CN2009101832216A patent/CN101621288B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030090244A1 (en) * | 2001-11-05 | 2003-05-15 | Krishna Shenai | Multislice DC-DC converter |
| CN1909351A (en) * | 2006-06-30 | 2007-02-07 | 艾默生网络能源有限公司 | Feedback circuit adapted for series resonance dc-dc converter |
| CN101272136A (en) * | 2007-03-22 | 2008-09-24 | 台湾类比科技股份有限公司 | Switching circuit and its method for pulse frequency modulation and pulse width modulation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101621288A (en) | 2010-01-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101621288B (en) | Circuit for converting PWM output mode into PFM output mode | |
| CN101304247B (en) | Multi-period random digit pulse-width modulation circuit and method | |
| CN107979359B (en) | Clock synchronization circuit for maintaining fixed pulse | |
| US6798248B2 (en) | Non-overlapping clock generation | |
| CN106257835B (en) | A kind of 25% duty cycle clock signal generation circuit | |
| CN102946185A (en) | Control circuit for improving switching power supply output voltage transient response | |
| CN103166605B (en) | A kind of heterogeneous non-overlapping clock circuit | |
| CN102025265A (en) | Frequency jittering circuit | |
| CN101399504B (en) | Full digital soft starting circuit and electric supply system applying the circuit | |
| CN104242629A (en) | Low-voltage low-power-consumption PWM comparator with ramp compensation function | |
| CN103138560A (en) | Frequency jitter system | |
| CN103178814A (en) | Function signal generating device and function signal generating method | |
| CN102055466A (en) | Multi-phase signal generation device | |
| CN103956996A (en) | High-resolution digital pulse width modulator based on double-frequency and multi-phase clock | |
| CN210780703U (en) | Sawtooth wave generating circuit and buck-boost converter | |
| CN206041784U (en) | Trigger pulse modulation circuit of thyristor | |
| CN1862935B (en) | Output power compensating method and switching controller | |
| CN208015698U (en) | It is a kind of to realize the clock switch circuit steadily switched | |
| CN110708044A (en) | Sawtooth wave generating circuit and buck-boost converter | |
| CN210780704U (en) | Sawtooth wave generating circuit and buck-boost converter | |
| CN104578756B (en) | A kind of DC DC pierce circuits of dual output | |
| CN113302827B (en) | Multiphase signal control circuit and method | |
| CN202957806U (en) | FPGA-based DDS signal generator | |
| CN103368533B (en) | The dynamically synchronized control circuit of satellite sailboard power array simulator | |
| CN203377848U (en) | Dynamic synchronous control circuit of satellite panel power source array simulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110831 Termination date: 20130729 |