CN202475380U - Multi-order M sequence generating circuit - Google Patents
Multi-order M sequence generating circuit Download PDFInfo
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- CN202475380U CN202475380U CN2012200558584U CN201220055858U CN202475380U CN 202475380 U CN202475380 U CN 202475380U CN 2012200558584 U CN2012200558584 U CN 2012200558584U CN 201220055858 U CN201220055858 U CN 201220055858U CN 202475380 U CN202475380 U CN 202475380U
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Abstract
The utility model relates to a multi-order M sequence generating circuit. The circuit comprises a trigger circuit and an exclusive OR gate correspondingly connected with the trigger circuit, wherein the exclusive OR gate is correspondingly connected with the trigger circuit by at least one microstrip line; and after the exclusive OR gate delays for the needed time via the microstrip lines, the trigger circuit is used for outputting the needed M sequences. The circuit has the following advantages: the exclusive OR gate is connected with the trigger circuit by at least a microstrip line and delays for the needed time via the microstrip lines and the trigger circuit can output the needed M sequences; the frequency is high and the GHz level clock frequency can be easily realized; the circuit has low cost, needs few components, realizes multi-order M sequences by only using three D triggers and one exclusive OR gate, has high reliability and good stability and can be used in the fields such as communications and radar; and the high-frequency multi-order M sequence generating circuit built by utilizing the microstrip lines is beneficial to solving the problems of low memorized frequency and difficult debugging of the M sequence generating circuits and can be widely applied to various high-frequency signal generating circuits.
Description
Technical field
The utility model relates to a kind of sequence generation circuit, and especially a kind of multistage M sequence generation circuit belongs to the technical field of sequence generation circuit.
Background technology
As shown in Figure 1: as to be the structural representation of existing 9 rank M sequence generation circuit.Wherein, the M sequence generation circuit on existing 9 rank is realized the generation of M sequence by 9 d type flip flops and 1 XOR gate.The Q end of trigger a8 links to each other with the D end of trigger a7; The Q end of trigger a7 links to each other with the D end of trigger a6, and the Q end of trigger a6 links to each other with the D end of trigger Q5, and the Q end of trigger a5 links to each other with the D end of trigger a4; The Q end of trigger a4 links to each other with the D end of trigger a3; The Q end of trigger a3 links to each other with the D end of trigger a2, and the Q end of trigger a2 links to each other with the D end of trigger a1, and the Q end of trigger a1 links to each other with the D end of trigger a0; Trigger a0 links to each other with XOR gate respectively with the Q end of trigger a5, and the output of XOR gate links to each other with the D end of trigger a8.
When the clock rising edge triggered, trigger was given the next stage d type flip flop with the state transfer of Q port; XOR gate carries out the XOR processing to the input state of trigger a5 and trigger a0 simultaneously, and transmits back the D end of trigger a8; Trigger a0 is as output, all after dates through 511, the state of whole generation circuit and initial state consistency, the i.e. one-period of 9 rank M sequences.
But this M sequence generation circuit generally only is applicable to low-frequency channel, is not suitable for the higher circuit of clock frequency.Even because select the operating frequency of trigger high again, when upset, also have certain time-delay, when the M sequence reached 9 rank, the delay accumulation of 9 d type flip flops can make the whole M sequence all get muddled.
The production method of another kind of M sequence is to produce with high-end FPGA, and it can produce the M sequence of the highest 6GHz, but the required device cost of this method is higher.
Summary of the invention
The purpose of the utility model is to overcome the deficiency that exists in the prior art, and a kind of multistage M sequence generation circuit is provided, and its frequency is high, and cost is low, and stability and reliability are high, and adaptability is good.
According to the technical scheme that the utility model provides, said multistage M sequence generation circuit comprises circuits for triggering and the corresponding XOR gate that links to each other with said circuits for triggering; Said XOR gate links to each other through at least one microstrip line is corresponding with circuits for triggering, after XOR gate postpones the required time through microstrip line, by the required M sequence of circuits for triggering output.
Said circuits for triggering comprise first d type flip flop and second d type flip flop, and the Q end of said first d type flip flop links to each other with the D end of second d type flip flop; The Q end of first d type flip flop links to each other with the input of XOR gate respectively with the Q end of second d type flip flop, and the output of XOR gate links to each other with the D end of first d type flip flop through microstrip line, the required M sequence of Q end output of second d type flip flop.
The Q end of said second d type flip flop links to each other with the input of XOR gate through microstrip line.Said circuits for triggering also comprise 3d flip-flop, and the Q end of said first d type flip flop links to each other with the D end of the 3rd trigger, and the Q end of 3d flip-flop links to each other with the D end of second d type flip flop.
The advantage of the utility model: link to each other through a microstrip line at least between XOR gate and circuits for triggering, through microstrip line postpone the required time can, circuits for triggering can be exported required M sequence; Frequency is high, can easily realize the clock frequency of GHz level; Cost is low, and required device is few, has only used three d type flip flops and an XOR gate to realize multistage M sequence in the utility model, and reliability is high, good stability, can be used for communication, field of radar; The multistage M sequence of the high frequency generation circuit that utilizes microstrip line to make up has solved that M sequence generation circuit frequency memory frequency is low, the problem of debug difficulties, and can be widely used in the various high-frequency signal generation circuit.
Description of drawings
Fig. 1 is the structure principle chart of existing 9 rank M sequence generation circuit.
Fig. 2 is the structural representation of the utility model.
Embodiment
Below in conjunction with concrete accompanying drawing and embodiment the utility model is described further.
In order to make M sequence generation circuit can reliablely and stablely export required M sequence; The utility model comprises circuits for triggering and the corresponding XOR gate that links to each other with said circuits for triggering; Said XOR gate links to each other with circuits for triggering through at least one microstrip line; After the required time of microstrip line delay, the M sequence that circuits for triggering output is required.After XOR gate passes through microstrip line and circuits for triggering is connected; Utilize microstrip line to postpone accurately characteristic and avoided the uncertain time-delay of high-speed door circuit in the traditional circuit; Utilize the controlled characteristics of the little concubine's duration of delay of microstrip line; Improve the operating frequency of M sequence, can reduce the quantity of gate circuit in the circuits for triggering simultaneously.
As shown in Figure 2: as to be the concrete implementation of the utility model.Circuits for triggering comprise first d type flip flop, second d type flip flop and 3d flip-flop, comprise first d type flip flop and second d type flip flop in the circuits for triggering at least; Wherein, first d type flip flop is a8, and second d type flip flop is a0, and 3d flip-flop is a1.The Q end of the first d type flip flop a8 links to each other with the D end of 3d flip-flop, and the Q end of 3d flip-flop links to each other with the D end of second d type flip flop, the required M sequence of Q end output of second d type flip flop; The Q end of first d type flip flop all links to each other with the input of XOR gate with the Q end of second d type flip flop, and the output of XOR gate links to each other with the D end of first d type flip flop through microstrip line, and the Q end of second d type flip flop also can link to each other with the input of XOR gate through microstrip line.When through after corresponding microstrip line is set, XOR gate can only reach required time of delay through the microstrip line that links to each other with output, makes circuits for triggering export the corresponding M sequence; XOR gate also can only reach required time of delay through the microstrip line that links to each other with input, makes circuits for triggering export the corresponding M sequence, and in like manner, the input of XOR gate can link to each other with corresponding microstrip line with output.In multistage M sequence generation circuit, also can comprise a plurality of XOR gates, when having a plurality of XOR gate, be serially connected between XOR gate more.
As shown in Figure 2: during work, select the quantity of corresponding d type flip flop in the circuits for triggering as required, and select the microstrip line of respective length according to required M sequence and circuits for triggering, XOR gate links to each other with circuits for triggering through microstrip line.Circuits for triggering link to each other with corresponding pulse signal, through behind the circuits for triggering, and circuits for triggering output corresponding M sequence.When needs obtain the M sequence of upper frequency, the model that d type flip flop in the circuits for triggering and XOR gate all should be selected corresponding high speed.Along with the raising of chip frequency, can also be applicable to the M sequence of higher frequency, and can be used in M sequence and other similar pseudo random sequence of other exponent numbers.
At least link to each other through a microstrip line between the utility model XOR gate and circuits for triggering, through microstrip line postpone the required time can, circuits for triggering can be exported required M sequence; Frequency is high, can easily realize the clock frequency of GHz level; Cost is low, and required device is few, has only used three d type flip flops and an XOR gate to realize multistage M sequence in the utility model, and reliability is high, good stability, can be used for communication, field of radar; The multistage M sequence of the high frequency generation circuit that utilizes microstrip line to make up has solved that M sequence generation circuit frequency memory frequency is low, the problem of debug difficulties, and can be widely used in the various high-frequency signal generation circuit.
Claims (4)
1. a multistage M sequence generation circuit comprises circuits for triggering and the corresponding XOR gate that links to each other with said circuits for triggering; It is characterized in that: said XOR gate links to each other through at least one microstrip line is corresponding with circuits for triggering, after XOR gate postpones the required time through microstrip line, by the required M sequence of circuits for triggering output.
2. multistage M sequence generation circuit according to claim 1, it is characterized in that: said circuits for triggering comprise first d type flip flop and second d type flip flop, the Q end of said first d type flip flop links to each other with the D end of second d type flip flop; The Q end of first d type flip flop links to each other with the input of XOR gate respectively with the Q end of second d type flip flop, and the output of XOR gate links to each other with the D end of first d type flip flop through microstrip line, the required M sequence of Q end output of second d type flip flop.
3. multistage M sequence generation circuit according to claim 2 is characterized in that: the Q end of said second d type flip flop links to each other with the input of XOR gate through microstrip line.
4. multistage M sequence generation circuit according to claim 2; It is characterized in that: said circuits for triggering also comprise 3d flip-flop; The Q end of said first d type flip flop links to each other with the D end of the 3rd trigger, and the Q end of 3d flip-flop links to each other with the D end of second d type flip flop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012200558584U CN202475380U (en) | 2012-02-20 | 2012-02-20 | Multi-order M sequence generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012200558584U CN202475380U (en) | 2012-02-20 | 2012-02-20 | Multi-order M sequence generating circuit |
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| Publication Number | Publication Date |
|---|---|
| CN202475380U true CN202475380U (en) | 2012-10-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012200558584U Expired - Lifetime CN202475380U (en) | 2012-02-20 | 2012-02-20 | Multi-order M sequence generating circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102571037A (en) * | 2012-02-20 | 2012-07-11 | 北方通用电子集团有限公司 | Multi-order M sequence generation circuit |
| CN107888168A (en) * | 2016-09-29 | 2018-04-06 | 中芯国际集成电路制造(上海)有限公司 | Trigger |
-
2012
- 2012-02-20 CN CN2012200558584U patent/CN202475380U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102571037A (en) * | 2012-02-20 | 2012-07-11 | 北方通用电子集团有限公司 | Multi-order M sequence generation circuit |
| CN107888168A (en) * | 2016-09-29 | 2018-04-06 | 中芯国际集成电路制造(上海)有限公司 | Trigger |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20121003 |
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| CX01 | Expiry of patent term |