CN201341120Y - Controllable delay line - Google Patents
Controllable delay line Download PDFInfo
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- CN201341120Y CN201341120Y CNU2008202028976U CN200820202897U CN201341120Y CN 201341120 Y CN201341120 Y CN 201341120Y CN U2008202028976 U CNU2008202028976 U CN U2008202028976U CN 200820202897 U CN200820202897 U CN 200820202897U CN 201341120 Y CN201341120 Y CN 201341120Y
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Abstract
The utility model relates to the technical field of delay line, in particular to a controllable delay line, which comprises a delay module used for delaying signal inputting and a tap selection module used for changing the delay time according to the difference of inputted control signals; the input end of the tap selection module is connected with the output end of the delay module; the output end of the tap selection module is used for outputting a delay signal; the tap selection module is arranged and the utility model can change the delay time according to the difference of the inputted control signals; therefore, the utility model relates to a controllable delay line; further more, a measuring module used for measuring the real time delay time of the delay module is arranged between the delay module and the tap selection module and the tap selection module can adjust the tap position of the delay signal according to the real time delay time inputted by the measuring module, thereby outputting a precise delay signal.
Description
Technical field:
The utility model relates to the delay line technique field, relates in particular to a kind of controllable delay line.
Background technology:
In integrated circuit (IC) design, often need do the delay of certain hour to signal, and delay line has obtained in integrated circuit using widely as a kind of important delay components and parts.Existing delay line generally is to be composed in series by a plurality of delay cells, and fix the time of delay of each delay cell, therefore, fix the time of delay of this delay line, can not differently according to the control signal of input change time of delay, do not have controllability.In addition, because during the work of the components and parts in the integrated circuit, can be subjected to the influence of factors such as operating voltage, temperature, different operational environments, the real time delay time of components and parts is also inequality, so, the delay line of existing structure, at different operational environments, its real time delay time is also inequality, certain error can be produced, promptly accurate inhibit signal can not be exported.
The utility model content:
The purpose of this utility model is exactly to provide a kind of controllable delay line at the deficiency of prior art existence, and it can change time of delay according to the difference of the control signal of importing.
To achieve these goals, the technical solution adopted in the utility model is:
It comprises the Postponement module that is used for delay input signal, the tap selection module that is used for changing according to the difference of the control signal of importing time of delay, tap selects the input of module to be connected with the output of Postponement module, and tap selects the output of module to be used for the output delay signal.
Wherein, described Postponement module and tap select to be provided with between the module measurement module of the real time delay time that is used to measure Postponement module, the input of measurement module is connected with the output of Postponement module, and the output of measurement module selects the input of module to be connected with tap.
Wherein, described Postponement module is to be composed in series by plural number level delay cell, and the output of every grade of delay cell selects the input of module to be connected with input, the tap of next stage delay cell respectively.
Wherein, described tap select module comprise decoder or door, a plurality of d type flip flop corresponding, a plurality of and d type flip flop with delay cell corresponding with door, the D end of each d type flip flop connects with the output of corresponding delay cell, all the CP of d type flip flop end links together, the output of each d type flip flop is connected with first input end door with corresponding, all be connected with second input of door with the output of decoder, with the output of door all with or the input of door be connected.
Wherein, described measurement module is connected to form by two dividers.
The utility model beneficial effect is:
A kind of controllable delay line that the utility model provides comprises the Postponement module that is used for delay input signal, the tap selection module that is used for changing according to the difference of the control signal of importing time of delay, tap selects the input of module to be connected with the output of Postponement module, tap selects the output of module to be used for the output delay signal, select module owing to be provided with tap, the utility model can change time of delay according to the difference of the control signal of importing, so the utility model is a kind of delay line with controllability.Further, described Postponement module and tap select to be provided with between the module measurement module of the real time delay time that is used to measure Postponement module, tap selects module to adjust the tap position of output delay signal according to the real time delay time of measurement module input, thereby exports accurate inhibit signal.
Description of drawings:
Fig. 1 is a block diagram of the present utility model;
Fig. 2 is circuit theory diagrams of the present utility model;
Fig. 3 is the oscillogram of the tap output of each d type flip flop;
Fig. 4 is that coding of the present utility model is realized circuit;
Fig. 5 is an application examples of the present utility model.
Embodiment:
Below in conjunction with accompanying drawing the utility model is further described, see shown in Figure 1, the utility model comprises the Postponement module 1 that is used for delay input signal, be used for changing the tap selection module 2 of time of delay according to the difference of the control signal of importing, tap selects the input of module 2 to be connected with the output of Postponement module 1, tap selects the output of module 2 to be used for the output delay signal, select module 2 owing to be provided with tap, the utility model can change time of delay according to the difference of the control signal of importing, so the utility model is a kind of delay line with controllability.
The Postponement module 1 of present embodiment and tap select to be provided with between the module 2 measurement module 3 of the real time delay time that is used to measure Postponement module 1, the input of measurement module 3 is connected with the output of Postponement module 1, the output of measurement module 3 selects the input of module 2 to be connected with tap, tap selects module 2 to adjust the tap position of output delay signal according to the real time delay time of measurement module 3 inputs, thereby exports accurate inhibit signal.
For can the control lag time, the method control lag output that the utility model adopts tap to select, tap selects to be equivalent to a code translator, select module 2 by tap, the control signal of input is converted to corresponding tap numbers, then with the output of the tap chosen as final delay output.
In order to obtain selected tap numbers, the utility model has adopted the time that will need to postpone to remove time of delay of each grade delay cell 11, just can obtain the way of the tap position of output signal.Suppose and to represent with symbol t that to the time of delay of input signal represent with symbol t0 the time of delay of one-level delay cell 11, tap numbers is represented with symbol k, can get
Formula 1:
Owing to delay cell 11 can change along with the change of operational environment, in order to obtain accurate time of delay (just accurate tap numbers), must know the time of delay of each moment delay cell 11, so must measure the real time delay time of each delay cell 11 in real time.
The input signal of present embodiment is the clock signal of a given frequency, at first measure needed delay cell 11 progression of a clock cycle of delay input signal, remove needed delay cell 11 progression by the clock cycle of input signal again, just can obtain the real time delay time of each grade delay cell 11.Suppose to represent with symbol T the clock cycle of input signal, symbol N represents input signal is postponed needed delay cell 11 progression of T, uses symbol t the time of delay of one-level delay cell 11
0Expression can get formula 2:
It is the tap position that needed delay cell 11 progression of a clock cycle of delay input signal equal a clock cycle of delay input signal.Though the real time delay time of each grade delay cell 11 that is calculated by formula 2 is a mean value, in identical by the technology of each grade delay cell 11, so this mean value and actual value differ very little.
See Fig. 2, the Postponement module 1 of present embodiment is to be composed in series by plural number level delay cell 11, the output of the delay cell 11 of the first order respectively with the input of partial delay cell 11, tap selects the input of module 2 to connect, the rest may be inferred, delay cell 11 until afterbody, and the output of the delay cell 11 of afterbody only connects the input that module 2 is selected in tap, be every grade of delay cell 11 output respectively with the input of next stage delay cell 11, tap selects the input of module 2 to connect, described tap selects module 2 to comprise decoder 23, or door 24, the d type flip flop 21 that a plurality of and delay cell 11 are corresponding, a plurality of and d type flip flop 21 corresponding with door 22, the D end of each d type flip flop 21 connects with the output of corresponding delay cell 11, all the CP of d type flip flop 21 end links together, the output of each d type flip flop 21 is connected with the corresponding first input end with door 22, all be connected with second input of door 22 with the output of decoder 23, with the output of door 22 all with or the input of door 24 be connected, or the output of door 24 then is used for the output delay signal, wherein, described measurement module 3 is connected to form by two dividers, the input of first divider 31 connects the period T of input respectively, tap numbers temp, the output of first divider 31 is connected with the input of second divider 32, the input of second divider 32 is input control signal also, and the output of second divider 32 then is connected with the input of decoder 23.Its operation principle is: the output delay signal of delay cell 11 is through being output as tap output behind the d type flip flop 21, the output of each tap output and decoder 23 through with door 22 with after, if decoder 23 has been selected some taps, then with door 22 signal output is arranged just at selected tap place, then, will with the output of door 22 through or door 24 after, the inhibit signal that can obtain exporting just.Wherein, what first divider 31 (realization of formula 2) in the measurement module 3 was exported is the real time delay time of each grade delay cell 11, (realization of formula 1) finally exports accurate tap numbers through second divider 32 again, sends in the decoder 23, selects a tap output by decoder 23.
See Fig. 3, it supposes to have ten secondary tap D0～D11 for the waveform of each d type flip flop 21 taps (being output) output.As seen from Figure 3, the waveform of tap D10 output is the output waveform that the waveform (being input signal) of D0 output has postponed a clock cycle, identify as dotted line among Fig. 3, rising edge place at the waveform of D0 output, the waveform of D9 output is a high level, the waveform of D11 output is a low level, promptly at the rising edge place of input signal, with respect to the delayed time previous tap of the tap after a clock cycle of input signal (input of first order delay cell) is high level, and a back tap then is low level.As can be seen from the above technical solutions, asking time of delay with the tap output valve is exactly a cataloged procedure.The thinking of this coding is, till searching first order d type flip flop 21 forward from d type flip flop 21 output of afterbody, last sequence number that satisfies condition to the d type flip flop 21 of " previous stage output high level; back one-level output low level " is exactly the tap numbers that has postponed a clock cycle, hence one can see that, can calculate the real time delay time of each grade delay cell according to said method.As Fig. 4, for the coding of this cataloged procedure is realized circuit.Suppose to have 8 taps, and only need wide 3 number as tap numbers, temp represents tap numbers with symbol, symbol D represents tap, if the output of the 3rd tap is the output that has postponed a clock cycle, then at the rising edge of input signal, first, second tap is output as high level, and the 4th tap is output as low level.Be among Fig. 4 with door 41,43 output low levels, with door 42 output high level, make or door 44 output high level place temp[0]=1; Equally, with door 53 output low levels, with door 52 output high level, through or door 54 after, place temp[1]=1, and with door 61,62,63 output low level all, through or 64 after, temp[3]=0, temp=011 in such cases.Measurement module 3 with temp import into tap select in the module 2 31 outputs of first divider, 31, the first dividers be the real time delay time of each grade delay cell 11.Because time of delay of each grade all is through measuring in real time, therefore, entire circuit of the present utility model can well reduce the influence of factors such as operating voltage, temperature.
See Fig. 5, the utility model is applied to the application examples of digital controlled oscillator 7, the utility model is in the next stage of digital controlled oscillator 7, digital controlled oscillator 7 exports running clock to the input of Postponement module 1 of the present utility model, the running clock skew is exported to the input that module 2 is selected in tap of the present utility model, then, the utility model is according to the running clock skew (being control signal) of digital controlled oscillator 7 inputs, running clock to digital controlled oscillator 7 outputs carries out certain delay, and by output of the present utility model (being the output that module 2 is selected in tap) the output clock of output through accurately postponing.
Certainly, the above only is preferred embodiment of the present utility model, so all equivalences of doing according to the described structure of the utility model patent claim, feature and principle change or modify, is included in the utility model patent claim.
Claims (5)
1, a kind of controllable delay line, it comprises the Postponement module that is used for delay input signal, it is characterized in that: it also comprises the tap selection module that is used for changing according to the difference of the control signal of importing time of delay, tap selects the input of module to be connected with the output of Postponement module, and tap selects the output of module to be used for the output delay signal.
2, a kind of controllable delay line according to claim 1, it is characterized in that: described Postponement module and tap select to be provided with between the module measurement module of the real time delay time that is used to measure Postponement module, the input of measurement module is connected with the output of Postponement module, and the output of measurement module selects the input of module to be connected with tap.
3, a kind of controllable delay line according to claim 1, it is characterized in that: described Postponement module is to be composed in series by plural number level delay cell, and the output of every grade of delay cell selects the input of module to be connected with input, the tap of next stage delay cell respectively.
4, a kind of controllable delay line according to claim 3, it is characterized in that: described tap select module comprise decoder or door, a plurality of d type flip flop corresponding, a plurality of and d type flip flop with delay cell corresponding with door, the D end of each d type flip flop connects with the output of corresponding delay cell, all the CP of d type flip flop end links together, the output of each d type flip flop is connected with first input end door with corresponding, all be connected with second input of door with the output of decoder, with the output of door all with or the input of door be connected.
5, a kind of controllable delay line according to claim 2, it is characterized in that: described measurement module is connected to form by two dividers.
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| Application Number | Priority Date | Filing Date | Title |
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| CNU2008202028976U CN201341120Y (en) | 2008-11-04 | 2008-11-04 | Controllable delay line |
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| CNU2008202028976U CN201341120Y (en) | 2008-11-04 | 2008-11-04 | Controllable delay line |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103457596A (en) * | 2012-06-05 | 2013-12-18 | 国民技术股份有限公司 | Time delay compensating circuit and method |
| CN108134754A (en) * | 2018-01-09 | 2018-06-08 | 西安科技大学 | A kind of intermediate frequency differential demodulator of gigabit continuous variable rate |
| CN111865300A (en) * | 2020-07-08 | 2020-10-30 | 福州大学 | Programmable digital control delay line applied to double-loop delay phase-locked loop |
-
2008
- 2008-11-04 CN CNU2008202028976U patent/CN201341120Y/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103457596A (en) * | 2012-06-05 | 2013-12-18 | 国民技术股份有限公司 | Time delay compensating circuit and method |
| CN108134754A (en) * | 2018-01-09 | 2018-06-08 | 西安科技大学 | A kind of intermediate frequency differential demodulator of gigabit continuous variable rate |
| CN108134754B (en) * | 2018-01-09 | 2019-02-01 | 西安科技大学 | A kind of intermediate frequency differential demodulator of gigabit continuous variable rate |
| CN111865300A (en) * | 2020-07-08 | 2020-10-30 | 福州大学 | Programmable digital control delay line applied to double-loop delay phase-locked loop |
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Granted publication date: 20091104 Termination date: 20111104 |