CN104935304A - Broadband repetition arbitrary waveform generator and generation method - Google Patents
Broadband repetition arbitrary waveform generator and generation method Download PDFInfo
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- CN104935304A CN104935304A CN201510293034.9A CN201510293034A CN104935304A CN 104935304 A CN104935304 A CN 104935304A CN 201510293034 A CN201510293034 A CN 201510293034A CN 104935304 A CN104935304 A CN 104935304A
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Abstract
The invention provides a broadband repetition arbitrary waveform generator and a generation method, and belongs to the field of digital signal processing. The generator comprises a single-chip microcomputer, an FPGA, a Flash, a DAC, and a numerical control gain amplifier. The generator can generate arbitrary waveform from 100Mhz to 500Mhz in a time period corresponding to the capacity of a storage unit, and a repetition time interval can be adjusted. Waveform data can be generated by an upper computer, and also can be generated by a data generation program in the upper computer, so as to shorten starting-up time. Waveform is generated in a mode of first calculation and second playing, so as to improve the system performance and enlarge signal bandwidth.
Description
Technical field
The invention belongs to digital processing field, be specifically related to a kind of broadband and repeat AWG (Arbitrary Waveform Generator) and method for generation.
Background technology
Along with society constantly develops, in today that science and technology is maked rapid progress, the demand of AWG (Arbitrary Waveform Generator) on civil and military is increasing.No matter civilian aspect, be scientific research or engineering project, all must carry out emulation testing in the project concluding stage.Particularly in the communications field, this will relate to the acquisition of echo signal, but some signal be not easy to get, and such as airborne ADS-B signal is for most important ADS-B receiver test, but laboratory is difficult to get real signal; Military aspect, need the interference (such as in radar countermeasures) some equipment being carried out to corresponding band, and jammer is exactly a kind of AWG (Arbitrary Waveform Generator) in fact.Based on above situation, visible AWG (Arbitrary Waveform Generator), no matter in civilian or military domain, all has a wide range of applications.
The AWG (Arbitrary Waveform Generator) volume sold in the market is larger, expensive (as Agilent, R & S, the equipment of NI) and existing low cost AWG (Arbitrary Waveform Generator) due to the defect of structure and design, daily scientific research demand can not be met.Such as, be mentioned to a kind of AWG (Arbitrary Waveform Generator) in patent CN201020207981.4, be characterized in that the Wave data produced is produced by host computer in real time and communicated by usb bus, digital to analog converter clock is subject to the restriction of usb bus speed thus systematic function is restricted; Disclose a kind of easy waveform generator in patent CN201420590569.3, this waveform generator can not produce the waveform wanted arbitrarily, makes function be subject to great restriction; The system configuration be mentioned in paper " development of AWG (Arbitrary Waveform Generator) " is subject to the restriction of host computer and equipment interface speed equally, makes to generate signal bandwidth very limited.There is following defect in existing AWG (Arbitrary Waveform Generator): in order to pursue real-time, and system velocity is subject to the impact of host computer interface, and systematic function is declined, and generation signal bandwidth and power limited can not adjust, and can not produce intermediate frequency, high-frequency signal fast.
Summary of the invention
In order to overcome the defect of existing simple and easy AWG (Arbitrary Waveform Generator), what AWG (Arbitrary Waveform Generator) can be tried one's best meets engineering and scientific research requirement, the invention provides a kind of structure simple, powerful AWG (Arbitrary Waveform Generator).This AWG (Arbitrary Waveform Generator) can with the clock work of 1.25Ghz, operating frequency is not subject to the impact of host computer computational speed and interface, generate any intermediate-freuqncy signal of 100M to 500M, and by signal repeat playing within the time that memory span size is corresponding, can adjust arbitrarily the recurrence interval time.
The technical solution adopted for the present invention to solve the technical problems is:
AWG (Arbitrary Waveform Generator) is repeated in a kind of broadband, its structure as shown in Figure 1, comprise single-chip microprocessor MCU, the on-site programmable gate array FPGA be connected with single-chip microcomputer, the flash memory Flash be connected with field programmable gate array, the digital to analog converter DAC be connected with field programmable gate array, the Data control gain amplifier that is connected with digital to analog converter output, waveform signal is exported by the output of affiliated Data control gain amplifier; Wherein said single-chip microcomputer is connected with host computer, receive the instruction of host computer, described single-chip microcomputer comprises control command unit, data command unit and triggering command unit, described control command unit is for controlling described Data control gain amplifier, described data command unit is used for the data command that single-chip microcomputer obtains to be transmitted to as in Wave data storage and described flash memory after described FPGA, and described triggering command unit is used for control single chip computer inside and generates data to FPGA; Described FPGA comprises data module, control module and parameter module, the data command that described data module sends for reading and store single-chip microcomputer, described control module sends data for controlling described data module to described digital to analog converter, and described parameter module is used for the time of delay that setting signal repeats.
Described single-chip microcomputer and host computer turn serial communication by USB.
Further, described AWG (Arbitrary Waveform Generator) also comprises the first band pass filter and the second band pass filter, the two ends of described first band pass filter connect the output of described digital to analog converter and the input of Data control gain amplifier respectively, and the two ends of described second band pass filter are connected to the output of described Data control gain amplifier and the output of described AWG (Arbitrary Waveform Generator).
The mode that the real-time calculating that the present invention abandons restriction system operating frequency forwards in real time, adopt and calculate the complete working method forwarded again, thus realize high speed operation, detailed process is:
The data module of FPGA stores the data that single-chip microcomputer provides successively from the initial address of Flash, until single-chip microcomputer provides complete by instruction notification FPGA control module data; Once data store complete, FPGA control module control data module to start from Flash initial position successively sense data to DAC, thus produce the random waveform of data description, when reading the last memory address of data, FPGA continues to send out zero data until parameter module time of delay of specifying, and then again from the initial address sense data successively of Flash, goes round and begins again, realize waveform to repeat to broadcast, interval can adjust arbitrarily.Based on above-mentioned design, get final product elevator system work clock, produce the intermediate-freuqncy signal of wide bandwidth.
Data account form: two kinds of modes are provided, one is by host computer calculated data, and by serial ports, data are passed to single-chip microcomputer, the data of single-chip microcomputer are stored in Flash by FPGA; Two is a few instructions by host computer, triggers internal data generator in single-chip microcomputer and generates data, and be stored in Flash by FPGA.
The present invention also provides a kind of and repeats random waveform method for generation, specifically comprises the following steps:
The instruction of step 1. host computer comprises following three kinds: control command, data command and triggering command; After the instruction receiving host computer, the type according to instruction carries out corresponding operating;
If step 2. receives data command, then the head identification division of received instruction is deleted, the remaining strings of commands is sent to FPGA;
If receive triggering command, then trigger the Data Generation Program of single-chip microcomputer inside, start to produce according to command request the Wave data existed in code, pass to FPGA by parallel interface;
If the control command of receiving, then control Data control gain amplifier according to order parameter;
By judging that the head of data determines that this information is data message or parameter (pulse length, interval time) information after step 3.FPGA receives data;
If be judged as data message according to data flow head, then data are stored in successively in outside memory;
If when being judged as parameter information, then signalization parameter (time signal period, recurrence interval time);
If the control command of being judged as, data are then stopped to store, transfer data reading pattern to, now FPGA sense data successively from the initial address of memory, until when reading last address of parameter information requirement only, and export after data are transmitted to DAC and Data control gain amplifier successively and namely obtain required waveform; After carrying out time delay according to parameter configuration, repeat to read data from the initial address of Flash, the repetitive pattern at fixed time interval can be obtained.
The invention has the beneficial effects as follows:
Structure of the present invention is simple, and repeatedly can produce any intermediate frequency waveform of 100M to 500M, wave form output power adjustable, repetition interval is adjustable, and the present invention utilizes single-chip microcomputer internal trigger mode to calculate the feature that Wave data has quick turn-on work.
Accompanying drawing explanation
Fig. 1 is system construction drawing of the present invention.
The data flow of the AWG (Arbitrary Waveform Generator) that Fig. 2 the present embodiment provides.
The generation point frequency modulation pulse temporal sectional drawing of the AWG (Arbitrary Waveform Generator) that Fig. 3 provides for embodiment; The interval 1us that equipment produces, pulse duration 2us, carrier frequency 300Mhz repeat a modulating pulse frequently.
The generation linear FM signal frequency spectrum of the AWG (Arbitrary Waveform Generator) that Fig. 4 provides for embodiment; The interval 1us that equipment produces, the repetition chirp of pulse duration 2us, carrier frequency 300Mhz to 305Mhz.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described further.
Embodiment
The AWG (Arbitrary Waveform Generator) structure that the present embodiment provides as shown in Figure 1.In FIG, host computer turns serial ports and single chip communication by USB, and single-chip microcomputer Main Function is the instruction of response host computer, there are 3 kinds of instruction modes: 1, data command; 2, control command; 3, triggering command.The remaining strings of commands, for removing the instruction identification head of single-chip microcomputer, is sent to FPGA by parallel interface by the response receiving data command; Receive the response of control command for controlling external number control gain device according to order parameter; The response receiving triggering command is the Data Generation Program triggering single-chip microcomputer inside, starts to produce according to command request the Wave data existed in code, passes to FPGA, improves transmission speed with this, shorten the available machine time by parallel interface.Method for computing data in trigger code is: if DAC clock is f, then single-chip microcomputer is from the t0=0 moment, signal function F (x) to be output is carried out to the sampling of Δ t=1/f, sampled value is converted to the corresponding figure place of DAC and carries out data transmission.
In turn store data in Flash from the initial address of Flash from by data module after FPGA receives data, until control module notification data module data produces complete, data module data read successively in Flash from the initial position of Flash of FPGA produce intermediate-freuqncy signal to DAC, the recurrence interval time of signal is provided by parameter module, and signal is by exporting after filter and amplification.
In Fig. 2, host computer turns serial ports and single chip communication by USB.Single-chip microcomputer inside comprises three instruction response units.Command unit 1 is for receiving data command unit, and its processing method is forwarded to FPGA for removing head by parallel interface; Command unit 2, can according to the information amendment external number control gain regulation output signal power of host computer for receiving control command unit; Command unit 3, for receiving triggering command unit, triggers respective signal model according to command request and starts calculated data.By judging that the head of data determines that this bit stream is data message or parameter (pulse length, interval time) information after FPGA receives single-chip data.FPGA inside comprises three processing modules: one is data module, and when being judged as data message according to data flow head, 1. data are stored in outside flash according to path by this module work successively; Two is parameter modules, when being judged as parameter information, and signalization parameter (time signal period, recurrence interval time); Three is control modules, when being judged as control command, stop storing, transfer readout mode to, now FPGA from the initial address of Flash according to path 2. sense data successively, simultaneously according to path 3. by data retransmission to DAC, until read last address of parameter request, after carrying out time delay according to parameter configuration, read from the initial address of Flash again, go round and begin again.
Fig. 3 is the generation interval 1us of the present embodiment, pulse duration 2us, the signal of carrier frequency 300Mhz.Fig. 4 is the generation interval 1us of the present embodiment, pulse duration 2us, the chirp pulse signal frequency spectrum of carrier frequency from 300Mhz to 305Mhz.
Claims (4)
1. AWG (Arbitrary Waveform Generator) is repeated in a broadband, comprise single-chip microcomputer, the field programmable gate array be connected with single-chip microcomputer, the flash memory be connected with field programmable gate array, the digital to analog converter be connected with field programmable gate array, the Data control gain amplifier that is connected with digital to analog converter output, waveform signal is exported by the output of affiliated Data control gain amplifier, wherein said single-chip microcomputer is connected with host computer, receives the instruction of host computer;
It is characterized in that, described single-chip microcomputer comprises control command unit, data command unit and triggering command unit, described control command unit is for controlling described Data control gain amplifier, described data command unit is used for the data command that single-chip microcomputer obtains to be transmitted to as in Wave data storage and described flash memory after described field programmable gate array, and described triggering command unit is used for control single chip computer inside and generates data to field programmable gate array; Described field programmable gate array comprises data module, control module and parameter module, the data command that described data module sends for reading and store single-chip microcomputer, described control module sends data for controlling described data module to described digital to analog converter, and described parameter module is used for the time of delay that setting signal repeats.
2. AWG (Arbitrary Waveform Generator) is repeated in broadband according to claim 1, and it is characterized in that, described single-chip microcomputer and host computer turn serial communication by USB.
3. AWG (Arbitrary Waveform Generator) is repeated in broadband according to claim 1, it is characterized in that, also comprise the first band pass filter and the second band pass filter, the two ends of described first band pass filter connect the output of described digital to analog converter and the input of Data control gain amplifier respectively, and the two ends of described second band pass filter are connected to the output of described Data control gain amplifier and the output of described AWG (Arbitrary Waveform Generator).
4. repeat a random waveform method for generation, specifically comprise the following steps:
The instruction of step 1. host computer comprises following three kinds: control command, data command and triggering command; After the instruction receiving host computer, the type according to instruction carries out corresponding operating;
If step 2. receives data command, then the head identification division of received instruction is deleted, the remaining strings of commands is sent to FPGA; If receive triggering command, then trigger the Data Generation Program of single-chip microcomputer inside, start to produce according to command request the Wave data existed in code, and pass to FPGA by parallel interface; If the control command of receiving, then control Data control gain amplifier according to order parameter;
By judging that the head of data determines the particular content of this information after step 3.FPGA receives data;
If be judged as data message according to data flow head, then data are stored in successively in outside memory;
If when being judged as parameter information, then signalization parameter;
If the control command of being judged as, data are then stopped to store, transfer data reading pattern to, now FPGA sense data successively from the initial address of memory, until when reading last address of parameter information requirement only, and export after data are transmitted to DAC and Data control gain amplifier successively and namely obtain required waveform; After carrying out time delay according to parameter configuration, repeat to read data from the initial address of Flash, the repetitive pattern at fixed time interval can be obtained.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104682943A (en) * | 2013-11-30 | 2015-06-03 | 中国科学院沈阳自动化研究所 | Device and method for generating wave signals |
| CN106444962A (en) * | 2016-11-30 | 2017-02-22 | 桂林电子科技大学 | Drawing random waveform signal generator |
| CN106855733A (en) * | 2016-12-21 | 2017-06-16 | 中国航空工业集团公司雷华电子技术研究所 | A kind of digital receiver waveform table method for parameter configuration |
| CN107368144A (en) * | 2017-07-18 | 2017-11-21 | 中国科学技术大学 | Arbitrary waveform generator and waveform playing method |
| CN108020821A (en) * | 2017-12-27 | 2018-05-11 | 成都锐芯盛通电子科技有限公司 | A kind of phased array radar antenna beam control circuit detecting system and its implementation |
| CN109240961A (en) * | 2018-11-30 | 2019-01-18 | 济南浪潮高新科技投资发展有限公司 | A kind of devices, systems, and methods for quantum calculation observing and controlling |
| CN109814656A (en) * | 2018-12-28 | 2019-05-28 | 中电科仪器仪表有限公司 | A kind of signal generating apparatus and method for arbitrary waveform generator |
| CN114050810A (en) * | 2022-01-13 | 2022-02-15 | 武汉通力路达科技有限公司 | PWM waveform generation method, device, embedded equipment and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950000243B1 (en) * | 1989-08-14 | 1995-01-12 | 대우전자 주식회사 | Wave-form generator used for one chip computer |
| CN101162398A (en) * | 2006-10-12 | 2008-04-16 | 东莞理工学院 | Arbitrarily signal generating device |
| CN102522967A (en) * | 2011-12-20 | 2012-06-27 | 陕西海泰电子有限责任公司 | B-type LXI (LAN eXtensions for Instrument) arbitrary waveform generator |
-
2015
- 2015-06-02 CN CN201510293034.9A patent/CN104935304B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950000243B1 (en) * | 1989-08-14 | 1995-01-12 | 대우전자 주식회사 | Wave-form generator used for one chip computer |
| CN101162398A (en) * | 2006-10-12 | 2008-04-16 | 东莞理工学院 | Arbitrarily signal generating device |
| CN102522967A (en) * | 2011-12-20 | 2012-06-27 | 陕西海泰电子有限责任公司 | B-type LXI (LAN eXtensions for Instrument) arbitrary waveform generator |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104682943A (en) * | 2013-11-30 | 2015-06-03 | 中国科学院沈阳自动化研究所 | Device and method for generating wave signals |
| CN106444962A (en) * | 2016-11-30 | 2017-02-22 | 桂林电子科技大学 | Drawing random waveform signal generator |
| CN106855733A (en) * | 2016-12-21 | 2017-06-16 | 中国航空工业集团公司雷华电子技术研究所 | A kind of digital receiver waveform table method for parameter configuration |
| CN107368144A (en) * | 2017-07-18 | 2017-11-21 | 中国科学技术大学 | Arbitrary waveform generator and waveform playing method |
| CN107368144B (en) * | 2017-07-18 | 2020-02-07 | 中国科学技术大学 | Arbitrary waveform generator and waveform playing method |
| CN108020821A (en) * | 2017-12-27 | 2018-05-11 | 成都锐芯盛通电子科技有限公司 | A kind of phased array radar antenna beam control circuit detecting system and its implementation |
| CN108020821B (en) * | 2017-12-27 | 2021-06-08 | 成都锐芯盛通电子科技有限公司 | Phased array radar antenna beam control circuit detection system and implementation method thereof |
| CN109240961A (en) * | 2018-11-30 | 2019-01-18 | 济南浪潮高新科技投资发展有限公司 | A kind of devices, systems, and methods for quantum calculation observing and controlling |
| CN109814656A (en) * | 2018-12-28 | 2019-05-28 | 中电科仪器仪表有限公司 | A kind of signal generating apparatus and method for arbitrary waveform generator |
| CN109814656B (en) * | 2018-12-28 | 2021-01-22 | 中电科仪器仪表有限公司 | Signal generation device and method for arbitrary waveform generator |
| CN114050810A (en) * | 2022-01-13 | 2022-02-15 | 武汉通力路达科技有限公司 | PWM waveform generation method, device, embedded equipment and storage medium |
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