CN206946471U - A kind of shared read-write SDRAM of multichannel circuit arrangement - Google Patents
A kind of shared read-write SDRAM of multichannel circuit arrangement Download PDFInfo
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- CN206946471U CN206946471U CN201720867956.0U CN201720867956U CN206946471U CN 206946471 U CN206946471 U CN 206946471U CN 201720867956 U CN201720867956 U CN 201720867956U CN 206946471 U CN206946471 U CN 206946471U
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Abstract
The utility model is a kind of shared read-write SDRAM of multichannel circuit arrangement, including SDRAM memory and read-write arbitration modules, read-write arbitration modules are connected to transmitting element and receiving unit, transmitting element includes multiple sendaisle cache modules and multichannel sends arbitration modules, and receiving unit includes multichannel and receives selecting module and multiple receiving channel cache modules；Each cache module connects a sendaisle in multiple sendaisle cache modules, and multichannel sends arbitration modules and is connected to read and write arbitration modules；Each cache module connects a receiving channel in multiple receiving channel cache modules, and multichannel receives selecting module and is connected to read and write arbitration modules；Sendaisle cache module is identical with receiving channel cache module quantity.The shared read-write SDRAM of this multichannel circuit arrangement, it is a kind of application for being directed to multi-channel data and sharing SDRAM memory spaces, by increasing L2 cache and multistage arbitration circuit, timesharing piecemeal controls, and reaches the purpose of lifting SDRAM storage service efficiency.
Description
Technical field
The utility model belongs to signal acquisition storage and processing technology field, and in particular to a kind of shared read-write of multichannel
SDRAM circuit arrangement.
Background technology
The processing of digital display circuits all at present, it is required for mounting the caching devices of Large Copacity, particularly with asynchronous
The docking of system, for rate matched and stream control is carried out, it is essential to carry out data buffer storage using SDRAM memory banks.
SDRAM（Synchronous dynamic random access memory, referred to as
SDRAM）It is the DRAM for having a sync cap（Dynamic random access memory, referred to as
DRAM）.Usual DRAM（DRAM）There is an asynchronous interface, so it response control can be inputted at any time
Change.And SDRAM has a sync cap, a clock signal can be waited before response control input, thus can and be counted
The system bus of calculation machine is synchronous.Clock is used to drive a finite state machine, and the instruction to entrance carries out pile line operation.This
So that SDRAM can have a more complicated behaviour compared with without the asynchronous DRAM (asynchronous DRAM) of sync cap
Operation mode.
, generally will be by controlling time slot to carry out timesharing to read-write because read-write physical port is multiplexing for SDRAM
Operation, and normally due to SDRAM memory spaces are big, caching single-pass data utilization ratio is relatively low.
Utility model content
The purpose of this utility model is that solve existing SDRAM because memory space is big, caches single-pass data utilization ratio
The problem of relatively low.
Therefore, the utility model provides a kind of shared read-write SDRAM of multichannel circuit arrangement, including SDRAM storages
Device and the read-write arbitration modules being connected with SDRAM memory, described read-write arbitration modules be also respectively connected with transmitting element and
Receiving unit, described transmitting element include multiple sendaisle cache modules and are connected with multiple sendaisle cache modules
Multichannel sends arbitration modules, and described receiving unit includes multichannel and receives selecting module and receive selecting module with multichannel
Multiple receiving channel cache modules of connection；
Described multiple sendaisle cache modules connect multiple sendaisles respectively, and multichannel sends arbitration modules connection
Read-write arbitration modules；
Described multiple receiving channel cache modules connect multiple receiving channels respectively, and multichannel receives selecting module connection
Read-write arbitration modules；
Described sendaisle cache module is identical with receiving channel cache module quantity.
Memory space inside described SDRAM memory is divided into multiple separate storage regions, separate storage region
Quantity is no less than sendaisle or the quantity of receiving channel.
Described sendaisle cache module and receiving channel cache module is buffer；Described multichannel sends secondary
Cut out module, multichannel receives selecting module and read-write arbitration modules are PLC.
Described sendaisle cache module and receiving channel cache module is 20,20 sendaisle cache modules
Connecting multi-channel sends arbitration modules respectively, and 20 receiving channel cache module difference connecting multi-channels receive selecting module, more
Passage sends arbitration modules and multichannel receives selecting module and connects read-write arbitration modules respectively.
The beneficial effects of the utility model：The shared read-write SDRAM of this multichannel provided by the utility model circuit dress
Put, be a kind of application for being directed to multi-channel data and sharing SDRAM memory spaces, by increasing L2 cache and multistage arbitration electricity
Road, timesharing piecemeal control, and reach the purpose of lifting SDRAM storage service efficiency.
Brief description of the drawings
The utility model is described in further details below with reference to accompanying drawing.
Fig. 1 is theory structure schematic diagram of the present utility model.
Description of reference numerals：1st, SDRAM memory；2nd, arbitration modules are read and write；3rd, sendaisle cache module；4th, multichannel
Send arbitration modules；5th, multichannel receives selecting module；6th, receiving channel cache module.
Embodiment
The utility model provides a kind of shared read-write SDRAM of multichannel circuit arrangement, as shown in figure 1, being deposited including SDRAM
Reservoir 1 and the read-write arbitration modules 2 being connected with SDRAM memory 1, described read-write arbitration modules 2, which are also respectively connected with, to be sent
Unit and receiving unit, described transmitting element include multiple sendaisle cache modules 3 and cache mould with multiple sendaisles
The multichannel that block 3 connects sends arbitration modules 4, and described receiving unit includes multichannel and receives selecting module 5 and and multichannel
Receive multiple receiving channel cache modules 6 that selecting module 5 connects；
Multiple sendaisle cache modules 3 connect multiple sendaisles respectively, and multichannel sends arbitration modules 4 and is connected to read
Write arbitration modules 2；Multiple receiving channel cache modules 6 connect multiple receiving channels respectively, and multichannel receives selecting module 5 and connected
Read-write arbitration modules 2；
Described sendaisle cache module 3 is identical with the quantity of receiving channel cache module 6.
The utility model adds transmitting element and receiving unit to SDRAM memory 1 and read-write arbitration modules 2 both sides,
Level cache and arbitration is respectively added to select in data receipt unit and transmitting element, in order to lift multichannel and share SDRAM
The throughput of memory 1, room for promotion utilization rate, while each channel data will not be lost.
Further, the memory space inside SDRAM memory 1 is divided into multiple separate storage regions, separate storage area
The quantity in domain is no less than sendaisle or the quantity of receiving channel.Multi-channel data is stored, according to channel data amount by SDRAM
The space in portion carries out decile, all puts fixed separate storage region per read-write data all the way, is independent of each other.
Sendaisle cache module 3 and receiving channel cache module 6 are buffer；Described multichannel sends arbitration mould
It is PLC that block 4, multichannel, which receive selecting module 5 and read-write arbitration modules 2,.Wherein, sendaisle cache module 3 is negative
The caching that each sendaisle sends data is blamed, when SDRAM memory 1 is not allocated to and writes time slot, by corresponding circuit-switched data
Write in the SDRAM memories 1 to be written such as sendaisle cache module 3；Receiving channel cache module 6 is responsible for each reception signal
The caching of data, when not reading certain circuit-switched data in time in outside, the reading data of time slot are read in the caching distribution of SDRAM memory 1；
Multichannel, which sends arbitration modules 4, to be responsible for the data that transmitting element multichannel caching is sent carrying out arbitration judgement, at a time secondary
Cut out wherein circuit-switched data initiation write request and give read-write arbitration modules 2, lead to request when read-write arbitration modules 2 are assigned to and write time slot
Track data is written in SDRAM memory 1；Multichannel receives selecting module 5 and completes to read time slot behaviour in the read-write distribution of arbitration modules 2
Which when making, stored data into according to each passage spatial cache occupancy situation selection is received in order caching；Read-write arbitration
Module 2 completes the read-write Time-sharing control of SDRAM memory 1, has SDRAM write request in transmitting element while receiving unit has
Read-write order is arbitrated during data buffer storage space.
Specifically, in the present embodiment, described sendaisle cache module 3 and receiving channel cache module 6 are 20,
20 sendaisle cache modules 3 are distinguished connecting multi-channel transmission 4,20 receiving channel cache modules 6 of arbitration modules and connected respectively
Connect multichannel and receive selecting module 5, it is secondary that multichannel transmission arbitration modules 4 and multichannel reception selecting module 5 connect read-write respectively
Cut out module 2.
Specific work process is as follows：
（1）Transmitting element：Outside data elder generation to be sent subchannel writes respective sendaisle cache module 3（FIFO）
In, the storage state of each road sendaisle cache module 3（Sky is full）Information is sent to multichannel and sends arbitration modules 4, as long as 20
Lu Zhongyou has data in sendaisle cache module 3 all the way, then produces and send written request signal and give read-write arbitration modules 2；Wait
SDRAM requests are write in the read-write response of arbitration modules 2, if SDRAM memory 1 has responded write request, divide in read-write arbitration modules 2
The channel data content for having data in sendaisle cache module 3 is write SDRAM memory 1 by writing in time slot for matching somebody with somebody, and is being write
When response comes into force, if there are data in multichannel sendaisle cache module 3, carried out according to the order of channel number from small to large
Poll write operation.
（2）Read and write arbitration rules:The read-write time slot that read-write arbitration modules 2 are mainly completed to SDRAM memory 1 divides
Match somebody with somebody, there are a data in the summation memory block that sends that ask the visitor in and in the case that external reception is cached with space, priority treatment transmitting element, i.e.,
The data of write request are first write into SDRAM memory 1, write-in data processing is completed（There is no write request）Afterwards, distribute to
SDRAM memory 1 carries out read operation.
（3）Receiving unit：Multichannel receives selecting module 5 and receives the read requests from read-write arbitration modules 2, the request
Judge whether to have in SDRAM memory 1 that data are to be read by read-write arbitration modules 2, while be assigned with again and read time slot to receiving
Unit；Because the data storage in SDRAM memory 1 is according to passage subregion, so the read requests pair of SDRAM memory 1
Answer the channel information of data to be read；Multichannel receives each passage caching situation of the selecting module 5 according to receiving unit（Sky is full）
Which SDRAM storage area data is read in selection, if having data in multichannel spatial cache all not full and SDRMA, and
Transmitting element is the same to be polled reading data according to channel number from small to large, gives in corresponding receiving channel cache module 6.
In summary, the shared read-write SDRAM of this multichannel provided by the utility model circuit arrangement, is that one kind is directed to
The application of SDRAM memory spaces is shared in multi-channel data, by increasing L2 cache and multistage arbitration circuit, timesharing piecemeal control
System, reach the purpose of lifting SDRAM storage service efficiency.
Exemplified as above is only for example, not forming to the scope of protection of the utility model to of the present utility model
Limitation, it is every to be belonged to the same or analogous design of the utility model within protection scope of the present invention.
Claims (4)
1. a kind of shared read-write SDRAM of multichannel circuit arrangement, including SDRAM memory（1）With with SDRAM memory（1）
The read-write arbitration modules of connection（2）, it is characterised in that：Described read-write arbitration modules（2）Be also respectively connected with transmitting element and
Receiving unit, described transmitting element include multiple sendaisle cache modules（3）With with multiple sendaisle cache modules（3）
The multichannel of connection sends arbitration modules（4）, described receiving unit includes multichannel and receives selecting module（5）With with multichannel
Receive selecting module（5）Multiple receiving channel cache modules of connection（6）；
Described multiple sendaisle cache modules（3）Multiple sendaisles are connected respectively, and multichannel sends arbitration modules（4）
It is connected to read and write arbitration modules（2）；
Described multiple receiving channel cache modules（6）Multiple receiving channels are connected respectively, and multichannel receives selecting module（5）
It is connected to read and write arbitration modules（2）；
Described sendaisle cache module（3）With receiving channel cache module（6）Quantity is identical.
2. the shared read-write SDRAM of multichannel as claimed in claim 1 circuit arrangement, it is characterised in that：Described SDRAM is deposited
Reservoir（1）Internal memory space is divided into multiple separate storage regions, and the quantity of separate storage region is no less than sendaisle
Or the quantity of receiving channel.
3. the shared read-write SDRAM of multichannel as claimed in claim 1 or 2 circuit arrangement, it is characterised in that：Described transmission
Passage cache module（3）With receiving channel cache module（6）It is buffer；Described multichannel sends arbitration modules（4）, it is more
Channel reception selecting module（5）With read-write arbitration modules（2）It is PLC.
4. the shared read-write SDRAM of multichannel as claimed in claim 1 circuit arrangement, it is characterised in that：Described transmission is led to
Road cache module（3）With receiving channel cache module（6）It is 20,20 sendaisle cache modules（3）Connect respectively more
Passage sends arbitration modules（4）, 20 receiving channel cache modules（6）Connecting multi-channel receives selecting module respectively（5）, it is more logical
Road sends arbitration modules（4）Selecting module is received with multichannel（5）Connection read-write arbitration modules respectively（2）.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108574870A (en) * | 2018-04-13 | 2018-09-25 | 郑州云海信息技术有限公司 | A kind of display methods, device and the equipment in multi channel signals source |
| CN109271335A (en) * | 2018-07-24 | 2019-01-25 | 上海威固信息技术股份有限公司 | A kind of FPGA implementation method of multi-channel data source DDR caching |
| CN111221754A (en) * | 2020-02-24 | 2020-06-02 | 山东华芯半导体有限公司 | Storage device with read-write collision prevention function |
| CN112040487A (en) * | 2020-07-15 | 2020-12-04 | 中国电子科技集团公司第三十研究所 | Multi-priority efficient 5G network data service security channel management method |
-
2017
- 2017-07-18 CN CN201720867956.0U patent/CN206946471U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108574870A (en) * | 2018-04-13 | 2018-09-25 | 郑州云海信息技术有限公司 | A kind of display methods, device and the equipment in multi channel signals source |
| CN109271335A (en) * | 2018-07-24 | 2019-01-25 | 上海威固信息技术股份有限公司 | A kind of FPGA implementation method of multi-channel data source DDR caching |
| CN109271335B (en) * | 2018-07-24 | 2021-04-20 | 上海威固信息技术股份有限公司 | FPGA implementation method for DDR cache of multi-channel data source |
| CN111221754A (en) * | 2020-02-24 | 2020-06-02 | 山东华芯半导体有限公司 | Storage device with read-write collision prevention function |
| CN112040487A (en) * | 2020-07-15 | 2020-12-04 | 中国电子科技集团公司第三十研究所 | Multi-priority efficient 5G network data service security channel management method |
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