CN103367136A - 将半导体芯片从箔拆下的方法 - Google Patents

将半导体芯片从箔拆下的方法 Download PDF

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CN103367136A
CN103367136A CN201310113448XA CN201310113448A CN103367136A CN 103367136 A CN103367136 A CN 103367136A CN 201310113448X A CN201310113448X A CN 201310113448XA CN 201310113448 A CN201310113448 A CN 201310113448A CN 103367136 A CN103367136 A CN 103367136A
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恩斯特·巴尔梅特勒
费边·赫斯希勒
布莱恩·普利斯
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Abstract

一种用于将半导体芯片从箔拆下的方法，使用包括具有直线支承边缘和L型支承边缘的板的管芯排出器，该方法包括：将板提升至盖板的表面上方的高度H1；降低具有L型支承边缘的第一对板；可选地，降低具有L型支承边缘的第二对板；提升还未被降低的板至高度H2＞H1；交错降低还未被降低的板，至少一个或几个板未被降低；可选地，降低还未被降低的板至高度H3＜H2；降低板直到所有的板都被降低，以及移走芯片夹具，其中在降低最后三个板之前芯片夹具触及半导体芯片。

Description

将半导体芯片从箔拆下的方法
技术领域
本发明涉及一种将半导体芯片从箔拆下的方法。
背景技术
半导体芯片通常被设置在由框架保持的箔上以用于在半导体安装装置上处理，在本领域中该箔也被称为胶带。半导体芯片粘在箔上。通过可移位的晶片台容纳具有箔的框架。该晶片台被移位，以在某一位置处依次提供半导体芯片，并且所提供的半导体芯片被芯片夹具拾取并且被循环地放置在基板上。由布置在箔下方的芯片排出器(在本领域被称为管芯排出器)支持从箔上移走所提供的半导体芯片的操作。
从US7115482中获知从箔拆下半导体芯片的方法，其中使用具有彼此相邻设置的多个板的管芯排出器。板被一起提升以拆下半导体芯片并且然后从外部到内部被顺序地降低，或者从外部到内部顺序地被提升以形成突出超过支承平面的锥体***。也可以从CN101740349A、US2010-252205和US8092645中获知这样的管芯排出器和方法。
发明内容
本发明基于进一步改进这样的拆卸方法的目标。
根据本发明，芯片夹具和包括具有直线支承边缘的第一板和具有L型支承边缘的第二板的管芯排出器被用于将半导体芯片从箔拆下。在初始位置，板的支承边缘形成箔搁置在其上的的支承平面。所述方法包括以下步骤：
A)提升所述板，使得板的支承边缘占据管芯排出器的盖板的表面上方的高度H1；
B)降低具有L型支承边缘的第一对板；
C)可选地，降低具有L型支承边缘的第二对板；
D)提升还未被降低的板，使得还没有被降低的板的支承边缘占据盖板的表面上方的高度H2＞H1；
E)按照特定的顺序，交错降低还未被降低的板，并且至少一个或几个板未被降低；
F)可选地，降低至少还未被降低的板，使得还未被降低的板的支承边缘占据盖板的表面上方的高度H3＜H2；
G)降低还未被降低的板直到所有的板都被降低，以及
H)移走具有半导体芯片的芯片夹具，
其中最迟在降低最后三个板之前，将芯片夹具定位在半导体芯片上方，并且降低所述芯片夹具直到它触及所述半导体芯片。
优选地，板被固定到载体，载体可垂直于盖板的表面移位，并且板可相对于载体被提升和降低。在初始位置，载体被设置在预定位置z0上，并且相对于载体提升板，使得板的支承边缘形成箔搁置在其上的支承平面。优选地，在步骤A中载体被提升预定距离Δz1，在步骤D中载体被提升预定距离Δz2，以及在可选的步骤F中载体被降低预定距离Δz3。
附图说明
被并入该说明书并构成该说明书的一部分的附图示出本发明的一个或更多个实施例，并且与具体说明一起用于解释本发明的原理和实施。附图不是真实的尺寸。
在附图中：
图1示出管芯排出器的侧视图和截面图；
图2以顶视图示出管芯排出器；
图3以透视图示出具有L型支承边缘的板；
图4示出管芯排出器的板的支承边缘的顶视图，并且
图5至图13示出拆卸过程的快照。
具体实施方式
图1示出具有主要从EP2184765中获知的构造的管芯排出器1的侧视截面图。管芯排出器1包括封闭腔2，其可以被提供有真空并且包括优选可移动和可交换的盖板3，具有半导体芯片5的箔4的一部分搁置在该盖板3上。还可以由管芯排出器1的外壳或其部分形成腔2。盖板3还可以是盖子。盖板3包含在中部的矩形孔6并且优选地包含多个附加孔7，该矩形孔6大约和半导体芯片5一样大，所述多个附加孔7仅在图2中示出并且用于在腔2被提供有真空时吸取箔4。管芯排出器1还包括在腔2内部被相邻布置并且固定到载体9的多个板8。管芯排出器1包括第一驱动器10，该第一驱动器10用于使载体9垂直于盖板3的表面12，即在该情况下沿z方向移位。管芯排出器1包括第二驱动器11，该第二驱动器11用于使板8相对于载体9在垂直于盖板3的表面12的方向上移位。因此载体9和板8二者能够被相对于箔4的表面提升和降低。
板8突出到盖板3的中心孔6中。在板8和孔6的边缘之间存在周边空隙13。腔2可以被提供有真空。管芯排出器1的盖板3的孔6内的板8占据的面积优选稍微小于半导体芯片5的面积，也就是以这样的方法确定尺寸，即半导体芯片5将在横向方向上的所有边上超出板8所占据的面积大约0.5至1mm。板8的数目和形状取决于半导体芯片5的尺寸。
在半导体芯片非常小的情况下，即通常在具有至多大约5mm的边缘长度的半导体芯片5的情况下，将仅使用具有直线支承边缘的板8。在中等尺寸半导体芯片的情况下，即通常在具有处于大约5至7mm的范围中的边缘长度的半导体芯片5的情况下，将使用具有直线支承边缘的板8和具有L型支承边缘的一对板。在半导体芯片5更大的情况下，将使用具有直线支承边缘的板8和具有L型支承边缘的两对或更多对(通常两对)板8。具有直线支承边缘的板8被布置在中央并分别被具有L型支承边缘的板成对地包围。
由于显示清晰度的缘故，图1中仅示出具有直线支承边缘的板8。图3示出具有L型支承边缘19的板8的透视图。在该实施例中，支承边缘19设有多个齿，以使在齿之间的中间空间中的真空将达到箔4的底侧并且因此将增加吸取力。支承边缘还可以被布置为没有齿，即，是平坦边缘。
图4示出构造用于相对大的半导体芯片的管芯排出器1的板8的支承边缘19的顶视图。该实施例中的板包括具有直线支承边缘的9个板8A和具有L型支承边缘的两对板8B和8C，即共有具有L型支承边缘的四个板。词语“直线”和“L型”涉及支承边缘19在支承平面中的形状。
具有L型支承边缘的第一对板8B(内部对)包围具有直线支承边缘的板8A。具有L型支承边缘的第二对板8C(外部对)包围具有L型支承边缘的内部对板8B。
借助于与芯片夹具16(图10)配合的管芯排出器1，发生半导体芯片5从箔4的拆卸和移除。芯片夹具16有利地包含吸取构件，该吸取构件可以被提供有真空并且将吸住半导体芯片并紧紧保持该芯片。芯片夹具16还可以包含基于伯努利效应的吸取构件，该吸取构件需要被提供有压缩空气以便实现吸入效应。将参考图5至图13详细解释拆卸半导体芯片的方法，所述图分别表示快照。图5至图13中未示出箔4和用于移动板8的驱动设备。板8在正z方向上的移动将会被指定为提升，而板8在负z方向上的移动将会被指定为降低。
为了将下一个半导体芯片从箔4拆下，箔4被相对于管芯排出器1移位，使得将待拆下的半导体芯片5定位在盖板3的孔6上方。另外，所有的板8被相对于载体9提升，使得它们的支承边缘19位于公共平面中，并且载体9被带入至预定位置z0，在预定位置z0中支承边缘19与盖板3的表面12齐平。在该初始位置中，箔4搁置在板8的支承边缘19上。用于从箔4拆下半导体芯片5的方法包括以下步骤：
A)提供真空的腔2，从而箔4被吸向盖板3；
B)以预定距离Δz1提升载体9，使得板8的支承边缘19将占据盖板3的表面12上方的高度H1；
C)降低具有L型支承边缘的最外部的一对板8C；
D)可选地，降低具有L型支承边缘的第二对板8B；
E)以预定距离Δz2提升载体9，使得还没有被降低的板的支承边缘将占据盖板3的表面12上方的高度H2＞H1；
F)按照预定的顺序，交错降低还未被降低的板8，并且至少一个或几个(优选三个)板8A未被降低；
G)可选地，降低载体9预定距离Δz3，使得还未被降低的板的支承边缘占据盖板3的表面12上方的高度H3＜H2；
H)交错降低还未被降低的板8A；
I)移走具有半导体芯片5的夹具16；
J)其中最迟在降低最后三个板8A之前，将芯片夹具16定位在半导体芯片5上方，并且降低芯片夹具16直到它触及并紧紧保持半导体芯片5。
图5示出初始位置的快照。
图6示出步骤B之后的快照。
图7示出步骤C之后的快照。
图8示出步骤E之后的快照。
图9至图11示出E和G之间连续的快照。
图12示出步骤G之后的快照。
图13示出步骤H之后的快照。
降低相应的下一个板能够在前面的板被全部降低之前发生，如图8至图12所示。芯片夹具16的支承的用于从半导体芯片5拆下箔4所需的时间点取决于以下几个因素，诸如半导体芯片5的厚度、半导体芯片5的尺寸、箔4的粘附力、由真空施加在箔4上的吸力。越晚需要使用芯片夹具16，自动组装机的生产率就越大。
为了准备下一个半导体芯片5的移除，板8再次被带回到初始位置。
使用具有L型支承边缘的板降低了机械负载对邻近的半导体芯片的影响，并且因此允许达到大于现有技术水平的高度H2，这促进了半导体芯片从箔的拆卸。
尽管本发明的实施例和应用已经被示出且描述，但对于获得本说明书的益处的本领域技术人员来说显而易见的是，在不背离本发明的构思的情况下，除上文提及之外的许多更多的修改是可能的。因此，除了所附权利要求及其等同物的精神之外，本发明不被限制。

Claims (2)

1.借助于芯片夹具(16)和管芯排出器(1)将半导体芯片(5)从箔(4)拆下的方法，所述管芯排出器(1)包括具有直线支承边缘的第一板(8A)和具有L型支承边缘的第二板(8B、8C)，位于初始位置的所述板(8A、8B、8C)的所述支承边缘(19)形成所述箔(4)搁置在其上的支承平面，所述方法包括以下步骤：
A)提升所述板(8A、8B、8C)，使得所述板(8A、8B、8C)的所述支承边缘(19)占据盖板(3)的表面(12)上方的高度H1；
B)降低具有L型支承边缘的第一对板(8B)；
C)可选地，降低具有L型支承边缘的第二对板(8C)；
D)提升还未被降低的所述板，使得还没有被降低的所述板的所述支承边缘(19)占据所述盖板(3)的所述表面(12)上方的高度H2＞H1；
E)按照特定的顺序，交错降低还未被降低的板，并且至少一个或多个板(8A)未被降低；
F)可选地，降低至少还未被降低的所述板，使得还未被降低的所述板的所述支承边缘(19)占据所述盖板(3)的所述表面(12)上方的高度H3＜H2；
G)降低还未被降低的所述板直到所有的板(8A、8B、8C)都被降低，以及
H)移走具有所述半导体芯片(5)的所述芯片夹具(16)，
其中最迟在降低最后三个板(8A)之前，将所述芯片夹具(16)定位在所述半导体芯片(5)上方，并且降低所述芯片夹具(16)直到所述芯片夹具(16)触及所述半导体芯片(5)。
2.根据权利要求1所述的方法，其中所述板(8A、8B、8C)被固定到载体(9)，所述载体(9)能够垂直于所述盖板(3)的所述表面(12)移位，并且所述板(8A、8B、8C)能够相对于所述载体(9)被提升和降低，在初始位置所述载体(9)被设置在预定位置z0中，并且相对于所述载体(9)提升所述板(8A、8B、8C)，使得所述板(8A、8B、8C)的所述支承边缘(19)形成所述箔(4)搁置在其上的支承平面，其特征在于：
在步骤A中所述载体(9)被提升预定距离Δz1；
在步骤D中所述载体(9)被提升预定距离Δz2，以及
在可选的步骤F中所述载体(9)被降低预定距离Δz3。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106463341A (zh) * 2014-06-18 2017-02-22 综合制造科技有限公司 使用多阶推顶器从胶带剥离半导体芯片的***及方法
CN111063653A (zh) * 2018-10-16 2020-04-24 先进装配***有限责任两合公司 用于促进布置在保持膜片上的部件脱离的顶脱器装置和方法

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH707236B1 (de) 2012-11-23 2016-10-31 Besi Switzerland Ag Verfahren zum Ablösen von Halbleiterchips von einer Folie.
JP5717910B1 (ja) * 2014-02-26 2015-05-13 株式会社新川 半導体ダイのピックアップ装置及びピックアップ方法
JP6797569B2 (ja) * 2016-06-13 2020-12-09 ファスフォードテクノロジ株式会社 半導体製造装置および半導体装置の製造方法
TWI648213B (zh) * 2017-11-30 2019-01-21 景碩科技股份有限公司 撕箔機構
JP2019169516A (ja) * 2018-03-22 2019-10-03 東芝メモリ株式会社 半導体装置の突き上げ装置及び突き上げ方法
CN109192681B (zh) * 2018-09-01 2022-05-31 佛山市美特智能科技有限公司 芯片的快速柔性制造***
JP7217605B2 (ja) * 2018-09-21 2023-02-03 ファスフォードテクノロジ株式会社 半導体製造装置、突上げ治具および半導体装置の製造方法
CH715447B1 (de) 2018-10-15 2022-01-14 Besi Switzerland Ag Chip-Auswerfer.
KR102656718B1 (ko) * 2018-11-05 2024-04-12 세메스 주식회사 다이 이젝팅 장치
JP7274902B2 (ja) 2019-03-25 2023-05-17 ファスフォードテクノロジ株式会社 半導体製造装置および半導体装置の製造方法
KR102020034B1 (ko) * 2019-07-09 2019-09-10 (주)삼정오토메이션 적층세라믹콘덴서 취출 방법
KR102177863B1 (ko) * 2020-08-07 2020-11-11 변영기 칩 필름 단계적 박리장치
US11764098B2 (en) * 2021-04-16 2023-09-19 Asmpt Singapore Pte. Ltd. Detaching a die from an adhesive tape by air ejection
JP2023064405A (ja) * 2021-10-26 2023-05-11 三菱電機株式会社 半導体製造装置および半導体装置の製造方法
JP2023167124A (ja) 2022-05-11 2023-11-24 三星電子株式会社 チップ剥離装置及びチップ剥離方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030075271A1 (en) * 2001-10-23 2003-04-24 Fujitsu Limited Method and device of peeling semiconductor device using annular contact members
CN1599035A (zh) * 2003-09-17 2005-03-23 株式会社瑞萨科技 制造半导体器件的方法
CN101335191A (zh) * 2007-06-19 2008-12-31 株式会社瑞萨科技 半导体集成电路装置的制造方法
CN101740349A (zh) * 2008-11-05 2010-06-16 Esec公司 芯片分离器
US20100252205A1 (en) * 2009-04-02 2010-10-07 Man Wai Chan Device for thin die detachment and pick-up

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH697213A5 (de) * 2004-05-19 2008-06-25 Alphasem Ag Verfahren und Vorrichtung zum Ablösen eines auf eine flexible Folie geklebten Bauteils.
JP4735829B2 (ja) * 2005-12-06 2011-07-27 澁谷工業株式会社 チップ突き上げ装置
US7665204B2 (en) * 2006-10-16 2010-02-23 Asm Assembly Automation Ltd. Die detachment apparatus comprising pre-peeling structure
JP4693805B2 (ja) * 2007-03-16 2011-06-01 株式会社東芝 半導体装置の製造装置及び製造方法
TWI463580B (zh) 2007-06-19 2014-12-01 Renesas Electronics Corp Manufacturing method of semiconductor integrated circuit device
US8092645B2 (en) * 2010-02-05 2012-01-10 Asm Assembly Automation Ltd Control and monitoring system for thin die detachment and pick-up
JP2011216529A (ja) * 2010-03-31 2011-10-27 Furukawa Electric Co Ltd:The 半導体装置の製造方法
CH707236B1 (de) * 2012-11-23 2016-10-31 Besi Switzerland Ag Verfahren zum Ablösen von Halbleiterchips von einer Folie.

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030075271A1 (en) * 2001-10-23 2003-04-24 Fujitsu Limited Method and device of peeling semiconductor device using annular contact members
CN1599035A (zh) * 2003-09-17 2005-03-23 株式会社瑞萨科技 制造半导体器件的方法
CN101335191A (zh) * 2007-06-19 2008-12-31 株式会社瑞萨科技 半导体集成电路装置的制造方法
CN101740349A (zh) * 2008-11-05 2010-06-16 Esec公司 芯片分离器
US20100252205A1 (en) * 2009-04-02 2010-10-07 Man Wai Chan Device for thin die detachment and pick-up

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106463341A (zh) * 2014-06-18 2017-02-22 综合制造科技有限公司 使用多阶推顶器从胶带剥离半导体芯片的***及方法
CN106463341B (zh) * 2014-06-18 2019-03-26 砺铸智能装备私人有限公司 使用多阶推顶器从胶带剥离半导体芯片的***及方法
CN111063653A (zh) * 2018-10-16 2020-04-24 先进装配***有限责任两合公司 用于促进布置在保持膜片上的部件脱离的顶脱器装置和方法

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