CN103246584A - Chip structure of system-on-chip and method for storing debug information - Google Patents
Chip structure of system-on-chip and method for storing debug information Download PDFInfo
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Abstract
The invention provides a chip structure of a system-on-chip and a method for storing debug information. The method for storing the debug information includes: firstly, appointing parts of subunits in a storing unit comprised by the chip structure of the system-on-chip to store the debug information; secondly, recording the debug information of the own chip structure of the system-on-chip by a recording unit in the chip structure of the system-on-chip when a processing unit of the chip structure of the system-on-chip executes debug operation; and finally, writing the debug information recorded by the recoding unit into the parts of the subunits by a reading unit of the chip structure of the system-on-chip when the processing unit does not read or write the storing unit. The chip structure of the system-on-chip and the method for storing the debug information have the advantages that no single storer for storing the debug information exists in a storer, and no pin connected with external storer is arranged, so that area of the chip can be effectively saved, and cost can be reduced.
Description
Technical field
The present invention relates to a kind of integrated circuit fields, the method that particularly relates to a kind of on-chip system chip structure and preserve Debugging message.
Background technology
On-chip system chip (being the SoC chip) is a kind of processor or System on Chip/SoCs such as DSP, storer of comprising, and the complication system function can be programmed to realize to this System on Chip/SoC in the outside.Because SoC can reduce electronics/infosystem Products Development cost effectively, shorten the construction cycle, improve competitiveness of product, so it will progressively become the topmost product development mode that industry member adopts.
Quality in order to ensure the SoC chip, usually, the circuit that the SoC chip that research staff or chip production merchant need design or produce oneself comprises is debugged, and with obtain such as bus read and write data, the chip internal state, the Debugging message such as jump address of routine change flow process, wait to offer the commissioning staff by external emulator, so that the usefulness of analysis.
Present debugging technique mainly contains two kinds: a kind of is that independently storage unit is set in the SoC chip, by the debugging module in the chip Debugging message of the chip gathered is write this independently storage unit; Another kind is to use external memory storage, by the debugging module in the chip Debugging message of the chip gathered is write this external memory storage.Yet in existing this dual mode, preceding a kind of mode can take a large amount of chip areas, increases production cost, and a kind of mode in back can additionally increase chip pin quantity, and debugging speed also can be restricted.
Therefore, the utmost point is necessary the debugging technique of existing SoC chip is improved.
Summary of the invention
The shortcoming of prior art the object of the present invention is to provide the little on-chip system chip structure of a kind of chip area in view of the above.
Another object of the present invention is to provide a kind of method of preserving Debugging message, in order to do not need independent storer to store Debugging message.
Reach other relevant purposes for achieving the above object, on-chip system chip structure provided by the invention, it comprises at least: processing unit; The storage unit that is connected with described processing unit; The record cell that is used for the record Debugging message; And the read-write cell that is connected with described storage unit and record cell, be used for when described processing unit does not carry out read or write to described storage unit, the Debugging message that described record cell is recorded writes in the pre-stator unit of described storage unit or with the Debugging message in the described pre-stator unit and reads.
Preferably, described record cell also comprises: first signal output apparatus, and when being filled with Debugging message, its temporary storage location that comprises for the record cell under self exports first alert signal to read-write cell.
Preferably, described read-write cell also comprises: the secondary signal output circuit, it is used for output second alert signal to described processing unit, in order to described processing unit is suspended described storage unit is carried out read or write.
The method of preservation Debugging message provided by the invention is used for aforesaid on-chip system chip structure, and it may further comprise the steps:
-the specified portions subelement is used for the storage Debugging message in the storage unit that described on-chip system chip structure comprises;
-processing unit in described on-chip system chip structure is carried out in the process of debugging operation the Debugging message of on-chip system chip structure under the recording unit records self in the described on-chip system chip structure; And
When the read-write cell the in-described on-chip system chip structure did not carry out read or write to described storage unit at described processing unit, the Debugging message that described record cell is recorded write described parton unit.
Preferably, the method for described preservation Debugging message also comprises when temporary storage location that described record cell comprises has been filled with Debugging message and exports first alert signal to the step of read-write cell.
Preferably, the method for described preservation Debugging message comprises that also described read-write cell exports second alert signal to described processing unit, so that described processing unit suspends the step that described storage unit is carried out read or write.
As mentioned above, on-chip system chip structure of the present invention and the method for preserving Debugging message have following beneficial effect: do not have independent storer to store Debugging message in the chip, can effectively save chip area thus, reduce cost; In addition, chip does not have the pin that is connected with external memory storage is set yet, thus effectively reduce pin of chip quantity, and then reduced the preparation cost of chip.
Description of drawings
Fig. 1 is shown as the structural representation of on-chip system chip structure of the present invention.
Fig. 2 is shown as a kind of preferred structure synoptic diagram of on-chip system chip structure of the present invention.
Fig. 3 is shown as the another kind of preferred structure synoptic diagram of on-chip system chip structure of the present invention.
Fig. 4 is shown as the process flow diagram of the method for preservation Debugging message of the present invention.
The element numbers explanation
1 on-chip system chip structure
11 processing units
12 storage unit
13 record cells
131 first signal output apparatus
14 read-write cells
141 secondary signal output circuits
Embodiment
Below by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this instructions.The present invention can also be implemented or be used by other different embodiment, and the every details in this instructions also can be based on different viewpoints and application, carries out various modifications or change under the spirit of the present invention not deviating from.
See also Fig. 1 to Fig. 4.Need to prove, the diagram that provides in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy only show in graphic with the present invention in relevant assembly but not component count, shape and size drafting when implementing according to reality, kenel, quantity and the ratio of each assembly can be a kind of random change during its actual enforcement, and its assembly layout kenel also may be more complicated.
As shown in the figure, the invention provides a kind of on-chip system chip structure, described on-chip system chip structure 1 comprises at least: processing unit 11, storage unit 12, record cell 13 and read-write cell 14.
Described processing unit 11 is as the core cell of on-chip system chip, the function that its circuit structure that comprises will be finished based on on-chip system chip determines that preferably, it comprises the circuit unit that comprises processor, for example, comprise one or more circuit unit among CPU, MCU, the DSP.
More detailed speech it, for example, described processing unit 11 comprise among CPU, MCU, the DSP one or more, clock circuit, timer, interruptable controller, serial-parallel interface, other peripherals, I/O port and be used for adhesive logic between the various IP kernels etc.
Described storage unit 12 is connected with described processing unit 11, is used for storage information.Preferably, described processing unit 11 comes described storage unit 12 is carried out read or write by bus.Preferably, described storage unit 12 comprises storeies such as various volatile, non-volatile or Cache.
Described record cell 13 is used for the record Debugging message.Wherein, described Debugging message comprises the various data messages that its internal circuit produces when described on-chip system chip structure 1 is debugged operation, preferably, include but not limited to: the jump address of the data of bus read-write, chip internal status information, routine change flow process etc.
Preferably, described record cell 13 comprises temporary storage location, and described temporary storage location can adopt storeies such as volatile, non-volatile or Cache to realize, also can adopt register to wait to realize.
Need to prove that in order to reduce chip area, the memory capacity of the temporary storage location that described record cell 13 comprises is as far as possible little, is preferably 8 to 16 bytes etc.
Described read-write cell 14 is connected with described storage unit 12 and record cell 13, be used for when described processing unit 11 does not carry out read or write to described storage unit 12, the Debugging message that described record cell 13 is recorded writes in the pre-stator unit of described storage unit 13.
Wherein, described pre-stator unit is preassigned subelement for the storage Debugging message, and preferably, it be sequential cells, for example, with address " 1234 " in the described storage unit 12 to the address storage unit of " 3FFF " be used for to store Debugging message.
Particularly, all whether the free time determines whether described processing unit 11 is carrying out read or write to described storage unit 12 to described read-write cell 14 by monitoring read data line between described processing unit 11 and the described storage unit 12 and write data line, and when when described processing unit 11 does not carry out read or write to described storage unit 12, the Debugging message that described record cell 13 is recorded writes in the pre-stator unit of described storage unit 13.
Those skilled in the art should be appreciated that the circuit structure of read-write cell based on above stated specification, so be not described in detail in this.
As of the present invention a kind of preferred, aforementioned record cell 13 comprises first signal output apparatus 131, as shown in Figure 2.
When being filled with Debugging message, the temporary storage location that described first signal output apparatus 131 comprises for the record cell 13 under self exports first alert signal to read-write cell 14, so that the Debugging message that described read-write cell 14 is in time stored described temporary storage location write in the pre-stator unit of described storage unit 12.
Wherein, first alert signal comprises that any temporary storage location that can show that record cell 13 comprises has been filled with the signal of Debugging message, preferably, includes but not limited to: low level signal, high level signal etc.
Particularly, described first signal output apparatus 131 can first be informed information based on relatively exporting of the byte number of the byte number of Debugging message to be recorded or address information and described temporary storage location or maximum address information.Preferably, described first signal output apparatus 131 can adopt comparator circuit to wait to realize.
As of the present invention a kind of preferred, aforementioned read-write cell 14 also comprises secondary signal output circuit 141, as shown in Figure 3.
Described secondary signal output circuit 141 is used for output second alert signal to described processing unit 11, in order to described processing unit 11 is suspended described storage unit 12 is carried out read or write, be convenient to described read-write 14 thus Debugging message is write in the pre-stator unit of described storage unit 12.
Wherein, second alert signal comprises any signal that can make described processing unit 11 time-outs that described storage unit 12 is carried out read or write, preferably, includes but not limited to: low level signal, high level signal etc.
Particularly, when described read-write cell 14 receives from first alert signal of first signal output apparatus, 131 outputs or because other reasons etc., when described read-write cell 14 need write the pre-stator unit of described storage unit 12 with the Debugging message that described record cell 13 records, if described processing unit 11 carries out read or write to described storage unit 12, then second alert signal of described secondary signal output circuit 141 output one such as high level etc. is to described processing unit 11, so that the read or write that described processing unit 11 suspends described storage unit 12.
Those skilled in the art should be appreciated that the circuit structure of first signal output apparatus based on above stated specification, so be not described in detail in this.
In addition, also need to prove, described on-chip system chip structure 1 also can comprise other functional module elements based on user's needs, for example, the analog front-end module, the power supply that comprise ADC/DAC provide with power managed module, RF front-end module, user and define logic and microelectron-mechanical module etc., describe in detail no longer one by one at this.
Based on earlier figures 1 to Fig. 3 any one on-chip system chip structure 1, the invention provides a kind of method of preserving Debugging message, as shown in Figure 4.
In step S1, the specified portions subelement is used for the storage Debugging message in the storage unit 12 that aforementioned on-chip system chip structure 1 comprises.
Particularly, in the debug phase, in described storage unit 12, distribute a subelement as debug memory earlier, be used for preserving Debugging message, unit in the described storage unit 12 except debug memory is as shared drive, processing unit 11 or other functional modules that this moment, described on-chip system chip structure 1 comprised will avoid using debug memory, and can be kept in the register of record cell 14 by the start address of the enable signal of the employed shared drive of other functional modules in described processing unit 11 or the described on-chip system chip structure 1 and debug memory distribution.
In step S2, the processing unit 11 in described on-chip system chip structure 1 is carried out in the process of debugging operation, the Debugging message of on-chip system chip structure 1 under record cell 14 records in the described on-chip system chip structure self.
Wherein, known to those skilled in the art knowing already done in the debugging that described processing unit 11 is carried out, so be not described in detail in this.
Particularly, processing unit 11 in described on-chip system chip structure 1 is carried out in the process of debugging operations, the reading and writing data of the connecting line (as the read/write bus) of the described storage unit 12 of connection in the described on-chip system chip structure 1 of described record cell 14 records, chip internal status data, the data such as jump address when processing unit 11 changes tasks.
In step S3, when the read-write cell 14 in the described on-chip system chip structure 1 did not carry out read or write to described storage unit at described processing unit 11, the Debugging message that described record cell 13 is recorded write described parton unit (being debug memory).
Particularly, described read-write cell 14 detects read/write data line between described processing unit 11 and the described storage unit 12 when idle, and the Debugging message that described record cell 13 is recorded writes in the debug memory.
If the read/write data line between described processing unit 11 and the described storage unit 12 is busy, the temporary storage location that causes described record cell 13 to comprise has been filled with Debugging message, then first signal output apparatus 131 output, first alert signal that comprises of described record cell 13 is to described read-write cell 14, so that the Debugging message that described read-write cell 14 in time records described record cell 13 write in the debug memory.
In addition, when described read-write cell 14 preparations write Debugging message to described storage unit 12, if described processing unit 11 is carrying out read or write to described storage unit 12, then the secondary signal output circuit that comprises of described read-write cell 14 141 outputs second alert signal is to described processing unit 11, so that described processing unit 11 discharges the read/write data line of described storage unit 12, subsequently, described read-write cell 14 can utilize the read/write data bundle of lines Debugging message of described storage unit 12 to move in the debug memory, and described processing unit 11 recovers operate as normal more then.
Have again, behind storage Debugging message in the debug memory, can read Debugging message in the described debug memory by outside on-line debugging emulator, and this Debugging message analyzed etc.
In sum, the Debugging message write storage unit (being in the Installed System Memory) that the method for on-chip system chip structure of the present invention and preservation Debugging message can record record cell based on read-write cell, owing to do not have independent storer to store Debugging message in the chip, so can effectively save chip area, reduce cost; In addition, chip does not have the pin that is connected with external memory storage is set yet, thus effectively reduce pin of chip quantity, and then reduced the preparation cost of chip.So the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not is used for restriction the present invention.Any person skilled in the art scholar all can be under spirit of the present invention and category, and above-described embodiment is modified or changed.Therefore, have in the technical field under such as and know that usually the knowledgeable modifies or changes not breaking away from all equivalences of finishing under disclosed spirit and the technological thought, must be contained by claim of the present invention.
Claims (9)
1. an on-chip system chip structure is characterized in that, described on-chip system chip structure comprises at least:
Processing unit;
The storage unit that is connected with described processing unit;
The record cell that is used for the record Debugging message;
The read-write cell that is connected with described storage unit and record cell is used for when described processing unit does not carry out read or write to described storage unit, and the Debugging message that described record cell is recorded writes in the pre-stator unit of described storage unit.
2. on-chip system chip structure according to claim 1 is characterized in that, described record cell also comprises:
First signal output apparatus is used for exporting first alert signal to read-write cell when temporary storage location that self affiliated record cell comprises has been filled with Debugging message.
3. on-chip system chip structure according to claim 1 is characterized in that, described read-write cell also comprises:
The secondary signal output circuit is used for output second alert signal to described processing unit, in order to described processing unit is suspended described storage unit is carried out read or write.
4. on-chip system chip structure according to claim 1, it is characterized in that: described processing unit comprises the circuit unit that comprises processor.
5. on-chip system chip structure according to claim 4, it is characterized in that: described processing unit comprises one or more among CPU, MCU, the DSP.
6. a method of preserving Debugging message is used for each described on-chip system chip structure of claim 1 to 5, and the method for described preservation Debugging message is characterised in that and comprises step:
-the specified portions subelement is used for the storage Debugging message in the storage unit that described on-chip system chip structure comprises;
-processing unit in described on-chip system chip structure is carried out in the process of debugging operation the Debugging message of on-chip system chip structure under the recording unit records self in the described on-chip system chip structure;
When the read-write cell the in-described on-chip system chip structure did not carry out read or write to described storage unit at described processing unit, the Debugging message that described record cell is recorded write described parton unit.
7. the method for preservation Debugging message according to claim 6 is characterized in that also comprising step: export first alert signal when temporary storage location that described record cell comprises has been filled with Debugging message to read-write cell.
8. the method for preservation Debugging message according to claim 6 is characterized in that also comprising step: described read-write cell is exported second alert signal to described processing unit, so that described processing unit suspends described storage unit is carried out read or write.
9. the method for preservation Debugging message according to claim 6 is characterized in that also comprising step: the Debugging message in the described parton unit is read.
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| CN106575258A (en) * | 2014-08-08 | 2017-04-19 | 三星电子株式会社 | Electronic device, on-chip memory and method of operating the on-chip memory |
| CN109144853A (en) * | 2018-07-26 | 2019-01-04 | 中国电子科技集团公司第五十四研究所 | A kind of software-defined radio SoC chip debugging system |
| CN110032482A (en) * | 2019-04-11 | 2019-07-19 | 盛科网络（苏州）有限公司 | Sheet sand covered device and method |
| CN115221070A (en) * | 2022-08-02 | 2022-10-21 | 无锡众星微***技术有限公司 | NVMe disk-based system-on-chip diagnosis method |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106575258A (en) * | 2014-08-08 | 2017-04-19 | 三星电子株式会社 | Electronic device, on-chip memory and method of operating the on-chip memory |
| CN109144853A (en) * | 2018-07-26 | 2019-01-04 | 中国电子科技集团公司第五十四研究所 | A kind of software-defined radio SoC chip debugging system |
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| CN110032482A (en) * | 2019-04-11 | 2019-07-19 | 盛科网络（苏州）有限公司 | Sheet sand covered device and method |
| CN115221070A (en) * | 2022-08-02 | 2022-10-21 | 无锡众星微***技术有限公司 | NVMe disk-based system-on-chip diagnosis method |
| CN115221070B (en) * | 2022-08-02 | 2023-06-20 | 无锡众星微***技术有限公司 | NVMe disk-based system-on-chip diagnosis method |
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Effective date of registration: 20171102 Address after: 610200 Sichuan Chengdu Shuangliu District Dongsheng Street Chengdu core industrial park concentration area Patentee after: Montage LZ Technologies (Chengdu) Co.,Ltd. Address before: Suzhou City, Jiangsu Province, Suzhou Industrial Park 215123 Xinghu Street No. 328 Creative Industry Park 6-1002 Patentee before: SUZHOU MONTAGE MICROELECTRONIC TECHNOLOGY Co.,Ltd. |
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Denomination of invention: On Chip System Chip Architecture and Methods for Saving Debugging Information Granted publication date: 20170222 Pledgee: Renlai Electronic Technology (Shanghai) Co.,Ltd. Pledgor: Montage LZ Technologies (Chengdu) Co.,Ltd. Registration number: Y2024980016173 |