CN206331414U - A kind of solid state hard disc - Google Patents
A kind of solid state hard disc Download PDFInfo
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- CN206331414U CN206331414U CN201620656466.1U CN201620656466U CN206331414U CN 206331414 U CN206331414 U CN 206331414U CN 201620656466 U CN201620656466 U CN 201620656466U CN 206331414 U CN206331414 U CN 206331414U
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- state hard
- solid
- nand flash
- hard disc
- hard disk
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Abstract
The utility model discloses a kind of solid state hard disc, including multiple NAND FLASH and solid-state hard disk controller；The solid-state hard disk controller includes status register；The multiple NAND FLASH free/busy signal pins access the status register by monitoring pin.The utility model need to only define a pin monitoring, when all NAND FLASH are idle condition, NAND FLASH can directly be judged for idle condition, without spending solid-state hard disk controller to pass through the time spent by command access NAND FLASH each logic unit；Only increase a chip pin, chip volume and manufacturing cost are not influenceed.
Description
Technical field
The utility model is related to electronic technology field, especially a kind of solid state hard disc.
Background technology
Solid state hard disc (Solid State Disk) is with the hard disk that solid-state electronic storage chip is storage medium, by controlling
Device unit and memory cell composition.NAND FLASH are the most widely used storage medium in memory cell.
Due to NAND FLASH characteristic, solid state hard disc has following features：
1. cache (Buffer)：
Each data storage and the erasing of the block page and writing speed in NAND FLASH are different.In order to carry
The stability of high write performance, the data of solid state hard disc write-in can be first put into cache (Buffer), then are written to many
In individual NAND FLASH.In addition, some system core information during normal use can be also put into cache by solid state hard disc.
So there being storage in cache：Not yet write NAND FLASH data cached and system core information.When solid state hard disc
When external power source is turned off, the data in cache will lose；
It is not lost in order to which reliability preserves the data in cache, solid state hard disc is configured with standby electric module, so as to outside
There is provided the power supply of short time during portion's power remove, allow controller that the data in cache are written in NAND FLASH.
2. logic unit READY/BUSY（Free/busy）Monitoring：
According to ONFI and Toggle protocol requirements：When carrying out erase or write operation to NAND FLASH, it is necessary to first look into
Ask the FLASH logic units of writing area（LUN）State, when the state that detects for free time（Ready）When operated again.
Otherwise NAND FLASH will not response controller order.
The usual way of current industry：
1. solid-state hard disk controller passes through command access NAND FLASH each logic unit（LUN）, but for tool
There is the solid state hard disc of multiple NAND FLASH chips, it will there are tens logic units.Solid-state hard disk controller completes all patrol
Collecting the conditional access of unit at least needs hundreds of the microseconds even time of Millisecond.For some to time requirement extremely harshness
Operation, such as：Data write-in before solid state hard disc power down in cache.Due to standby electric module for power supply duration generally only
There is the time of Millisecond, accessing energy storage consumption of the time of logic unit consuming to standby electric module will be very big；
2. solid-state hard disk controller defines the physical pin with the quantity such as required NAND FLASH logic units, directly with
Each logic unit of NAND FLASH READY/BUSY（Free/busy）Signal pins are connected.This scheme requires that solid-state is hard
Disk control chip at least needs many reserved tens pins when designing, and pin number directly affects the volume of chip and is manufactured into
This.
The drawbacks of having larger in two schemes as can be seen here, there will naturally be inconvenience and defect in actual applications,
It is therefore necessary to improved.
The content of the invention
Technical problem to be solved in the utility model is, in view of the shortcomings of the prior art, providing a kind of solid state hard disc.
In order to solve the above technical problems, the technical scheme that the utility model is used is：A kind of solid state hard disc, including it is multiple
NAND FLASH and solid-state hard disk controller；The solid-state hard disk controller includes status register；The multiple NAND
FLASH free/busy signal pins access the status register by monitoring pin.
Compared with prior art, the utility model have the advantage that for：The utility model need to only define one and draw
Pin is monitored, and when all NAND FLASH are idle condition, NAND FLASH can be directly judged for idle condition, without spending
Solid-state hard disk controller passes through the time spent by command access NAND FLASH each logic unit；Only increase a core
Piece pin, does not influence on chip volume and manufacturing cost.
Brief description of the drawings
Fig. 1 is the utility model embodiment circuit block diagram；
Fig. 2 is the process chart of the utility model embodiment 1.
Fig. 3 is the process chart of the utility model embodiment 2.
Embodiment
Directly it is connected as shown in figure 1, solid-state hard disk controller defines one with solid-state controller internal status register
Hardware pin（Monitor pin）, this hardware pin can be universal input output pin (GPIO) or special FLASH
State-detection pin（READY/BUSY INPUT）, the state of hardware pin will be embodied directly in shape inside solid-state hard disk controller
In state register；By the READY/BUSY of all NAND FLASH chips in solid state hard disc（Free/busy）Signal pins are connected to
Together, and it is connected to above-mentioned hardware pin.
Embodiment 1
Fig. 2 shows to operate the flow chart of the method for stand-by period totally according to the reduction solid state hard disc of embodiment 1.Such as Fig. 2
Shown, when external power source closes solid state hard disc power down, solid state hard disc uses standby electric module for power supply, and solid-state hard disk controller starts
Power down flow：
On the one hand, solid-state hard disk controller reads the state that internal status register learns all NAND FLASH chips,
When it is busy to detect all NAND FLASH states, circulation continuous is detected this status register by solid-state hard disk controller；
It it is the free time when detecting all NAND FLASH states, controller will write reflecting for solid state hard disc into FLASH
It is data cached in firing table and not yet write-in FLASH；
On the other hand, solid-state hard disk controller accesses all NAND FLASH each logic list by way of repeating query
Member, until having, enough logic units can be used for depositing data cached to be idle, and the READY/BUSY of controller（Idle/
It is busy）It is that storage controller will write the mapping item of solid state hard disc into FLASH and not yet write that state, which is posted and remained as busy,
Enter data cached in FLASH.
Controller directly accesses internal register and only needs to several clock cycle, it is only necessary to which nanosecond can be completed to all
NAND FLASH states are idle monitoring.And the conditional access that solid-state hard disk controller completes all logic units needs at least
Hundreds of microseconds, in addition Millisecond time.The method is by significantly reduction solid state hard disc in the wait before write-in is data cached
Between.
Embodiment 2
Fig. 3 shows to operate the flow chart of the method for stand-by period totally according to the reduction solid state hard disc of embodiment 2.Such as Fig. 3
It is shown, when main frame, which is issued, carries out overall erasing operation to solid state hard disc：
Solid-state hard disk controller reads internal status register and learns the states of all NAND FLASH chips, when detecting
When all NAND FLASH states are busy, circulation continuous is detected this status register by solid-state hard disk controller；
It it is the free time when detecting all NAND FLASH states, controller will be to all NAND FLASH logic units
Carry out erasing operation.
For the solid state hard disc with multiple NAND FLASH chips, it will there is tens logic units.Such as：64G MCL
FLASH, which amounts to, 4 logic units, and 512G solid state hard disc needs 8 64G FLASH chip, and solid state hard disc, which amounts to, to be had
32 logic units.The conditional access that solid-state hard disk controller completes all logic units needs at least hundreds of microseconds, such as runs into
When thering is the logic unit to be wiped or be written to the slower page of programming time（page）, the spent time be up to milli
Second level.And controller directly accesses internal register and only needs to several clock cycle, it is only necessary to which nanosecond can be completed to all
NAND FLASH states are idle monitoring.Before the method will significantly reduce solid state hard disc to overall all logic unit operations
Stand-by period.
Claims (3)
1. a kind of solid state hard disc, including multiple NAND FLASH and solid-state hard disk controller；The solid-state hard disk controller includes
Status register；Characterized in that, the multiple NAND FLASH free/busy signal pins are accessed by monitoring pin
The status register.
2. solid state hard disc according to claim 1, it is characterised in that the monitoring pin is input and output pin.
3. solid state hard disc according to claim 1, it is characterised in that the monitoring pin is FLASH state-detection pins.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620656466.1U CN206331414U (en) | 2016-06-29 | 2016-06-29 | A kind of solid state hard disc |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620656466.1U CN206331414U (en) | 2016-06-29 | 2016-06-29 | A kind of solid state hard disc |
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| Publication Number | Publication Date |
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| CN206331414U true CN206331414U (en) | 2017-07-14 |
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| CN201620656466.1U Active CN206331414U (en) | 2016-06-29 | 2016-06-29 | A kind of solid state hard disc |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020015136A1 (en) * | 2018-07-20 | 2020-01-23 | 江苏华存电子科技有限公司 | Method for increasing reaction rate employing flash memory pins |
| CN110874333A (en) * | 2018-08-31 | 2020-03-10 | 威刚科技股份有限公司 | Storage device and storage method |
| CN111176563A (en) * | 2019-12-24 | 2020-05-19 | 湖南国科微电子股份有限公司 | Method for bypass access to storage data, storage device and bypass access storage system |
-
2016
- 2016-06-29 CN CN201620656466.1U patent/CN206331414U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020015136A1 (en) * | 2018-07-20 | 2020-01-23 | 江苏华存电子科技有限公司 | Method for increasing reaction rate employing flash memory pins |
| CN110874333A (en) * | 2018-08-31 | 2020-03-10 | 威刚科技股份有限公司 | Storage device and storage method |
| CN111176563A (en) * | 2019-12-24 | 2020-05-19 | 湖南国科微电子股份有限公司 | Method for bypass access to storage data, storage device and bypass access storage system |
| CN111176563B (en) * | 2019-12-24 | 2023-10-31 | 湖南国科微电子股份有限公司 | Method for bypass access to storage data, storage device and bypass access storage system |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Jiangsu Xinsheng Intelligent Technology Co., Ltd. Assignor: GOKE MICROELECTRONICS CO., LTD. Contract record no.: 2018430000021 Denomination of utility model: Data access method for solid state disk Granted publication date: 20170714 License type: Common License Record date: 20181203 |
|
| EE01 | Entry into force of recordation of patent licensing contract |