CN207281748U - A kind of processor chips emulator - Google Patents

Abstract

The utility model discloses a kind of processor chips emulator, including：Reset detection module, management module, emulation chip and XRAM memories；There is randomizer in management module；Emulation chip is connected by normal data/address bus with XRAM memories and management module；Reset detection module is connected by reseting signal line with management module and emulation chip.The utility model energy real simulation re-powers the function that rear product chips XRAM modules are changed into random number, and in terms of personal code work debugging and test angle, it is zero to reset to XRAM data to be changed into taking for random number, and performance is also consistent with product chips.

Description

A kind of processor chips emulator

Technical field

It the utility model is related to a kind of processor chips emulator.

Background technology

There is the user program of User Exploitation in processor chips, in the writing and debug of user program, used work Tool is usually emulator.Using the emulation chip for including product treatment device chip various functions in emulator, for analog equipment The work behavior of processor chips, emulation chip and the other components of emulator (program storage, the storage number of storage user program According to data storage, and Integrated Development Environment on user computer etc.) coordinate the simulation run of realizing user program and each Item debugging function.

Processor chips generally all containing XRAM (on-chip expanded RAM, external random access memory) in piece, are made To store the data storage of data, available for data storage, caching, and parameter transmission etc..XRAM is in physical characteristic The characteristic random with value is powered on, that is to say, that after chip re-powers every time, data are all random values in XRAM.This is special Property need when being processor chips Code Design to pay close attention to and consider, for example, needing design initialization XRAM data to delay in code Deposit area, prevent data buffer zone no initializtion with regard to code segment of reading of content etc., so being also required to equivalent in design of Simulator Realize this function, such code segment is debugged and tested in exploitation code for user.

In existing design of Simulator, with emulation chip substitute products chip, contained in emulation chip and product chips The basically identical XRAM modules of function, performance, XRAM data when emulator powers in emulation chip are random values, with product core Piece is consistent.But emulator also needs to the process of analog equipment chip power-on and power-off repeatedly, and when generally considering system initialization Between, factor, the emulator complete machine such as stability and service life will not make repeatedly power-on and power-off again, but from the upper of periphery Lower electrical equivalent is a reset signal, specifically, the electricity/when re-powering exactly under generation, the overall not lower electricity/weight of emulator Newly power on, but detect lower electricity/behavior for re-powering, produce the signal of an into/out reset to emulation chip, control The into/out reset state of emulation chip processed.After exiting reset, program pointer, register value in emulation chip, memory value The state after the power is turned on of original state, functionally equivalent actual product chip after the power is turned on is returned to Deng needs.Also wrap among these The XRAM regions in emulation chip are included, the data after generation is powered on again in XRAM regions need all to become random value.It is existing The way of emulator is that the XRAM in emulation chip is equivalent to dual port RAM, is detecting the signal that exits reset, re-power Afterwards, emulator produces one group of random number, and gets around chip processor and perform one to the XRAM regions of emulation chip from back channel All over full sheet write-in random number operation, after functionally equivalent product chips re-power, all become random value in XRAM Characteristic.

But data in rear XRAM are re-powered in actual product chip and become the physical characteristic decision that random number is XRAM , all it is random number from re-powering to XRAM data, centre is without additionally time-consuming.It is such in existing emulator to do Method, although functionally it is equivalent go out XRAM re-power the function that rear data are changed into random value because there are a production Raw one group of random number, and the process of random number is re-write by back channel to full XRAM, this process have it is certain time-consuming, Generally having tens to hundreds of Microsecond grades, (based on delay is write routine XRAM 5-20 nanoseconds, XRAM10-100K byte-sizeds, are imitated True device is write with 60-100M speed), if the amount of capacity of XRAM is larger in processor chip configuration, XRAM write-in time delay Larger, emulator write-in XRAM service speed is relatively low, this takes can also increase therewith, cause emulator and actual product core Notable difference of the piece in upper electrical property, is unfavorable for the debugging and test of personal code work.Meanwhile dual port RAM structure is complex, There are two groups of passages to be written and read operation to XRAM, also reduce the reliability of system.

Utility model content

The technical problem to be solved by the present invention is to provide a kind of processor chips emulator, can real simulation again on Product chips XRAM modules are changed into the function of random number after electricity, in terms of personal code work debugging and test angle, reset to XRAM numbers It is zero according to taking for random number is changed into, performance is also consistent with product chips.

In order to solve the above technical problems, the processor chips emulator of the utility model, including：Reset detection module, pipe Manage module, emulation chip and XRAM memories；There is randomizer in the management module；The emulation chip passes through mark Quasi- data/address bus is connected with XRAM memories and management module；The reset detection module by reseting signal line with Management module is connected with emulation chip.

Using the utility model emulator can real simulation re-power rear product chips XRAM modules and be changed into random Several functions, meanwhile, it can also be directed to personal code work and debug and test, equivalent simulation goes out to reset to XRAM data and is changed into random number consumption When be zero performance, the real simulation function and performance of product chips, ensures that user debugs on emulator, tests code Authenticity and reliability, meanwhile, simplify system (i.e. XRAM memories) and realize structure, improve system reliability, contribute to Code development efficiency is improved, finds all hiding and performance-relevant problems.

Brief description of the drawings

The utility model is described in further detail with reference to the accompanying drawings and detailed description：

Fig. 1 is the structure diagram of the processor chips emulator.

Embodiment

As shown in Figure 1, the processor chips emulator 1 (i.e. emulator in Fig. 1), including：Reset detection module 2, Management module 3, emulation chip 4 and XRAM memories 5.There is randomizer 6 in the management module 3.The emulation core Piece 4 is connected by normal data/address bus 8 with XRAM memories 5, and the normal data/address bus 8 draws XRAM at the same time Memory 5, and be connected with management module 3.The reset detection module 2 is connected by reseting signal line 7 with management module 3, institute State reseting signal line 7 while draw reset detection module 2, and be connected with emulation chip 4.

The reset detection module 2 can monitor external drive environment in real time, judge whether to be in power-down state.If it is in Power-down state, then export effective reset signal, such as " 0 " by the reseting signal line 7 to management module 3 and emulation chip 4 Level signal；If being not at power-down state, nothing is exported to management module 3 and emulation chip 4 by the reseting signal line 7 Imitate reset signal, such as level"1" signal.For example, the processor chips powered using wireless carrier, the reset detection module 2 detection externally fed situations, carrier field is powerful then to be judged to be not at power-down state in power supply field strength requirements；Carrier wave field strength, which is less than, to be supplied Electric field strong demand, then judge to enter power-down state.

The emulation chip 4 by reseting signal line 7 when obtaining effective reset signal, in reset state, it is impossible to logical Cross the normal data/address bus 8 and read and write data from XRAM memories 5；The emulation chip 4 is passing through reseting signal line 7 When obtaining invalid reset signal, reset state is not at, can be total by the normal data/address in normal operating conditions Line 8 reads and writes data from XRAM memories 5.In this way, product treatment device chip not work when in power-down state with regard to real simulation Make, it is impossible to read and write XRAM；During in normal operating conditions, the function of XRAM can be read and write.

The management module 3 can control randomizer 6 therein to produce random number, be used for management module 3.It is described Management module 3 when obtaining effective reset signal by reseting signal line 7, can by the normal data/address bus 8 to XRAM memories 5 write data；The management module 3 by reseting signal line 7 when obtaining invalid reset signal, it is impossible to passes through Normal data/the address bus 8 reads and writes data to XRAM memories 5.In this way, when reset signal is invalid, it is necessary to emulation chip 4 During in normal operating conditions, only emulation chip 4 can operate XRAM memories 5, pipe by normal data/address bus 8 Reason module 3 cannot operate XRAM memories 5；When reset signal is effective, and emulation chip 4 is in reset state, mould is only managed Block 3 can operate XRAM memories 5 by normal data/address bus 8, and emulation chip 4 cannot operate XRAM memories 5.Very XRAM cannot be operated when resetting by simulating product chips in fact, while can operating the function of XRAM in normal work, Ensure that to be not in management module 3 and emulation chip 4 while the situation for operating XRAM memories 5, it is not necessary to use dual port RAM Structure carrys out equivalent XRAM memories 5, it is nonetheless possible to use single port RAM makees XRAM memories, and few one group of operate interface is improved and ensured The stability of system.

The management module 3 can be detected by the reset signal that reseting signal line 7 inputs from effectively to invalid change Change with from invalid to effective.The management module 3 detect reset signal from it is invalid become effective when, control random number Generator 6 produces one group of random number, and normal data/address bus 8 by being connected with XRAM memories 5 is to XRAM memories 5 region-wide write-in random number.In this way, emulator 1 after reset state is entered, begins to produce one group of random number, and write The region-wide of XRAM memories 5 is arrived.It is tens to hundreds of Microsecond grades that this, which produces random number to take with the process write, and It make use of emulation chip 4 to be in the time of reset state, rather than reset state exited into after working status in emulation chip 4 Just start to produce random number and write-in.In the case of lower electricity a period of time will re-power people again in order to control, emulation chip 4 is in The time of reset state is at least second level, completes enough to the region-wide filling random number of XRAM memories 5；Even for software Or the power-on and power-off situation of system control, also due to capacitance characteristic in processor chips exists, it is necessary to capacitance is substantially discharged, ensure The true power down of chip and reset, the time requirement of the effectively lower electricity provided to external environment condition, which is also that Millisecond is other, (to be allowed exterior The minimum effectively lower electric time that environment provides), generally at least require as a few tens of milliseconds, it is random much larger than being produced in emulator 1 Count and write tens to hundreds of microseconds needed for full XRAM memory areas.In this way, in practical situations, present invention institute is real The emulation chip 4 of existing emulator 1 is re-powered into after normal operating conditions, from XRAM memories in terms of personal code work angle Through all becoming random number, take as 0, it is completely the same with the function and performance of actual products chip.

The emulation chip 4 can use FPGA (Field Programmable Gate Array, that is, field programmable gate Array) chip realization；The reset detection module 2 can add power supply detection sensor to realize using general processor chip；Institute Stating management module 3 can use general processor chip to realize, randomizer 6 therein can use scm software side Formula is realized；XRAM memories 5 can use the ram in slice memory resource in single single port XRAM chips or fpga chip It is equivalent to single port XRAM realizations.

The utility model is described in detail above by embodiment, but these are not formed to this reality With new limitation.In the case where not departing from the utility model principle, those skilled in the art can also make many deformations And improvement, these also should be regarded as the scope of protection of the utility model.

Claims (4)

1. A kind of 1. processor chips emulator, it is characterised in that including：Reset detection module, management module, emulation chip and XRAM memories；There is randomizer in the management module；The emulation chip by normal data/address bus with XRAM memories are connected with management module；The reset detection module passes through reseting signal line and management module and emulation chip It is connected.
2. 2. emulator as claimed in claim 1, it is characterised in that：The XRAM memories are made of single port RAM.
3. 3. emulator as claimed in claim 1, it is characterised in that：The emulation chip is made of fpga chip.
4. 4. emulator as claimed in claim 1, it is characterised in that：The reset detection module adds confession by general processor chip Electro-detection sensor is formed；The management module is made of general processor chip.