CN103246584B - Chip structure of system-on-chip and method for storing debug information - Google Patents
Chip structure of system-on-chip and method for storing debug information Download PDFInfo
- Publication number
- CN103246584B CN103246584B CN201210032741.9A CN201210032741A CN103246584B CN 103246584 B CN103246584 B CN 103246584B CN 201210032741 A CN201210032741 A CN 201210032741A CN 103246584 B CN103246584 B CN 103246584B
- Authority
- CN
- China
- Prior art keywords
- chip
- unit
- debugging
- processing unit
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000012545 processing Methods 0.000 claims abstract description 49
- 238000003860 storage Methods 0.000 claims description 23
- 238000004321 preservation Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 3
- 230000006399 behavior Effects 0.000 claims description 2
- 238000009826 distribution Methods 0.000 claims description 2
- 230000008859 change Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000005055 memory storage Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000012356 Product development Methods 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
Abstract
The invention provides a chip structure of a system-on-chip and a method for storing debug information. The method for storing the debug information includes: firstly, appointing parts of subunits in a storing unit comprised by the chip structure of the system-on-chip to store the debug information; secondly, recording the debug information of the own chip structure of the system-on-chip by a recording unit in the chip structure of the system-on-chip when a processing unit of the chip structure of the system-on-chip executes debug operation; and finally, writing the debug information recorded by the recoding unit into the parts of the subunits by a reading unit of the chip structure of the system-on-chip when the processing unit does not read or write the storing unit. The chip structure of the system-on-chip and the method for storing the debug information have the advantages that no single storer for storing the debug information exists in a storer, and no pin connected with external storer is arranged, so that area of the chip can be effectively saved, and cost can be reduced.
Description
Technical field
The present invention relates to a kind of integrated circuit fields, more particularly to a kind of chip structure of system-on-chip and preservation debugging letter
The method of breath.
Background technology
On-chip system chip (i.e. SoC chip) is that one kind comprises the System on Chip/SoC such as processor or DSP, memorizer, and outside can
To be programmed this System on Chip/SoC to realize complication system function.Produce because SoC can be effectively reduced electronics/information system
The development cost of product, shortens the construction cycle, improves the competitiveness of product, and therefore it is progressively become the main of industrial quarters employing
Product development mode.
In order to ensure the quality of SoC chip, generally, research staff or chip production business need to oneself design or produce
The circuit that SoC chip is comprised is debugged, and the such as bus being obtained is read and write data, chip internal state, and program changes
The Debugging message such as the jump address of variable flow, to be supplied to commissioning staff by external emulator etc., so that analysis is used.
Present debugging technique mainly has two kinds：A kind of is to arrange independent memory element in SoC chip, by chip
Debugging module the Debugging message of the chip being gathered is write this independent memory element；Another kind is to use external storage
The Debugging message of the chip being gathered is write this external memory storage by the debugging module in chip by device.However, existing this two
In the mode of kind, former mode can take a large amount of chip areas, increases production cost, and latter approach can additionally increase chip and draw
Foot quantity, and debugging speed also can be restricted.
Therefore, pole is necessary the debugging technique of existing SoC chip is improved.
Content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide on a kind of little piece of chip area be
System chip structure.
Another object of the present invention is to providing a kind of method preserving Debugging message, so as not to need single memorizer
To store Debugging message.
For achieving the above object and other related purposes, the chip structure of system-on-chip that the present invention provides, it at least includes：
Processing unit；The memory element being connected with described processing unit；For recording the recording unit of Debugging message；And deposit with described
The read-write cell that storage unit and recording unit are connected, for not reading or writing to described memory element when described processing unit
During operation, Debugging message that described recording unit is recorded writes in the pre- stator unit of described memory element or will be described pre-
Debugging message in stator unit reads.
Preferably, described recording unit also includes：First signal output apparatus, it is used for the recording unit belonging to when itself
The temporary storage location being comprised has been filled with output first during Debugging message and has informed signal to read-write cell.
Preferably, described read-write cell also includes：Secondary signal output circuit, it is used for output second and informs signal to institute
State processing unit, to make described processing unit suspend carry out read or write to described memory element.
The method of the preservation Debugging message that the present invention provides, for aforesaid chip structure of system-on-chip, it includes following
Step：
In-system chip structure comprises on said sheets memory element, specified portions subelement is used for storage debugging letter
Breath；
- on said sheets during the processing unit execution Task of Debugging in system chip structure, described SOC(system on a chip)
The Debugging message of the affiliated chip structure of system-on-chip of the recording unit records in chip structure itself；And
Read-write cell in-described chip structure of system-on-chip is not read to described memory element in described processing unit
Or during write operation, the Debugging message that described recording unit is recorded writes described part subelement.
Preferably, the described method preserving Debugging message also includes the temporary storage location that described recording unit comprises and has been filled with tune
During examination information, output first informs signal to the step of read-write cell.
Preferably, the described method preserving Debugging message also includes described read-write cell output second and informs signal to described
Processing unit, so that the step that described processing unit time-out carries out read or write to described memory element.
As described above, the chip structure of system-on-chip of the present invention and the method preserving Debugging message, there is following beneficial effect
Really：Single memorizer is not had to store Debugging message in chip, thus can be with effectively save chip area, reduces cost；This
Outward, chip is also not provided with the pin being connected with external memory storage, therefore effectively reduces the pin number of chip, and then reduces core
The preparation cost of piece.
Brief description
Fig. 1 is shown as the structural representation of the chip structure of system-on-chip of the present invention.
Fig. 2 is shown as a kind of preferred structure schematic diagram of the chip structure of system-on-chip of the present invention.
Fig. 3 is shown as another kind of preferred structure schematic diagram of the chip structure of system-on-chip of the present invention.
The flow chart that Fig. 4 is shown as the method for preservation Debugging message of the present invention.
Component label instructions
1 chip structure of system-on-chip
11 processing units
12 memory element
13 recording units
131 first signal output apparatus
14 read-write cells
141 secondary signal output circuits
Specific embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also be by addition different concrete realities
The mode of applying is carried out or applies, and the every details in this specification can also be based on different viewpoints and application, without departing from
Carry out various modifications and changes under the spirit of the present invention.
Refer to Fig. 1 to Fig. 4.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only shows the assembly relevant with the present invention rather than then according to package count during actual enforcement in schema
Mesh, shape and size are drawn, and during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its
Assembly layout kenel is likely to increasingly complex.
As illustrated, the present invention provides a kind of chip structure of system-on-chip, described chip structure of system-on-chip 1 is at least wrapped
Include：Processing unit 11, memory element 12, recording unit 13 and read-write cell 14.
Described processing unit 11 is based on SOC(system on a chip) as the core cell of on-chip system chip, the circuit structure that it comprises
Chip function to be done determining it is preferable that it includes comprising the circuit unit of processor, for example, comprise CPU, MCU,
The circuit unit of one or more of DSP.
In more detail speech, for example, described processing unit 11 include one or more of CPU, MCU, DSP, clock circuit,
Intervalometer, interrupt control unit, serial-parallel interface, other ancillary equipment, I/O port and the bonding being used between various IP kernels are patrolled
Volume etc..
Described memory element 12 is connected with described processing unit 11, for storage information.Preferably, described processing unit
11 carry out read or write by bus to described memory element 12.Preferably, described memory element 12 include various volatile,
The memorizeies such as non-volatile or Cache.
Described recording unit 13 is used for recording Debugging message.Wherein, described Debugging message is included to described SOC(system on a chip)
Chip structure 1 carries out various data messages produced by its internal circuit during Task of Debugging it is preferable that including but is not limited to：Always
The data of line read-write, chip internal status information, jump address of routine change flow process etc..
Preferably, described recording unit 13 includes temporary storage location, described temporary storage location can using volatile, non-volatile or
The memorizeies such as Cache, to realize, may also be employed depositor etc. to realize.
It should be noted that in order to reduce chip area, the memory capacity of the temporary storage location that described recording unit 13 comprises
As little as possible, preferably 8 to 16 bytes etc..
Described read-write cell 14 is connected with described memory element 12 and recording unit 13, for when described processing unit 11
When read or write not being carried out to described memory element 12, deposit described in Debugging message write that described recording unit 13 is recorded
In the pre- stator unit of storage unit 13.
Wherein, described pre- stator unit is the preassigned subelement for storing Debugging message it is preferable that it is even
Continuous unit, for example, the memory element of address " 1234 " to address " 3FFF " in described memory element 12 is used for storage debugging letter
Breath.
Specifically, described read-write cell 14 passes through to monitor the reading between described processing unit 11 and described memory element 12
According to line and write data line, all whether the free time determines whether described processing unit 11 is reading or writing to described memory element 12
Operation, and when when described processing unit 11 does not carry out read or write to described memory element 12, by described recording unit 13
The Debugging message being recorded writes in the pre- stator unit of described memory element 13.
Those skilled in the art, therefore be will not be described in detail herein it should be appreciated that the circuit structure of read-write cell based on preceding description.
A kind of preferred as the present invention, aforementioned recording unit 13 includes the first signal output apparatus 131, as shown in Figure 2.
The temporary storage location that described first signal output apparatus 131 are comprised for the recording unit 13 belonging to when itself is deposited
During full Debugging message, output first informs signal to read-write cell 14, so that described read-write cell 14 is in time by described temporary storage location
The Debugging message being stored writes in the pre- stator unit of described memory element 12.
Wherein, first inform that signal includes any one and can be shown that the temporary storage location that recording unit 13 is comprised has been filled with tune
The signal of examination information is it is preferable that include but is not limited to：Low level signal, high level signal etc..
Specifically, described first signal output apparatus 131 can byte number based on Debugging message to be recorded or address letter
Breath and the byte number of described temporary storage location or maximum address information relatively to export the first notification.Preferably, described
One signal output apparatus 131 can adopt comparison circuit etc. to realize.
A kind of preferred as the present invention, aforementioned read-write cell 14 also includes secondary signal output circuit 141, as Fig. 3 institute
Show.
Described secondary signal output circuit 141 is used for output second and informs signal to described processing unit 11, to make institute
State processing unit 11 and suspend and read or write is carried out to described memory element 12, be thus easy to described read-write 14 and Debugging message is write
Enter in the pre- stator unit of described memory element 12.
Wherein, second inform that signal includes any one described processing unit 11 can be made to suspend described memory element 12 is entered
The signal of row read or write is it is preferable that include but is not limited to：Low level signal, high level signal etc..
Specifically, inform letter when described read-write cell 14 receives from the first of the first signal output apparatus 131 output
Number or because other reasonses etc., described read-write cell 14 needs the Debugging message being recorded described recording unit 13 to write institute
State memory element 12 pre- stator unit when, if described processing unit 11 carries out reading or writing behaviour to described memory element 12
Make, then described secondary signal output circuit 141 exports the second of a high level etc. and informs signal to described processing unit 11,
So that described processing unit 11 suspends the read or write to described memory element 12.
, based on preceding description it should be appreciated that the circuit structure of the first signal output apparatus, therefore here is or not those skilled in the art
Describe in detail again.
In addition it is also necessary to explanation, described chip structure of system-on-chip 1 be also based on user need comprise other work(
Energy modular unit, it may for example comprise the analog front-end module of ADC/DAC, power supply provide and power managed module, radio-frequency front-end mould
Block, user define logic and microelectron-mechanical module etc., and here no longer describes in detail one by one.
Based on any one chip structure of system-on-chip 1 of aforementioned Fig. 1 to Fig. 3, the present invention provides a kind of preservation Debugging message
Method, as shown in Figure 4.
In step sl, in the memory element 12 that aforementioned chip structure of system-on-chip 1 comprises, specified portions subelement is used
In storage Debugging message.
Specifically, in the debugging stage, in described memory element 12, first distribute a subelement as debugging internal memory, for protecting
Deposit Debugging message, in described memory element 12, as shared drive, now described is above the unit in addition to debugging internal memory
The processing unit 11 that system chip structure 1 comprises or other functions module will avoid using debugging internal memory, and can be processed list by described
In the enable signal of shared drive and debugging that other functions module in first 11 or described chip structure of system-on-chip 1 is used
The initial address depositing distribution can be saved in the depositor of recording unit 14.
In step s 2, on said sheets during the processing unit 11 execution Task of Debugging in system chip structure 1,
Recording unit 14 in described chip structure of system-on-chip records the Debugging message of itself affiliated chip structure of system-on-chip 1.
Wherein, the Task of Debugging of described processing unit 11 execution is known to those skilled in the art knows, therefore here is no longer
Describe in detail.
Specifically, on said sheets during the processing unit 11 execution Task of Debugging in system chip structure 1, described
Recording unit 14 records the connecting line of the described memory element 12 of connection in described chip structure of system-on-chip 1 (as read/write is total
Line) read-write data, internal state data of chip, processing unit 11 change the data such as jump address during task.
In step s3, the read-write cell 14 in described chip structure of system-on-chip 1 in described processing unit 11 not to institute
When stating memory element and carrying out read or write, the Debugging message that described recording unit 13 is recorded writes described part subelement
(debugging internal memory).
Specifically, described read-write cell 14 detects the read/write between described processing unit 11 and described memory element 12
When data wire is idle, in the Debugging message write debugging internal memory that described recording unit 13 is recorded.
If the read/write data line between described processing unit 11 and described memory element 12 is busy, lead to described record
The temporary storage location that unit 13 is comprised has been filled with Debugging message, then the first signal output apparatus that described recording unit 13 is comprised
131 outputs first inform signal to described read-write cell 14, so that described read-write cell 14 is in time by described recording unit 13 institute
In the Debugging message write debugging internal memory of record.
Additionally, when described read-write cell 14 prepares to described memory element 12 write Debugging message, if described process list
Unit 11 is carrying out read or write to described memory element 12, then the secondary signal output circuit that described read-write cell 14 comprises
141 outputs second inform signal to described processing unit 11, so as described processing unit 11 discharge the reading of described memory element 12/
Write data line, subsequently, described read-write cell 14 can utilize the read/write data bundle of lines Debugging message of described memory element 12 to move
To in debugging internal memory, then described processing unit 11 recovers normal work again.
Further, after debugging storage Debugging message in internal memory, can be read described by outside on-line debugging emulator
Debugging message in debugging internal memory, and this Debugging message is analyzed.
In sum, the chip structure of system-on-chip of the present invention and preserve Debugging message method be based on read-write cell can be by
The Debugging message write storage unit (i.e. in Installed System Memory) that recording unit is recorded, due to not having single memorizer in chip
To store Debugging message, therefore can be with effectively save chip area, reduces cost；Additionally, chip is also not provided with and external storage
The pin that device connects, therefore effectively reduce the pin number of chip, and then reduce the preparation cost of chip.So, the present invention has
Effect overcomes various shortcoming of the prior art and has high industrial utilization.
Above-described embodiment only principle of the illustrative present invention and its effect, not for the restriction present invention.Any ripe
The personage knowing this technology all can carry out modifications and changes without prejudice under the spirit and the scope of the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete with institute under technological thought without departing from disclosed spirit such as
All equivalent modifications becoming or change, must be covered by the claim of the present invention.
Claims (9)
1. a kind of chip structure of system-on-chip is it is characterised in that described chip structure of system-on-chip at least includes：
Processing unit；
The memory element being connected with described processing unit；In described memory element, distribution one pre- stator unit is as in debugging
Deposit, for preserving Debugging message；In described memory element, the unit in addition to debugging internal memory is as shared drive；
For recording the recording unit of Debugging message；The debugging of the affiliated chip structure of system-on-chip of described recording unit records itself
Information；
The read-write cell being connected with described memory element and recording unit, for when described processing unit is to described storage list
When unit carries out read or write, the Debugging message that described recording unit is recorded writes the pre- stator unit of described memory element
In.
2. chip structure of system-on-chip according to claim 1 is it is characterised in that described recording unit also includes：
First signal output apparatus, when the temporary storage location being comprised for the recording unit belonging to itself is filled with Debugging message
Output first informs signal to read-write cell.
3. chip structure of system-on-chip according to claim 1 is it is characterised in that described read-write cell also includes：
Secondary signal output circuit, informs signal to described processing unit for output second, to make described processing unit temporary
Stop carrying out read or write to described memory element.
4. chip structure of system-on-chip according to claim 1 it is characterised in that：Described processing unit includes comprising to process
The circuit unit of device.
5. chip structure of system-on-chip according to claim 4 it is characterised in that：Described processing unit include CPU, MCU,
One or more of DSP.
6. a kind of method preserving Debugging message, for the chip structure of system-on-chip described in any one of claim 1 to 5, institute
The method stating preservation Debugging message is characterised by including step：
Distribute a part of subelement in-system chip structure comprises on said sheets memory element as debugging internal memory, be used for
Preserve Debugging message；In described memory element, the unit in addition to debugging internal memory is as shared drive；
- on said sheets during the processing unit execution Task of Debugging in system chip structure, described on-chip system chip
The Debugging message of the affiliated chip structure of system-on-chip of the recording unit records in structure itself；
Read-write cell in-described chip structure of system-on-chip does not read or write to described memory element in described processing unit
During operation, the Debugging message that described recording unit is recorded writes described part subelement.
7. the method preserving Debugging message according to claim 6 is it is characterised in that also include step：Described recording unit
The temporary storage location comprising has been filled with output first during Debugging message and has informed signal to read-write cell.
8. the method preserving Debugging message according to claim 6 is it is characterised in that also include step：Described read-write cell
Output second informs signal to described processing unit, described processing unit suspends to carry out reading or writing behaviour to described memory element
Make.
9. the method preserving Debugging message according to claim 6 is it is characterised in that also include step：By described partly son
Debugging message in unit reads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210032741.9A CN103246584B (en) | 2012-02-14 | 2012-02-14 | Chip structure of system-on-chip and method for storing debug information |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210032741.9A CN103246584B (en) | 2012-02-14 | 2012-02-14 | Chip structure of system-on-chip and method for storing debug information |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103246584A CN103246584A (en) | 2013-08-14 |
| CN103246584B true CN103246584B (en) | 2017-02-22 |
Family
ID=48926114
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210032741.9A Active CN103246584B (en) | 2012-02-14 | 2012-02-14 | Chip structure of system-on-chip and method for storing debug information |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103246584B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160018204A (en) * | 2014-08-08 | 2016-02-17 | 삼성전자주식회사 | Electronic device, On-Chip memory and operating method of the on-chip memory |
| CN109144853B (en) * | 2018-07-26 | 2021-09-24 | 中国电子科技集团公司第五十四研究所 | Software defined radio SoC chip debugging system |
| CN110032482A (en) * | 2019-04-11 | 2019-07-19 | 盛科网络（苏州）有限公司 | Sheet sand covered device and method |
| CN115221070B (en) * | 2022-08-02 | 2023-06-20 | 无锡众星微***技术有限公司 | NVMe disk-based system-on-chip diagnosis method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101261601A (en) * | 2008-04-25 | 2008-09-10 | 浙江大学 | Microprocessor debugging method and microprocessor debugging module |
| CN101458725A (en) * | 2007-12-14 | 2009-06-17 | 上海海尔集成电路有限公司 | Microcontroller chip and debug method thereof |
| CN101769988A (en) * | 2008-12-30 | 2010-07-07 | 易视芯科技(北京)有限公司 | Chip debugging method, system and debugging module |
-
2012
- 2012-02-14 CN CN201210032741.9A patent/CN103246584B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101458725A (en) * | 2007-12-14 | 2009-06-17 | 上海海尔集成电路有限公司 | Microcontroller chip and debug method thereof |
| CN101261601A (en) * | 2008-04-25 | 2008-09-10 | 浙江大学 | Microprocessor debugging method and microprocessor debugging module |
| CN101769988A (en) * | 2008-12-30 | 2010-07-07 | 易视芯科技(北京)有限公司 | Chip debugging method, system and debugging module |
Non-Patent Citations (1)
| Title |
|---|
| 《嵌入式微处理器可测性设计与片上调试技术的研究与实现》;严明;《国防科学技术大学硕士论文库》;20051101;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103246584A (en) | 2013-08-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9910605B2 (en) | Page migration in a hybrid memory device | |
| CN107466418A (en) | The other unit mode nonvolatile memory of cost optimization single-stage for multi-level cell mode non-volatile memory | |
| Guz et al. | Many-core vs. many-thread machines: Stay away from the valley | |
| CN102789439B (en) | The method of the interruption in control data transmission process and memory device | |
| CN102799392B (en) | Memory device and interrupt control method thereof | |
| CN101799744B (en) | Solid-state drive command divides into groups | |
| CN103034454B (en) | Flexible flash command | |
| US10067813B2 (en) | Method of analyzing a fault of an electronic system | |
| CN103246584B (en) | Chip structure of system-on-chip and method for storing debug information | |
| CN105930186B (en) | The method for loading software of multi -CPU and software loading apparatus based on multi -CPU | |
| CN106325758B (en) | A kind of queue storage space management method and device | |
| CN104375895B (en) | For the data storage dispatching method and device between multiple memorizers | |
| CN108710583A (en) | Management method, device, computer equipment and the medium in SSD write buffers area | |
| TW201530170A (en) | On-die logic analyzer for semiconductor die | |
| US20130332933A1 (en) | Performance monitoring resources programmed status | |
| CN107430554A (en) | Storage cache performance is improved as the standard that cache is inserted by using the compressibility of data | |
| CN102597912A (en) | Coordinating device and application break events for platform power saving | |
| US20090187747A1 (en) | System and method for tracing instruction pointers and data access | |
| CN110209357A (en) | Improve method, apparatus, computer equipment and the storage medium of the big file write performance of SSD | |
| CN104409099B (en) | High speed eMMC array control units based on FPGA | |
| TW201303870A (en) | Effective utilization of flash interface | |
| CN207008602U (en) | A kind of storage array control device based on Nand Flash memorizer multichannel | |
| CN208907999U (en) | A kind of novel Raid buckle | |
| CN109491959A (en) | A kind of programmable logic device configurator | |
| CN104460938B (en) | System-wide power conservation method and system using memory cache |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20171102 Address after: 610200 Sichuan Chengdu Shuangliu District Dongsheng Street Chengdu core industrial park concentration area Patentee after: Montage LZ Technologies (Chengdu) Co.,Ltd. Address before: Suzhou City, Jiangsu Province, Suzhou Industrial Park 215123 Xinghu Street No. 328 Creative Industry Park 6-1002 Patentee before: SUZHOU MONTAGE MICROELECTRONIC TECHNOLOGY Co.,Ltd. |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: On Chip System Chip Architecture and Methods for Saving Debugging Information Granted publication date: 20170222 Pledgee: Renlai Electronic Technology (Shanghai) Co.,Ltd. Pledgor: Montage LZ Technologies (Chengdu) Co.,Ltd. Registration number: Y2024980016173 |