JP4958257B2 - マルチチップパッケージ - Google Patents
マルチチップパッケージ Download PDFInfo
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- JP4958257B2 JP4958257B2 JP2006059772A JP2006059772A JP4958257B2 JP 4958257 B2 JP4958257 B2 JP 4958257B2 JP 2006059772 A JP2006059772 A JP 2006059772A JP 2006059772 A JP2006059772 A JP 2006059772A JP 4958257 B2 JP4958257 B2 JP 4958257B2
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- Prior art keywords
- semiconductor chip
- circuit
- chip
- analog circuit
- analog
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/4809—Loop shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06506—Wire or wire-like electrical connections between devices
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10162—Shape being a cuboid with a square active surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
5)となる。スイッチS4がオンする場合には、出力電圧Voutは、Vout=Vin×Rtotal/(R5)となる。このようにスイッチS1、S2、S3、S4のいずれをオンさせるか選択することで、アナログ回路103の回路特性である出力電圧Voutが調整されることになる。
2:デジタル回路
3:アナログ回路
4:不揮発性レジスタ
5:パッド
7:パッド
8:リードフレーム
9:ワイヤ
11、31:半導体チップ(第2の半導体チップ)
12:接着剤
37:パッド
39:ワイヤ
Claims (5)
- モールド樹脂封止されるマルチパッケージであって、
不揮発性レジスタと上記不揮発性レジスタにより特性が調整されるアナログ回路領域とが形成されたアナログ混載型の第1の半導体チップと、
接着剤を介して、前記半導体チップの上記アナログ回路領域上にのみ重畳して局所的に装着される第2の半導体チップと、を有することを特徴とするマルチチップパッケージ。 - 請求項1に記載のマルチチップパッケージにおいて、
上記第2の半導体チップは、ダミーチップであることを特徴とするマルチチップパッケージ。 - 請求項1に記載のマルチチップパッケージにおいて、
上記第2の半導体チップは、その表面上に回路領域が形成されていることを特徴とするマルチチップパッケージ。 - モールド樹脂封止されるマルチチップパッケージであって、
アナログ回路領域が形成されたアナログ混載型の第1の半導体チップと、
接着剤を介して、前記半導体チップの上記アナログ回路領域上にのみ重畳して局所的に装着されるダミーチップである第2の半導体チップと、を有することを特徴とするマルチチップパッケージ。 - 請求項1乃至4のいずれか1項に記載のマルチチップパッケージにおいて、
上記第2の半導体チップは、上記第1の半導体チップと同じ材料組成の基板からなっていることを特徴とするマルチチップパッケージ。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006059772A JP4958257B2 (ja) | 2006-03-06 | 2006-03-06 | マルチチップパッケージ |
CNB2006101727466A CN100479151C (zh) | 2006-03-06 | 2006-12-30 | 多芯片封装体 |
US11/713,798 US7701068B2 (en) | 2006-03-06 | 2007-03-05 | Multi-chip package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006059772A JP4958257B2 (ja) | 2006-03-06 | 2006-03-06 | マルチチップパッケージ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007242705A JP2007242705A (ja) | 2007-09-20 |
JP4958257B2 true JP4958257B2 (ja) | 2012-06-20 |
Family
ID=38478125
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006059772A Expired - Fee Related JP4958257B2 (ja) | 2006-03-06 | 2006-03-06 | マルチチップパッケージ |
Country Status (3)
Country | Link |
---|---|
US (1) | US7701068B2 (ja) |
JP (1) | JP4958257B2 (ja) |
CN (1) | CN100479151C (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8779599B2 (en) * | 2011-11-16 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages including active dies and dummy dies and methods for forming the same |
KR101936355B1 (ko) * | 2012-11-22 | 2019-01-08 | 에스케이하이닉스 주식회사 | 멀티-칩 시스템 및 반도체 패키지 |
US9613931B2 (en) | 2015-04-30 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out stacked system in package (SIP) having dummy dies and methods of making the same |
KR102477352B1 (ko) * | 2017-09-29 | 2022-12-15 | 삼성전자주식회사 | 반도체 패키지 및 이미지 센서 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3175981B2 (ja) * | 1992-10-28 | 2001-06-11 | 株式会社東芝 | トリミング回路 |
JPH08204582A (ja) * | 1995-01-20 | 1996-08-09 | Fujitsu Ltd | 半導体集積回路 |
JP3268740B2 (ja) | 1997-08-20 | 2002-03-25 | 株式会社東芝 | Asicの設計製造方法、スタンダードセル、エンベッテドアレイ、及びマルチ・チップ・パッケージ |
JPH11168185A (ja) * | 1997-12-03 | 1999-06-22 | Rohm Co Ltd | 積層基板体および半導体装置 |
JP3224796B2 (ja) * | 1999-09-20 | 2001-11-05 | ローム株式会社 | 半導体装置 |
JP3831593B2 (ja) | 2000-09-21 | 2006-10-11 | 三洋電機株式会社 | マルチチップモジュール |
JP4243077B2 (ja) * | 2002-07-23 | 2009-03-25 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
JP2004146816A (ja) * | 2002-09-30 | 2004-05-20 | Matsushita Electric Ind Co Ltd | 固体撮像装置およびこれを用いた機器 |
JP4615189B2 (ja) * | 2003-01-29 | 2011-01-19 | シャープ株式会社 | 半導体装置およびインターポーザチップ |
JP3948430B2 (ja) * | 2003-04-03 | 2007-07-25 | ソニー株式会社 | 半導体集積回路の製造方法 |
JP2004363187A (ja) | 2003-06-02 | 2004-12-24 | Denso Corp | 半導体パッケージ |
JP4366472B2 (ja) * | 2003-11-19 | 2009-11-18 | Okiセミコンダクタ株式会社 | 半導体装置 |
KR100843137B1 (ko) * | 2004-12-27 | 2008-07-02 | 삼성전자주식회사 | 반도체 소자 패키지 |
JP2006186375A (ja) * | 2004-12-27 | 2006-07-13 | Samsung Electronics Co Ltd | 半導体素子パッケージ及びその製造方法 |
TWI263314B (en) * | 2005-10-26 | 2006-10-01 | Advanced Semiconductor Eng | Multi-chip package structure |
TWI305410B (en) * | 2005-10-26 | 2009-01-11 | Advanced Semiconductor Eng | Multi-chip package structure |
-
2006
- 2006-03-06 JP JP2006059772A patent/JP4958257B2/ja not_active Expired - Fee Related
- 2006-12-30 CN CNB2006101727466A patent/CN100479151C/zh not_active Expired - Fee Related
-
2007
- 2007-03-05 US US11/713,798 patent/US7701068B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2007242705A (ja) | 2007-09-20 |
US20070210456A1 (en) | 2007-09-13 |
US7701068B2 (en) | 2010-04-20 |
CN101034699A (zh) | 2007-09-12 |
CN100479151C (zh) | 2009-04-15 |
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