CN103025069A - Method for improving outer pattern layer contraposition precision by virtue of exposure PIN pins - Google Patents
Method for improving outer pattern layer contraposition precision by virtue of exposure PIN pins Download PDFInfo
- Publication number
- CN103025069A CN103025069A CN2012104768270A CN201210476827A CN103025069A CN 103025069 A CN103025069 A CN 103025069A CN 2012104768270 A CN2012104768270 A CN 2012104768270A CN 201210476827 A CN201210476827 A CN 201210476827A CN 103025069 A CN103025069 A CN 103025069A
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- China
- Prior art keywords
- exposure
- pin
- circuit board
- nail
- pin nail
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- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a method for improving outer pattern layer contraposition precision by virtue of exposure PIN pins. The method is characterized by comprising the following steps of: respectively drilling 8 exposure PIN pin contraposition holes and a fool-proof hole in an outer exposure film and a circuit board; respectively inserting the positioning PIN pins into upper and lower exposure films and the circuit board, wherein the heads of the PIN pins face the circuit board; and fixing the caps of the positioning PIN pins on the exposure film with adhesive paper. According to the method, the exposure films and the circuit board are directly fixed by a simple auxiliary tool, a novel outer pattern contraposition process and a multi-point positioning manner, so that the relative displacement of the exposure films and the circuit board generated in manual operation and manufacture processes can be avoided, the requirement of a client to outer pattern contraposition precision with high concentration and high precision of +/-1.5mil of an outer circuit pattern can be fulfilled, the contraposition precision can be improved, and the use is simple.
Description
[technical field]
The present invention relates to the method that a kind of using exposure PIN nail improves the outer graphics aligning accuracy.
[background technology]
In the manufacture craft that the circuit board outer graphics shifts, the client is more and more higher to the aligning accuracy requirement of outer graphics, especially for the highly dense circuit board of circuit.Circuit-board industry is emptied the part of four jiaos of the outer exposure films generally by manual clappers, uses the gummed paper film that will expose to be fixed on the circuit board, and adopts specific boring, as the contraposition of outer graphics transfer.But in manufacturing process, be difficult to avoid the exposure film that causes in people's manual manipulation and the exposure vacuum and the off normal between the wiring board, be difficult to satisfy that the client is highly dense for the outer-layer circuit figure, high accuracy+/-the outer graphics alignment precision requirement of 1.5mil.The contraposition deviation that occurs in the outer graphics transfer process can directly cause the figure displacement, and orifice ring is less than normal, even collapses the hole, causes the circuit board short circuit, even can't Assembly part, and quality is brought great hidden danger.
[summary of the invention]
The object of the invention is to overcome the figure off normal defective that existing manual clappers bring, use a kind of simple aid and novel outer graphics alignment method, can satisfy that the client is highly dense for the outer-layer circuit figure, high accuracy+/-the outer graphics alignment precision requirement of 1.5mil, but and the using exposure PIN of Effective Raise aligning accuracy nail improve the method for outer graphics aligning accuracy.
For addressing the above problem, the present invention's design is achieved through the following technical solutions:
Using exposure PIN nail improves the method for outer graphics aligning accuracy, it is characterized in that step is as follows:
Step 1 is bored respectively 8 exposure PIN nail registration holes and 1 fool proof hole on the skin exposure film and wiring board;
Step 2 will be located the PIN nail and be inserted respectively the levels exposure film and wiring board, and the PIN ailhead is towards wiring board.
Step 3 will be located the PIN head of a nail and will be fixed on the exposure film with gummed paper.
Aforesaid using exposure PIN nail improves the method for outer graphics aligning accuracy, and the PIN that it is characterized in that exposing nail registration holes lays respectively on 4 plate angles, and each plate angle is provided with 2 holes, and 2 holes on each plate angle keep level.
Aforesaid using exposure PIN nail improves the method for outer graphics aligning accuracy, it is characterized in that fool proof hole and any one group of PIN nail registration holes are placed on the Ban Jiao position side by side.
Aforesaid using exposure PIN nail improves the method for outer graphics aligning accuracy, it is characterized in that staggering in the position of the location PIN nail insertion of adjacent levels.
The present invention uses a kind of simple aid and novel outer graphics alignment process, adopt multipoint positioning, directly fix the exposure film and wiring board, avoid the exposure film that produces in people's manual manipulation and the manufacturing process and the relative displacement of wiring board, can satisfy that the client is highly dense for the outer-layer circuit figure, high accuracy+/-the outer graphics alignment precision requirement of 1.5mil, and the raising aligning accuracy, use simple.
[embodiment]
Using exposure PIN nail improves the method for outer graphics aligning accuracy, and step is as follows:
Step 1 is bored respectively 8 exposure PIN nail registration holes and 1 fool proof hole on the skin exposure film and wiring board;
Step 2 will be located the PIN nail and be inserted respectively the levels exposure film and wiring board, and the PIN ailhead is towards wiring board.
Step 3 will be located the PIN head of a nail and will be fixed on the exposure film with gummed paper.
Described exposure PIN nail registration holes lays respectively on 4 plate angles, and each plate angle is provided with 2 holes, and 2 holes on each plate angle keep level.Guarantee to locate stressed even.
Described fool proof hole and any one group of PIN nail registration holes are placed on the Ban Jiao position side by side, as hole for subsequent use.
Described exposure PIN nail registration holes and fool proof hole size can be decided according to producing the design of actual needs and circuit board itself.
Exposure PIN nail registration holes center is fixing to plate minor face distance, can suitably adjust to the long back gauge of plate.
Distance between the exposure PIN nail location hole is designed to fixed value by process capability.
Fool proof hole and any one group of exposure PIN nail registration holes are placed on the Ban Jiao position side by side, 8 location PIN nails are inserted in the boring respectively, in order to insert location PIN nail, carry out multiple spot and fix, levels location PIN nail is noted staggered positions, prevents that levels location PIN from following closely mutual jack-up.
Location PIN ailhead is towards wiring board, and the PIN head of a nail is fixed on the exposure film by gummed paper.
Claims (4)
1. using exposure PIN nail improves the method for outer graphics aligning accuracy, it is characterized in that step is as follows:
Step 1 is bored respectively 8 exposure PIN nail registration holes and 1 fool proof hole on the skin exposure film and wiring board;
Step 2 will be located the PIN nail and be inserted respectively the levels exposure film and wiring board, and the PIN ailhead is towards wiring board.
Step 3 will be located the PIN head of a nail and will be fixed on the exposure film with gummed paper.
2. using exposure PIN nail according to claim 1 improves the method for outer graphics aligning accuracy, and the PIN that it is characterized in that exposing nail registration holes lays respectively on 4 plate angles, and each plate angle is provided with 2 holes, and 2 holes on each plate angle keep level.
3. using exposure PIN nail according to claim 1 improves the method for outer graphics aligning accuracy, it is characterized in that fool proof hole and any one group of PIN nail registration holes are placed on the Ban Jiao position side by side.
4. using exposure PIN nail according to claim 1 improves the method for outer graphics aligning accuracy, it is characterized in that staggering in the position of the location PIN nail insertion of adjacent levels.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012104768270A CN103025069A (en) | 2012-11-21 | 2012-11-21 | Method for improving outer pattern layer contraposition precision by virtue of exposure PIN pins |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012104768270A CN103025069A (en) | 2012-11-21 | 2012-11-21 | Method for improving outer pattern layer contraposition precision by virtue of exposure PIN pins |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103025069A true CN103025069A (en) | 2013-04-03 |
Family
ID=47973039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012104768270A Pending CN103025069A (en) | 2012-11-21 | 2012-11-21 | Method for improving outer pattern layer contraposition precision by virtue of exposure PIN pins |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103025069A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103345132A (en) * | 2013-06-25 | 2013-10-09 | 惠州中京电子科技股份有限公司 | Method for aligning outer layer film PIN nails |
| CN105792529A (en) * | 2016-04-08 | 2016-07-20 | 梅州市中联精密电子有限公司 | Loose-leaf type circuit board Pin nail counterpoint technology |
| CN109587950A (en) * | 2018-11-28 | 2019-04-05 | 惠州中京电子科技有限公司 | A kind of low error PCB sawing sheet drillhole pattern localization method |
Citations (7)
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|---|---|---|---|---|
| JP2001094229A (en) * | 1999-09-27 | 2001-04-06 | Matsushita Electric Works Ltd | Method of manufacturing circuit board and mask film attachment hole drilling apparatus |
| JP2008053524A (en) * | 2006-08-25 | 2008-03-06 | Calsonic Kansei Corp | Apparatus for manufacturing circuit board |
| CN201245260Y (en) * | 2008-06-25 | 2009-05-27 | 瑞之路(厦门)眼镜科技有限公司 | Packing box for lens |
| CN101598901A (en) * | 2009-07-14 | 2009-12-09 | 昆山鼎鑫电子有限公司 | A kind of operational method of manual exposure machine |
| CN101772268A (en) * | 2009-12-22 | 2010-07-07 | 深圳市集锦线路板科技有限公司 | Technology for aligning circuit board by PIN nail |
| CN201742639U (en) * | 2010-08-06 | 2011-02-09 | 深圳崇达多层线路板有限公司 | Circuit board positioning device |
| CN101969746A (en) * | 2010-11-04 | 2011-02-09 | 沪士电子股份有限公司 | Method for removing electroplating copper locally in hollowed-out area of printed circuit board |
-
2012
- 2012-11-21 CN CN2012104768270A patent/CN103025069A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001094229A (en) * | 1999-09-27 | 2001-04-06 | Matsushita Electric Works Ltd | Method of manufacturing circuit board and mask film attachment hole drilling apparatus |
| JP2008053524A (en) * | 2006-08-25 | 2008-03-06 | Calsonic Kansei Corp | Apparatus for manufacturing circuit board |
| CN201245260Y (en) * | 2008-06-25 | 2009-05-27 | 瑞之路(厦门)眼镜科技有限公司 | Packing box for lens |
| CN101598901A (en) * | 2009-07-14 | 2009-12-09 | 昆山鼎鑫电子有限公司 | A kind of operational method of manual exposure machine |
| CN101772268A (en) * | 2009-12-22 | 2010-07-07 | 深圳市集锦线路板科技有限公司 | Technology for aligning circuit board by PIN nail |
| CN201742639U (en) * | 2010-08-06 | 2011-02-09 | 深圳崇达多层线路板有限公司 | Circuit board positioning device |
| CN101969746A (en) * | 2010-11-04 | 2011-02-09 | 沪士电子股份有限公司 | Method for removing electroplating copper locally in hollowed-out area of printed circuit board |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103345132A (en) * | 2013-06-25 | 2013-10-09 | 惠州中京电子科技股份有限公司 | Method for aligning outer layer film PIN nails |
| CN103345132B (en) * | 2013-06-25 | 2016-01-20 | 惠州中京电子科技股份有限公司 | A kind of outer film PIN follows closely the method for contraposition |
| CN105792529A (en) * | 2016-04-08 | 2016-07-20 | 梅州市中联精密电子有限公司 | Loose-leaf type circuit board Pin nail counterpoint technology |
| CN109587950A (en) * | 2018-11-28 | 2019-04-05 | 惠州中京电子科技有限公司 | A kind of low error PCB sawing sheet drillhole pattern localization method |
| CN109587950B (en) * | 2018-11-28 | 2020-08-04 | 惠州中京电子科技有限公司 | Low-error PCB cutting and drilling pattern positioning method |
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Application publication date: 20130403 |