CN102779820A - 半导体装置以及半导体元件 - Google Patents

半导体装置以及半导体元件 Download PDF

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CN102779820A
CN102779820A CN2012101962461A CN201210196246A CN102779820A CN 102779820 A CN102779820 A CN 102779820A CN 2012101962461 A CN2012101962461 A CN 2012101962461A CN 201210196246 A CN201210196246 A CN 201210196246A CN 102779820 A CN102779820 A CN 102779820A
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semiconductor
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CN102779820B (zh
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K.H.赫斯塞恩
齐藤省二
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Mitsubishi Electric Corp
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Abstract

本发明的目的在于提供能够减少开关损失的半导体装置以及半导体元件。本发明的半导体装置的特征在于，具备：半导体元件，该半导体元件具有：具有第一栅极并且以来自该第一栅极的信号控制导通截止的第一元件部和具有第二栅极并且以来自该第二栅极的信号控制导通截止的第二元件部；信号传输单元，与该第一栅极以及该第二栅极连接，并且以如下方式向该第一栅极和该第二栅极传输信号：在接通该半导体元件时，同时接通该第一元件部和该第二元件部，在关断该半导体元件时，使该第二元件部比该第一元件部延迟关断。

Description

半导体装置以及半导体元件
技术领域
本发明涉及在例如功率控制等中所使用的半导体装置以及半导体元件。
背景技术
在专利文献1中公开了包含根据栅极电压的有无来进行开关的半导体元件的半导体装置。
专利文献1：日本特开平04－280475号公报。
当半导体元件进行开关时，产生开关损失。为了减少开关损失，需要减少接通（turn-on）损失和关断（turn-off）损失。但是，由于接通损失和关断损失为折衷选择（trade-off）的关系，所以，不能够减少开关损失。
发明内容
本发明是为了解决上述那样的课题而提出的，其目的在于提供能够减少开关损失的半导体装置以及半导体元件。
本发明提供一种半导体装置，其特征在于，具备：半导体元件，该半导体元件具有：具有第一栅极并且以来自该第一栅极的信号控制导通截止的第一元件部和具有第二栅极并且以来自该第二栅极的信号控制导通截止的第二元件部；信号传输单元，与该第一栅极以及该第二栅极连接，并且以如下方式向该第一栅极和该第二栅极传输信号：在接通该半导体元件时，同时接通该第一元件部和该第二元件部，在关断该半导体元件时，使该第二元件部比该第一元件部延迟关断。
本发明提供一种半导体装置，其特征在于，具备：半导体元件，具有分别单独形成有栅极的多个元件部；信号传输单元，与该半导体元件的全部的栅极连接，在接通该半导体元件时，使该多个元件部的全部同时接通，在关断该半导体元件时，依次关断该多个元件部。
本发明提供一种半导体元件，其特征在于，具备：第一元件部，以来自第一栅极的信号控制导通截止；第二元件部，构成为以来自第二栅极的信号控制导通截止并且相对于该第一元件部延迟进行工作。
根据本发明，使多个元件部依次关断，所以，能够减少半导体装置的开关损失。
附图说明
图1是示出本发明的实施方式1的半导体装置的电路图。
图2是示出本发明的实施方式1的半导体装置的半导体元件的图。
图3是图2的虚线部的剖面图。
图4是示出本发明的实施方式1的半导体装置的工作的时序图。
图5是示出接通损失的图。
图6是示出关断损失的图。
图7是示出关断损失和元件部的面积的关系的图。
图8是示出本发明的实施方式1的半导体装置的变形例的图。
图9是示出本发明的实施方式2的半导体装置的半导体元件的图。
图10是示出本发明的实施方式3的半导体装置的半导体元件的图。
图11是示出图10的虚线部的温度分布的图。
图12是示出本发明的实施方式3的半导体元件的变形例的图。
图13是示出本发明的实施方式3的半导体元件的变形例的图。
图14是本发明的实施方式4的半导体元件的剖面图。
图15是示出第一元件部和第二元件部的规格的差异的图。
图16是示出对第一元件部和第二元件部的关断损失等进行模拟的结果的图。
图17是示出为了控制载流子的寿命而在n－层形成了寿命扼杀剂（lifetime killer）的图。
图18是本发明的实施方式5的半导体元件的剖面图。
图19是示出本发明的实施方式5的半导体元件的变形例的图。
图20是本发明的实施方式6的半导体元件的剖面图。
具体实施方式
实施方式1
图1是示出本发明的实施方式1的半导体装置的电路图。本发明的实施方式1的半导体装置具备第一元件部10和第二元件部12。以第一元件部10和第二元件部12形成一个半导体元件。第一元件部10的栅极（称为第一栅极）和第二元件部12的栅极（称为第二栅极）连接到信号传输单元14。信号传输单元14是分别向第一栅极和第二栅极提供信号的部分。
信号传输单元14具备接收驱动信号（Drive Signal）的IC16。IC16根据驱动信号，从输出1和输出2输出信号。来自输出1的信号使开关Q1和Q2导通，接通第一元件部10和第二元件部12。来自输出2的信号使开关Q3和Q4导通，关断第一元件部10和第二元件部12。
图2是示出本发明的实施方式1的半导体装置的半导体元件的图。第一元件部10和第二元件部12形成为一个芯片，成为一个半导体元件20。第一元件部10和第二元件部12的元件面积相等。对于第一元件部10来说，由来自第一栅极（G1）的信号来控制导通截止。对于第二元件部12来说，由来自第二栅极（G2）的信号来控制导通截止。即，第一元件部10和第二元件部12由不同的信号控制。
图3是图2的虚线部的剖面图。简化了栅极等的最表面的结构。半导体元件20由IGBT形成。半导体元件20具备n－层（漂移层）30。在n－层30的表面依次形成有基极层（base layer）32和沟道层34。在第一元件部10中以贯通基极层32和沟道层34的方式形成有栅极36a。多晶硅栅极36a与第一栅极（G1）连接。在第二元件部12中以贯通基极层32和沟道层34的方式形成有多晶硅栅极36b。多晶硅栅极36b与第二栅极（G2）连接。在n－层30的背面依次形成有缓冲层38和集电极层40。
接着，对本发明的实施方式1的半导体装置的工作进行说明。图4是示出本发明的实施方式1的半导体装置的工作的时序图。时刻t1是接通半导体元件20的时刻。在时刻t1，从外部向IC16传输驱动信号（DS）。IC16从输出1送出信号，使第一栅极（G1）和第二栅极（G2）的信号同时为高（HIGH）。由此，使第一元件部10和第二元件部12同时接通。
时刻t2是关断第一元件部10的时刻。在时刻t2，切断从外部向IC16的驱动信号（DS）。并且，IC16的输出2送出信号，使第一栅极（G1）的信号为低（LOW）。由此，第一元件部10关断。
从时刻t2到时刻t3是从输出1和输出2这两者输出信号的期间。在该期间，来自输出2的信号被延迟电路DLY2延迟，开关Q4成为截止状态。因此，在该期间中，第二元件部12维持导通状态。
时刻t3是关断第二元件部12的时刻。在时刻t3，切断来自输出1的信号。并且，来自输出2的信号使第二元件部12关断。在时刻t3，第一元件部10和第二元件部12都被关断，完成半导体元件20的关断。
这样，在接通半导体元件20时，同时接通第一元件部10和第二元件部12。另一方面，在关断半导体元件20时，使第二元件部12比第一元件部10延迟关断。
本发明的实施方式1的半导体装置减少接通时以及关断时的开关损失。首先，对接通时的开关损失（称为接通损失）进行说明。图5是示出接通损失的图。在图5中，2P同时接通是指同时接通第一元件部10和第二元件部12。2P错开时间接通是指使第一元件部10和第二元件部12的任一个相对于另一个延迟接通。
根据图5可知，能够减少接通损失的是2P同时接通的情况。即，当用大面积的元件部接通半导体元件时能够减少接通损失。根据本发明的实施方式1的半导体装置，同时接通第一元件部10和第二元件部12，所以，能够减少接通损失。
接着，对关断时的开关损失（称为关断损失）进行说明。图6是示出关断损失的图。在图6中，2P同时关断是指同时关断第一元件部10和第二元件部12。2P错开时间关断是指使第二元件部12比第一元件部10延迟关断。
根据图6可知，能够减少关断损失的是2P错开时间关断的情况。2P错开时间关断实质上是仅以第二元件部12进行关断工作，与第一、第二元件部这两者关断时相比，元件面积为小面积。即，越使关断时的元件部的面积变小，越能够减少关断损失。根据本发明的实施方式1的半导体装置，使第二元件部12比第一元件部10延迟关断，所以，能够减少关断损失。
图7是示出关断损失和元件部的面积的关系的图。使用元件A、元件B以及元件C这三个元件测定关断损失。当将元件A的面积设为100时，元件B的面积为66.7，元件C的面积为33.3。根据图7可知，元件面积越小越能够减少关断损失（EOFF）。根据该结果也可知，越是元件面积小的半导体元件越能够减少关断损失。
根据本发明的实施方式1的半导体装置，能够减少接通损失和关断损失这两者，所以，能够减少半导体装置的开关损失。
本发明的实施方式1的半导体装置能够进行各种变形。半导体元件20分割为第一元件部10和第二元件部12两个元件部，但是，也可以将其分割为分别单独形成有栅极的三个以上的多个元件部。在该情况下，在接通半导体元件时，使全部的元件部同时接通，在关断半导体元件时，使各元件部依次关断。
图8是示出本发明的实施方式1的半导体装置的变形例的图。在图8中示出在第一元件部10形成有感测焊盘10a的半导体元件60。设置感测焊盘10a，由此，能够检查在半导体元件接通时有无短路并能够进行过电流保护等。
实施方式2
图9是示出本发明的实施方式2的半导体装置的半导体元件的图。半导体元件70具有第一元件部72和第二元件部74。第二元件部74以与第一元件部72相比为大面积的方式形成。关于半导体装置的在图9中未示出的部分以及半导体装置的工作，与实施方式1相同。
在实施方式1的半导体元件中，存在如下情况：在关断时，第二元件部的电流密度上升，第二元件部恶化。但是，根据本发明的实施方式2的半导体元件，第二元件部74为比较大的面积，所以，能够减少关断时的电流密度。因此，能够防止第二元件部74的恶化。此外，与实施方式1相同，能够减少开关损失。再有，本发明的实施方式2的半导体元件能够进行至少与实施方式1相同程度的变形。
实施方式3
图10是示出本发明的实施方式3的半导体装置的半导体元件的图。半导体元件80具有第一元件部82和第二元件部84。第二元件部84以包围第一元件部82的方式形成。第一元件部82的面积和第二元件部84的面积相等。关于半导体装置的在图10中未示出的部分以及半导体装置的工作，与实施方式1相同。
半导体元件由于关断损失而发热。半导体元件的中央部的散热困难，容易成为高温。另一方面，半导体元件的外周部能够向半导体元件的周围散热，所以，难以成为高温。因此，存在半导体元件的中央部成为高温而使半导体元件恶化的情况。
但是，在本发明的实施方式3的半导体元件中，半导体元件80的中央部的第一元件部82比第二元件部84先关断，所以，第一元件部82的发热量比第二元件部84的发热量少。因此，能够防止半导体元件80的中央部成为高温。
图11是示出图10的虚线部的温度分布的图。实线表示先关断第一元件部82之后关断第二元件部84的情况下的温度分布。虚线表示同时关断第一元件部82和第二元件部84的情况下的温度分布。根据图11可知，若先关断半导体元件80的中央部（P2）的第一元件部82，则能够降低半导体元件80的中央部（P2）的温度。
图12是示出本发明的实施方式3的半导体元件的变形例的图。在半导体元件90的中央部形成有第一元件部92。在半导体元件90的外周部形成有第二元件部94。第二元件部94的面积比第一元件部92的面积大。由此，能够进一步减少第一元件部92的发热量，能够降低半导体元件90的中央部的温度。此外，第二元件部94为大面积，所以，也能够降低第二元件部94的温度。
图13是示出本发明的实施方式3的半导体元件的变形例的图。在第一元件部82形成有感测焊盘82a。设置感测焊盘82a，由此，能够检查在半导体元件接通时有无短路，能够进行过电流保护等。再有，本发明的实施方式3的半导体元件能够进行至少与实施方式1相同程度的变形。
实施方式4
本发明的实施方式4的半导体元件的特征在于，在第一元件部和第二元件部使开关速度变化。图14是本发明的实施方式4的半导体元件的剖面图。半导体元件是从集电极层40a以及40b向漂移层30注入载流子的电导率调制型的半导体元件。图14示出的剖面图和图3示出的剖面图的不同点是集电极层。再有，关于半导体装置的在图14中未示出的部分以及半导体装置的工作，与实施方式1相同。
第一元件部10以提高第一集电极层40a的杂质浓度而成为低速规格的方式形成。低速规格是稳态损失EVce低、关断损失Eoff高的规格。另一方面，第二元件部12以使第二集电极层40b的杂质浓度比第一集电极层40a减少而成为高速规格的方式形成。高速规格是指稳态损失EVce高、关断损失低的规格。
图15是示出第一元件部10和第二元件部12的规格的差异的图。第一元件部10为低速规格，第二元件部12为高速规格。第二元件部12与第一元件部10相比以高速进行开关，所以，关断损失（Eoff）变低。
但是，占据半导体装置的关断损失的大部分的是比第一元件部10晚关断的第二元件部12。图16是示出对第一元件部和第二元件部的关断损失（Eoff）等进行模拟的结果的图。图16的虚线是第一元件部10的波形，实线是第二元件部12的波形。根据Eoff波形可知，半导体装置的关断损失大体上由第二元件部12产生。这是因为，先关断第一元件部10，由此，被第一元件部10和第二元件部12分担的电流在第二元件部12集中。
根据本发明的实施方式4的半导体装置，占据关断损失的大部分的第二元件部12以高速规格形成，所以，能够减少第二元件部12的关断损失。因此，能够减少半导体装置整体的开关损失。
在本发明的实施方式4的半导体元件中，使第二集电极层40b的杂质浓度比第一集电极层40a的杂质浓度低。但是，也可以以其他方法形成低速规格的元件部和高速规格的元件部。例如，变更栅极的间隔、沟道长度、缓冲层的厚度或浓度、或者集电极层的厚度，由此，能够形成低速规格的元件部和高速规格的元件部。
图17是示出为了控制载流子的寿命而在n－层形成寿命扼杀剂的图。在第二元件部12的n－层30b形成有寿命扼杀剂110。寿命扼杀剂110利用Au或Pt的导入、或者电子束照射形成。
利用寿命扼杀剂110使第二元件部12的少数载流子的寿命比第一元件部10的少数载流子的寿命短。因此，能够使第二元件部12与第一元件部10相比为高速规格。
再有，如果与第二元件部12的寿命扼杀剂相比为低密度，则也可以在第一元件部10的n－层30a形成寿命扼杀剂。即，如果在第二元件部12以比第一元件部10高的密度形成载流子的寿命扼杀剂，则能够得到本发明的效果。此外，本发明的实施方式4的半导体元件能够进行至少与实施方式1相同程度的变形。
实施方式5
本发明的实施方式5的半导体元件的特征在于，第一元件部和第二元件部的阈值电压不同。图18是本发明的实施方式5的半导体元件的剖面图。向栅极G1以及G2传输相同的信号。
第一元件部10以成为第一阈值电压的方式形成。此外，第二元件部12以具有比第一阈值电压高的第二阈值电压的方式形成。阈值电压的差是通过使沟道层34a的杂质浓度比沟道层34b的杂质浓度低而产生的。
根据本发明的实施方式5的半导体元件，对第一栅极（G1）和第二栅极（G2）使用相同的信号并且能够使第二元件部12相对于第一元件部10延迟驱动。即，能够使第二元件部12相对于第一元件部10延迟关断。因此，能够减少开关损失。此外，能够在第一元件部10和第二元件部12中使用相同的信号，所以，能够简化信号传输单元的结构。
在本发明的实施方式5的半导体元件中，调整了沟道层的杂质浓度，但是，本发明不限定于此。只要具备向栅极传输信号来进行导通截止的控制的第一元件部和以利用与该信号相同的信号进行导通截止的控制并且相对于第一元件部延迟进行工作的方式构成的第二元件部，就能够得到本发明的效果。
图19是示出本发明的实施方式5的半导体元件的变形例的图。第一元件部10的栅极氧化膜39a形成得比第二元件部12的栅极氧化膜39b薄。因此，能够使第二元件部12相对于第一元件部10延迟关断。
实施方式6
本发明的实施方式6的半导体元件的特征在于，第一元件部和第二元件部的CR时间常数不同。图20是本发明的实施方式6的半导体元件的剖面图。向第一栅极（G1）以及第二栅极（G2）传输相同的信号。
多晶硅栅极36a和多晶硅栅极36b由不同的材料形成。因此，第二元件部12的栅极电阻比第一元件部10的栅极电阻高。并且，第一元件部10的基极层32a的杂质量比第二元件部12的基极层32b的杂质量少。此外，沟道层34a的杂质量比沟道层34b的杂质量少。因此，第二元件部12的内部电容比第一元件部10的内部电容高。
因此，第一元件部10具有第一CR时间常数，第二元件部12具有比第一CR时间常数大的第二CR时间常数。
由此，能够使第二元件部12相对于第一元件部10延迟开关。由于能够使第二元件部12比第一元件部延迟关断，所以，能够减少半导体元件的开关损失。此外，由于能够在第一元件部10和第二元件部12中使用相同的信号，所以，能够简化信号传输单元的结构。
在之前的全部的实施方式中，半导体元件采用作为少数载流子（双极（bipolar））器件的IGBT。但是，作为半导体元件，也可以使用如MOSFET那样的多数载流子（单极（unipolar））器件。多数载流子器件开关速度快，所以，与少数载流子器件相比能够期待开关损失的减少。
半导体元件可以由硅形成，但是，也可以由带隙比硅大的宽带隙半导体形成。作为宽带隙半导体，例如有碳化硅、氮化镓类材料或者金刚石。
附图标记的说明：
10  第一元件部
10a  感测焊盘
12  第二元件部
14  信号传输单元
16  IC
20  半导体元件
G1  第一栅极
G2  第二栅极。

Claims (13)

1.一种半导体装置，其特征在于，具备：
半导体元件，该半导体元件具有：具有第一栅极并且以来自所述第一栅极的信号控制导通截止的第一元件部和具有第二栅极并且以来自所述第二栅极的信号控制导通截止的第二元件部；以及
信号传输单元，与所述第一栅极以及所述第二栅极连接，并且以如下方式向所述第一栅极和所述第二栅极传输信号：在接通所述半导体元件时，同时接通所述第一元件部和所述第二元件部，在关断所述半导体元件时，使所述第二元件部比所述第一元件部延迟关断。
2.根据权利要求1所述的半导体装置，其特征在于，
所述第二元件部的面积比所述第一元件部的面积大。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述第二元件部以包围所述第一元件部的方式形成。
4.根据权利要求1或2所述的半导体装置，其特征在于，
所述第二元件部以与所述第一元件部相比以高速进行开关的方式构成。
5.根据权利要求4所述的半导体装置，其特征在于，
所述半导体元件是从集电极层向漂移层注入载流子的电导率调制型的半导体元件，
所述半导体装置具备：
第一集电极层，形成在所述第一元件部；以及
第二集电极层，形成在所述第二元件部，
所述第二集电极层的杂质浓度比所述第一集电极层的杂质浓度低。
6.根据权利要求4所述的半导体装置，其特征在于，
在所述第二元件部以比所述第一元件部高的密度形成有载流子的寿命扼杀剂。
7.根据权利要求1所述的半导体装置，其特征在于，
具备形成于所述半导体元件的感测焊盘。
8.一种半导体装置，其特征在于，具备：
半导体元件，具有分别单独形成有栅极的多个元件部；以及
信号传输单元，与所述半导体元件的全部的栅极连接，在接通所述半导体元件时，使所述多个元件部的全部同时接通，在关断所述半导体元件时，依次关断所述多个元件部。
9.根据权利要求1或8所述的半导体装置，其特征在于，
所述半导体元件由宽带隙半导体形成。
10.根据权利要求9所述的半导体装置，其特征在于，
所述宽带隙半导体是碳化硅、氮化镓类材料或者金刚石。
11.一种半导体元件，其特征在于，具备：
第一元件部，以来自第一栅极的信号控制导通截止；以及
第二元件部，构成为以来自第二栅极的信号控制导通截止并且相对于所述第一元件部延迟进行工作。
12.根据权利要求11所述的半导体元件，其特征在于，
所述半导体元件由宽带隙半导体形成。
13.根据权利要求12所述的半导体元件，其特征在于，
所述宽带隙半导体是碳化硅、氮化镓类材料或者金刚石。
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CN105577153A (zh) * 2014-10-31 2016-05-11 富士电机株式会社 半导体装置
CN110062957A (zh) * 2016-12-12 2019-07-26 三菱电机株式会社 半导体装置的驱动方法以及驱动电路
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